fsl-imx8qm-lpddr4-arm2-hdmi.dts
2.24 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
/*
* Copyright 2017-2018 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* HDMI only dts, disable ldb display.
*/
#include "fsl-imx8qm-lpddr4-arm2.dts"
/ {
sound-hdmi-tx {
compatible = "fsl,imx-audio-cdnhdmi";
model = "imx-audio-hdmi-tx";
audio-cpu = <&sai_hdmi_tx>;
constraint-rate = <48000>;
protocol = <1>;
hdmi-out;
};
sound-amix-sai {
status = "disabled";
};
sound-hdmi-arc {
compatible = "fsl,imx-audio-spdif";
model = "imx-hdmi-arc";
spdif-controller = <&spdif1>;
spdif-in;
spdif-out;
};
};
&ldb1_phy {
status = "disabled";
};
&ldb1 {
status = "disabled";
};
&i2c1_lvds0 {
status = "disabled";
};
&irqsteer_hdmi {
status = "okay";
};
&hdmi {
compatible = "fsl,imx8qm-hdmi";
assigned-clocks = <&clk IMX8QM_HDMI_PXL_SEL>,
<&clk IMX8QM_HDMI_PXL_LINK_SEL>,
<&clk IMX8QM_HDMI_PXL_MUX_SEL>;
assigned-clock-parents = <&clk IMX8QM_HDMI_AV_PLL_CLK>,
<&clk IMX8QM_HDMI_AV_PLL_CLK>,
<&clk IMX8QM_HDMI_AV_PLL_CLK>;
fsl,no_edid;
status = "okay";
};
&amix {
status = "disabled";
};
&sai6 {
status = "disabled";
};
&sai7 {
status = "disabled";
};
&sai_hdmi_tx {
assigned-clocks =<&clk IMX8QM_ACM_HDMI_TX_SAI0_MCLK_SEL>,
<&clk IMX8QM_AUD_PLL1_DIV>,
<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>,
<&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>,
<&clk IMX8QM_AUD_SAI_HDMITX0_MCLK>;
assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>;
assigned-clock-rates = <0>, <768000000>, <768000000>, <768000000>, <768000000>;
fsl,sai-asynchronous;
status = "okay";
};
&sai_hdmi_rx {
fsl,sai-asynchronous;
status = "okay";
};
&spdif1 {
assigned-clocks =<&clk IMX8QM_AUD_PLL0_DIV>,
<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>,
<&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>;
assigned-clock-rates = <786432000>, <49152000>, <12288000>;
status = "okay";
};