synclink.c
230 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641
3642
3643
3644
3645
3646
3647
3648
3649
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
3750
3751
3752
3753
3754
3755
3756
3757
3758
3759
3760
3761
3762
3763
3764
3765
3766
3767
3768
3769
3770
3771
3772
3773
3774
3775
3776
3777
3778
3779
3780
3781
3782
3783
3784
3785
3786
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809
3810
3811
3812
3813
3814
3815
3816
3817
3818
3819
3820
3821
3822
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836
3837
3838
3839
3840
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850
3851
3852
3853
3854
3855
3856
3857
3858
3859
3860
3861
3862
3863
3864
3865
3866
3867
3868
3869
3870
3871
3872
3873
3874
3875
3876
3877
3878
3879
3880
3881
3882
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895
3896
3897
3898
3899
3900
3901
3902
3903
3904
3905
3906
3907
3908
3909
3910
3911
3912
3913
3914
3915
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932
3933
3934
3935
3936
3937
3938
3939
3940
3941
3942
3943
3944
3945
3946
3947
3948
3949
3950
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960
3961
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971
3972
3973
3974
3975
3976
3977
3978
3979
3980
3981
3982
3983
3984
3985
3986
3987
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999
4000
4001
4002
4003
4004
4005
4006
4007
4008
4009
4010
4011
4012
4013
4014
4015
4016
4017
4018
4019
4020
4021
4022
4023
4024
4025
4026
4027
4028
4029
4030
4031
4032
4033
4034
4035
4036
4037
4038
4039
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049
4050
4051
4052
4053
4054
4055
4056
4057
4058
4059
4060
4061
4062
4063
4064
4065
4066
4067
4068
4069
4070
4071
4072
4073
4074
4075
4076
4077
4078
4079
4080
4081
4082
4083
4084
4085
4086
4087
4088
4089
4090
4091
4092
4093
4094
4095
4096
4097
4098
4099
4100
4101
4102
4103
4104
4105
4106
4107
4108
4109
4110
4111
4112
4113
4114
4115
4116
4117
4118
4119
4120
4121
4122
4123
4124
4125
4126
4127
4128
4129
4130
4131
4132
4133
4134
4135
4136
4137
4138
4139
4140
4141
4142
4143
4144
4145
4146
4147
4148
4149
4150
4151
4152
4153
4154
4155
4156
4157
4158
4159
4160
4161
4162
4163
4164
4165
4166
4167
4168
4169
4170
4171
4172
4173
4174
4175
4176
4177
4178
4179
4180
4181
4182
4183
4184
4185
4186
4187
4188
4189
4190
4191
4192
4193
4194
4195
4196
4197
4198
4199
4200
4201
4202
4203
4204
4205
4206
4207
4208
4209
4210
4211
4212
4213
4214
4215
4216
4217
4218
4219
4220
4221
4222
4223
4224
4225
4226
4227
4228
4229
4230
4231
4232
4233
4234
4235
4236
4237
4238
4239
4240
4241
4242
4243
4244
4245
4246
4247
4248
4249
4250
4251
4252
4253
4254
4255
4256
4257
4258
4259
4260
4261
4262
4263
4264
4265
4266
4267
4268
4269
4270
4271
4272
4273
4274
4275
4276
4277
4278
4279
4280
4281
4282
4283
4284
4285
4286
4287
4288
4289
4290
4291
4292
4293
4294
4295
4296
4297
4298
4299
4300
4301
4302
4303
4304
4305
4306
4307
4308
4309
4310
4311
4312
4313
4314
4315
4316
4317
4318
4319
4320
4321
4322
4323
4324
4325
4326
4327
4328
4329
4330
4331
4332
4333
4334
4335
4336
4337
4338
4339
4340
4341
4342
4343
4344
4345
4346
4347
4348
4349
4350
4351
4352
4353
4354
4355
4356
4357
4358
4359
4360
4361
4362
4363
4364
4365
4366
4367
4368
4369
4370
4371
4372
4373
4374
4375
4376
4377
4378
4379
4380
4381
4382
4383
4384
4385
4386
4387
4388
4389
4390
4391
4392
4393
4394
4395
4396
4397
4398
4399
4400
4401
4402
4403
4404
4405
4406
4407
4408
4409
4410
4411
4412
4413
4414
4415
4416
4417
4418
4419
4420
4421
4422
4423
4424
4425
4426
4427
4428
4429
4430
4431
4432
4433
4434
4435
4436
4437
4438
4439
4440
4441
4442
4443
4444
4445
4446
4447
4448
4449
4450
4451
4452
4453
4454
4455
4456
4457
4458
4459
4460
4461
4462
4463
4464
4465
4466
4467
4468
4469
4470
4471
4472
4473
4474
4475
4476
4477
4478
4479
4480
4481
4482
4483
4484
4485
4486
4487
4488
4489
4490
4491
4492
4493
4494
4495
4496
4497
4498
4499
4500
4501
4502
4503
4504
4505
4506
4507
4508
4509
4510
4511
4512
4513
4514
4515
4516
4517
4518
4519
4520
4521
4522
4523
4524
4525
4526
4527
4528
4529
4530
4531
4532
4533
4534
4535
4536
4537
4538
4539
4540
4541
4542
4543
4544
4545
4546
4547
4548
4549
4550
4551
4552
4553
4554
4555
4556
4557
4558
4559
4560
4561
4562
4563
4564
4565
4566
4567
4568
4569
4570
4571
4572
4573
4574
4575
4576
4577
4578
4579
4580
4581
4582
4583
4584
4585
4586
4587
4588
4589
4590
4591
4592
4593
4594
4595
4596
4597
4598
4599
4600
4601
4602
4603
4604
4605
4606
4607
4608
4609
4610
4611
4612
4613
4614
4615
4616
4617
4618
4619
4620
4621
4622
4623
4624
4625
4626
4627
4628
4629
4630
4631
4632
4633
4634
4635
4636
4637
4638
4639
4640
4641
4642
4643
4644
4645
4646
4647
4648
4649
4650
4651
4652
4653
4654
4655
4656
4657
4658
4659
4660
4661
4662
4663
4664
4665
4666
4667
4668
4669
4670
4671
4672
4673
4674
4675
4676
4677
4678
4679
4680
4681
4682
4683
4684
4685
4686
4687
4688
4689
4690
4691
4692
4693
4694
4695
4696
4697
4698
4699
4700
4701
4702
4703
4704
4705
4706
4707
4708
4709
4710
4711
4712
4713
4714
4715
4716
4717
4718
4719
4720
4721
4722
4723
4724
4725
4726
4727
4728
4729
4730
4731
4732
4733
4734
4735
4736
4737
4738
4739
4740
4741
4742
4743
4744
4745
4746
4747
4748
4749
4750
4751
4752
4753
4754
4755
4756
4757
4758
4759
4760
4761
4762
4763
4764
4765
4766
4767
4768
4769
4770
4771
4772
4773
4774
4775
4776
4777
4778
4779
4780
4781
4782
4783
4784
4785
4786
4787
4788
4789
4790
4791
4792
4793
4794
4795
4796
4797
4798
4799
4800
4801
4802
4803
4804
4805
4806
4807
4808
4809
4810
4811
4812
4813
4814
4815
4816
4817
4818
4819
4820
4821
4822
4823
4824
4825
4826
4827
4828
4829
4830
4831
4832
4833
4834
4835
4836
4837
4838
4839
4840
4841
4842
4843
4844
4845
4846
4847
4848
4849
4850
4851
4852
4853
4854
4855
4856
4857
4858
4859
4860
4861
4862
4863
4864
4865
4866
4867
4868
4869
4870
4871
4872
4873
4874
4875
4876
4877
4878
4879
4880
4881
4882
4883
4884
4885
4886
4887
4888
4889
4890
4891
4892
4893
4894
4895
4896
4897
4898
4899
4900
4901
4902
4903
4904
4905
4906
4907
4908
4909
4910
4911
4912
4913
4914
4915
4916
4917
4918
4919
4920
4921
4922
4923
4924
4925
4926
4927
4928
4929
4930
4931
4932
4933
4934
4935
4936
4937
4938
4939
4940
4941
4942
4943
4944
4945
4946
4947
4948
4949
4950
4951
4952
4953
4954
4955
4956
4957
4958
4959
4960
4961
4962
4963
4964
4965
4966
4967
4968
4969
4970
4971
4972
4973
4974
4975
4976
4977
4978
4979
4980
4981
4982
4983
4984
4985
4986
4987
4988
4989
4990
4991
4992
4993
4994
4995
4996
4997
4998
4999
5000
5001
5002
5003
5004
5005
5006
5007
5008
5009
5010
5011
5012
5013
5014
5015
5016
5017
5018
5019
5020
5021
5022
5023
5024
5025
5026
5027
5028
5029
5030
5031
5032
5033
5034
5035
5036
5037
5038
5039
5040
5041
5042
5043
5044
5045
5046
5047
5048
5049
5050
5051
5052
5053
5054
5055
5056
5057
5058
5059
5060
5061
5062
5063
5064
5065
5066
5067
5068
5069
5070
5071
5072
5073
5074
5075
5076
5077
5078
5079
5080
5081
5082
5083
5084
5085
5086
5087
5088
5089
5090
5091
5092
5093
5094
5095
5096
5097
5098
5099
5100
5101
5102
5103
5104
5105
5106
5107
5108
5109
5110
5111
5112
5113
5114
5115
5116
5117
5118
5119
5120
5121
5122
5123
5124
5125
5126
5127
5128
5129
5130
5131
5132
5133
5134
5135
5136
5137
5138
5139
5140
5141
5142
5143
5144
5145
5146
5147
5148
5149
5150
5151
5152
5153
5154
5155
5156
5157
5158
5159
5160
5161
5162
5163
5164
5165
5166
5167
5168
5169
5170
5171
5172
5173
5174
5175
5176
5177
5178
5179
5180
5181
5182
5183
5184
5185
5186
5187
5188
5189
5190
5191
5192
5193
5194
5195
5196
5197
5198
5199
5200
5201
5202
5203
5204
5205
5206
5207
5208
5209
5210
5211
5212
5213
5214
5215
5216
5217
5218
5219
5220
5221
5222
5223
5224
5225
5226
5227
5228
5229
5230
5231
5232
5233
5234
5235
5236
5237
5238
5239
5240
5241
5242
5243
5244
5245
5246
5247
5248
5249
5250
5251
5252
5253
5254
5255
5256
5257
5258
5259
5260
5261
5262
5263
5264
5265
5266
5267
5268
5269
5270
5271
5272
5273
5274
5275
5276
5277
5278
5279
5280
5281
5282
5283
5284
5285
5286
5287
5288
5289
5290
5291
5292
5293
5294
5295
5296
5297
5298
5299
5300
5301
5302
5303
5304
5305
5306
5307
5308
5309
5310
5311
5312
5313
5314
5315
5316
5317
5318
5319
5320
5321
5322
5323
5324
5325
5326
5327
5328
5329
5330
5331
5332
5333
5334
5335
5336
5337
5338
5339
5340
5341
5342
5343
5344
5345
5346
5347
5348
5349
5350
5351
5352
5353
5354
5355
5356
5357
5358
5359
5360
5361
5362
5363
5364
5365
5366
5367
5368
5369
5370
5371
5372
5373
5374
5375
5376
5377
5378
5379
5380
5381
5382
5383
5384
5385
5386
5387
5388
5389
5390
5391
5392
5393
5394
5395
5396
5397
5398
5399
5400
5401
5402
5403
5404
5405
5406
5407
5408
5409
5410
5411
5412
5413
5414
5415
5416
5417
5418
5419
5420
5421
5422
5423
5424
5425
5426
5427
5428
5429
5430
5431
5432
5433
5434
5435
5436
5437
5438
5439
5440
5441
5442
5443
5444
5445
5446
5447
5448
5449
5450
5451
5452
5453
5454
5455
5456
5457
5458
5459
5460
5461
5462
5463
5464
5465
5466
5467
5468
5469
5470
5471
5472
5473
5474
5475
5476
5477
5478
5479
5480
5481
5482
5483
5484
5485
5486
5487
5488
5489
5490
5491
5492
5493
5494
5495
5496
5497
5498
5499
5500
5501
5502
5503
5504
5505
5506
5507
5508
5509
5510
5511
5512
5513
5514
5515
5516
5517
5518
5519
5520
5521
5522
5523
5524
5525
5526
5527
5528
5529
5530
5531
5532
5533
5534
5535
5536
5537
5538
5539
5540
5541
5542
5543
5544
5545
5546
5547
5548
5549
5550
5551
5552
5553
5554
5555
5556
5557
5558
5559
5560
5561
5562
5563
5564
5565
5566
5567
5568
5569
5570
5571
5572
5573
5574
5575
5576
5577
5578
5579
5580
5581
5582
5583
5584
5585
5586
5587
5588
5589
5590
5591
5592
5593
5594
5595
5596
5597
5598
5599
5600
5601
5602
5603
5604
5605
5606
5607
5608
5609
5610
5611
5612
5613
5614
5615
5616
5617
5618
5619
5620
5621
5622
5623
5624
5625
5626
5627
5628
5629
5630
5631
5632
5633
5634
5635
5636
5637
5638
5639
5640
5641
5642
5643
5644
5645
5646
5647
5648
5649
5650
5651
5652
5653
5654
5655
5656
5657
5658
5659
5660
5661
5662
5663
5664
5665
5666
5667
5668
5669
5670
5671
5672
5673
5674
5675
5676
5677
5678
5679
5680
5681
5682
5683
5684
5685
5686
5687
5688
5689
5690
5691
5692
5693
5694
5695
5696
5697
5698
5699
5700
5701
5702
5703
5704
5705
5706
5707
5708
5709
5710
5711
5712
5713
5714
5715
5716
5717
5718
5719
5720
5721
5722
5723
5724
5725
5726
5727
5728
5729
5730
5731
5732
5733
5734
5735
5736
5737
5738
5739
5740
5741
5742
5743
5744
5745
5746
5747
5748
5749
5750
5751
5752
5753
5754
5755
5756
5757
5758
5759
5760
5761
5762
5763
5764
5765
5766
5767
5768
5769
5770
5771
5772
5773
5774
5775
5776
5777
5778
5779
5780
5781
5782
5783
5784
5785
5786
5787
5788
5789
5790
5791
5792
5793
5794
5795
5796
5797
5798
5799
5800
5801
5802
5803
5804
5805
5806
5807
5808
5809
5810
5811
5812
5813
5814
5815
5816
5817
5818
5819
5820
5821
5822
5823
5824
5825
5826
5827
5828
5829
5830
5831
5832
5833
5834
5835
5836
5837
5838
5839
5840
5841
5842
5843
5844
5845
5846
5847
5848
5849
5850
5851
5852
5853
5854
5855
5856
5857
5858
5859
5860
5861
5862
5863
5864
5865
5866
5867
5868
5869
5870
5871
5872
5873
5874
5875
5876
5877
5878
5879
5880
5881
5882
5883
5884
5885
5886
5887
5888
5889
5890
5891
5892
5893
5894
5895
5896
5897
5898
5899
5900
5901
5902
5903
5904
5905
5906
5907
5908
5909
5910
5911
5912
5913
5914
5915
5916
5917
5918
5919
5920
5921
5922
5923
5924
5925
5926
5927
5928
5929
5930
5931
5932
5933
5934
5935
5936
5937
5938
5939
5940
5941
5942
5943
5944
5945
5946
5947
5948
5949
5950
5951
5952
5953
5954
5955
5956
5957
5958
5959
5960
5961
5962
5963
5964
5965
5966
5967
5968
5969
5970
5971
5972
5973
5974
5975
5976
5977
5978
5979
5980
5981
5982
5983
5984
5985
5986
5987
5988
5989
5990
5991
5992
5993
5994
5995
5996
5997
5998
5999
6000
6001
6002
6003
6004
6005
6006
6007
6008
6009
6010
6011
6012
6013
6014
6015
6016
6017
6018
6019
6020
6021
6022
6023
6024
6025
6026
6027
6028
6029
6030
6031
6032
6033
6034
6035
6036
6037
6038
6039
6040
6041
6042
6043
6044
6045
6046
6047
6048
6049
6050
6051
6052
6053
6054
6055
6056
6057
6058
6059
6060
6061
6062
6063
6064
6065
6066
6067
6068
6069
6070
6071
6072
6073
6074
6075
6076
6077
6078
6079
6080
6081
6082
6083
6084
6085
6086
6087
6088
6089
6090
6091
6092
6093
6094
6095
6096
6097
6098
6099
6100
6101
6102
6103
6104
6105
6106
6107
6108
6109
6110
6111
6112
6113
6114
6115
6116
6117
6118
6119
6120
6121
6122
6123
6124
6125
6126
6127
6128
6129
6130
6131
6132
6133
6134
6135
6136
6137
6138
6139
6140
6141
6142
6143
6144
6145
6146
6147
6148
6149
6150
6151
6152
6153
6154
6155
6156
6157
6158
6159
6160
6161
6162
6163
6164
6165
6166
6167
6168
6169
6170
6171
6172
6173
6174
6175
6176
6177
6178
6179
6180
6181
6182
6183
6184
6185
6186
6187
6188
6189
6190
6191
6192
6193
6194
6195
6196
6197
6198
6199
6200
6201
6202
6203
6204
6205
6206
6207
6208
6209
6210
6211
6212
6213
6214
6215
6216
6217
6218
6219
6220
6221
6222
6223
6224
6225
6226
6227
6228
6229
6230
6231
6232
6233
6234
6235
6236
6237
6238
6239
6240
6241
6242
6243
6244
6245
6246
6247
6248
6249
6250
6251
6252
6253
6254
6255
6256
6257
6258
6259
6260
6261
6262
6263
6264
6265
6266
6267
6268
6269
6270
6271
6272
6273
6274
6275
6276
6277
6278
6279
6280
6281
6282
6283
6284
6285
6286
6287
6288
6289
6290
6291
6292
6293
6294
6295
6296
6297
6298
6299
6300
6301
6302
6303
6304
6305
6306
6307
6308
6309
6310
6311
6312
6313
6314
6315
6316
6317
6318
6319
6320
6321
6322
6323
6324
6325
6326
6327
6328
6329
6330
6331
6332
6333
6334
6335
6336
6337
6338
6339
6340
6341
6342
6343
6344
6345
6346
6347
6348
6349
6350
6351
6352
6353
6354
6355
6356
6357
6358
6359
6360
6361
6362
6363
6364
6365
6366
6367
6368
6369
6370
6371
6372
6373
6374
6375
6376
6377
6378
6379
6380
6381
6382
6383
6384
6385
6386
6387
6388
6389
6390
6391
6392
6393
6394
6395
6396
6397
6398
6399
6400
6401
6402
6403
6404
6405
6406
6407
6408
6409
6410
6411
6412
6413
6414
6415
6416
6417
6418
6419
6420
6421
6422
6423
6424
6425
6426
6427
6428
6429
6430
6431
6432
6433
6434
6435
6436
6437
6438
6439
6440
6441
6442
6443
6444
6445
6446
6447
6448
6449
6450
6451
6452
6453
6454
6455
6456
6457
6458
6459
6460
6461
6462
6463
6464
6465
6466
6467
6468
6469
6470
6471
6472
6473
6474
6475
6476
6477
6478
6479
6480
6481
6482
6483
6484
6485
6486
6487
6488
6489
6490
6491
6492
6493
6494
6495
6496
6497
6498
6499
6500
6501
6502
6503
6504
6505
6506
6507
6508
6509
6510
6511
6512
6513
6514
6515
6516
6517
6518
6519
6520
6521
6522
6523
6524
6525
6526
6527
6528
6529
6530
6531
6532
6533
6534
6535
6536
6537
6538
6539
6540
6541
6542
6543
6544
6545
6546
6547
6548
6549
6550
6551
6552
6553
6554
6555
6556
6557
6558
6559
6560
6561
6562
6563
6564
6565
6566
6567
6568
6569
6570
6571
6572
6573
6574
6575
6576
6577
6578
6579
6580
6581
6582
6583
6584
6585
6586
6587
6588
6589
6590
6591
6592
6593
6594
6595
6596
6597
6598
6599
6600
6601
6602
6603
6604
6605
6606
6607
6608
6609
6610
6611
6612
6613
6614
6615
6616
6617
6618
6619
6620
6621
6622
6623
6624
6625
6626
6627
6628
6629
6630
6631
6632
6633
6634
6635
6636
6637
6638
6639
6640
6641
6642
6643
6644
6645
6646
6647
6648
6649
6650
6651
6652
6653
6654
6655
6656
6657
6658
6659
6660
6661
6662
6663
6664
6665
6666
6667
6668
6669
6670
6671
6672
6673
6674
6675
6676
6677
6678
6679
6680
6681
6682
6683
6684
6685
6686
6687
6688
6689
6690
6691
6692
6693
6694
6695
6696
6697
6698
6699
6700
6701
6702
6703
6704
6705
6706
6707
6708
6709
6710
6711
6712
6713
6714
6715
6716
6717
6718
6719
6720
6721
6722
6723
6724
6725
6726
6727
6728
6729
6730
6731
6732
6733
6734
6735
6736
6737
6738
6739
6740
6741
6742
6743
6744
6745
6746
6747
6748
6749
6750
6751
6752
6753
6754
6755
6756
6757
6758
6759
6760
6761
6762
6763
6764
6765
6766
6767
6768
6769
6770
6771
6772
6773
6774
6775
6776
6777
6778
6779
6780
6781
6782
6783
6784
6785
6786
6787
6788
6789
6790
6791
6792
6793
6794
6795
6796
6797
6798
6799
6800
6801
6802
6803
6804
6805
6806
6807
6808
6809
6810
6811
6812
6813
6814
6815
6816
6817
6818
6819
6820
6821
6822
6823
6824
6825
6826
6827
6828
6829
6830
6831
6832
6833
6834
6835
6836
6837
6838
6839
6840
6841
6842
6843
6844
6845
6846
6847
6848
6849
6850
6851
6852
6853
6854
6855
6856
6857
6858
6859
6860
6861
6862
6863
6864
6865
6866
6867
6868
6869
6870
6871
6872
6873
6874
6875
6876
6877
6878
6879
6880
6881
6882
6883
6884
6885
6886
6887
6888
6889
6890
6891
6892
6893
6894
6895
6896
6897
6898
6899
6900
6901
6902
6903
6904
6905
6906
6907
6908
6909
6910
6911
6912
6913
6914
6915
6916
6917
6918
6919
6920
6921
6922
6923
6924
6925
6926
6927
6928
6929
6930
6931
6932
6933
6934
6935
6936
6937
6938
6939
6940
6941
6942
6943
6944
6945
6946
6947
6948
6949
6950
6951
6952
6953
6954
6955
6956
6957
6958
6959
6960
6961
6962
6963
6964
6965
6966
6967
6968
6969
6970
6971
6972
6973
6974
6975
6976
6977
6978
6979
6980
6981
6982
6983
6984
6985
6986
6987
6988
6989
6990
6991
6992
6993
6994
6995
6996
6997
6998
6999
7000
7001
7002
7003
7004
7005
7006
7007
7008
7009
7010
7011
7012
7013
7014
7015
7016
7017
7018
7019
7020
7021
7022
7023
7024
7025
7026
7027
7028
7029
7030
7031
7032
7033
7034
7035
7036
7037
7038
7039
7040
7041
7042
7043
7044
7045
7046
7047
7048
7049
7050
7051
7052
7053
7054
7055
7056
7057
7058
7059
7060
7061
7062
7063
7064
7065
7066
7067
7068
7069
7070
7071
7072
7073
7074
7075
7076
7077
7078
7079
7080
7081
7082
7083
7084
7085
7086
7087
7088
7089
7090
7091
7092
7093
7094
7095
7096
7097
7098
7099
7100
7101
7102
7103
7104
7105
7106
7107
7108
7109
7110
7111
7112
7113
7114
7115
7116
7117
7118
7119
7120
7121
7122
7123
7124
7125
7126
7127
7128
7129
7130
7131
7132
7133
7134
7135
7136
7137
7138
7139
7140
7141
7142
7143
7144
7145
7146
7147
7148
7149
7150
7151
7152
7153
7154
7155
7156
7157
7158
7159
7160
7161
7162
7163
7164
7165
7166
7167
7168
7169
7170
7171
7172
7173
7174
7175
7176
7177
7178
7179
7180
7181
7182
7183
7184
7185
7186
7187
7188
7189
7190
7191
7192
7193
7194
7195
7196
7197
7198
7199
7200
7201
7202
7203
7204
7205
7206
7207
7208
7209
7210
7211
7212
7213
7214
7215
7216
7217
7218
7219
7220
7221
7222
7223
7224
7225
7226
7227
7228
7229
7230
7231
7232
7233
7234
7235
7236
7237
7238
7239
7240
7241
7242
7243
7244
7245
7246
7247
7248
7249
7250
7251
7252
7253
7254
7255
7256
7257
7258
7259
7260
7261
7262
7263
7264
7265
7266
7267
7268
7269
7270
7271
7272
7273
7274
7275
7276
7277
7278
7279
7280
7281
7282
7283
7284
7285
7286
7287
7288
7289
7290
7291
7292
7293
7294
7295
7296
7297
7298
7299
7300
7301
7302
7303
7304
7305
7306
7307
7308
7309
7310
7311
7312
7313
7314
7315
7316
7317
7318
7319
7320
7321
7322
7323
7324
7325
7326
7327
7328
7329
7330
7331
7332
7333
7334
7335
7336
7337
7338
7339
7340
7341
7342
7343
7344
7345
7346
7347
7348
7349
7350
7351
7352
7353
7354
7355
7356
7357
7358
7359
7360
7361
7362
7363
7364
7365
7366
7367
7368
7369
7370
7371
7372
7373
7374
7375
7376
7377
7378
7379
7380
7381
7382
7383
7384
7385
7386
7387
7388
7389
7390
7391
7392
7393
7394
7395
7396
7397
7398
7399
7400
7401
7402
7403
7404
7405
7406
7407
7408
7409
7410
7411
7412
7413
7414
7415
7416
7417
7418
7419
7420
7421
7422
7423
7424
7425
7426
7427
7428
7429
7430
7431
7432
7433
7434
7435
7436
7437
7438
7439
7440
7441
7442
7443
7444
7445
7446
7447
7448
7449
7450
7451
7452
7453
7454
7455
7456
7457
7458
7459
7460
7461
7462
7463
7464
7465
7466
7467
7468
7469
7470
7471
7472
7473
7474
7475
7476
7477
7478
7479
7480
7481
7482
7483
7484
7485
7486
7487
7488
7489
7490
7491
7492
7493
7494
7495
7496
7497
7498
7499
7500
7501
7502
7503
7504
7505
7506
7507
7508
7509
7510
7511
7512
7513
7514
7515
7516
7517
7518
7519
7520
7521
7522
7523
7524
7525
7526
7527
7528
7529
7530
7531
7532
7533
7534
7535
7536
7537
7538
7539
7540
7541
7542
7543
7544
7545
7546
7547
7548
7549
7550
7551
7552
7553
7554
7555
7556
7557
7558
7559
7560
7561
7562
7563
7564
7565
7566
7567
7568
7569
7570
7571
7572
7573
7574
7575
7576
7577
7578
7579
7580
7581
7582
7583
7584
7585
7586
7587
7588
7589
7590
7591
7592
7593
7594
7595
7596
7597
7598
7599
7600
7601
7602
7603
7604
7605
7606
7607
7608
7609
7610
7611
7612
7613
7614
7615
7616
7617
7618
7619
7620
7621
7622
7623
7624
7625
7626
7627
7628
7629
7630
7631
7632
7633
7634
7635
7636
7637
7638
7639
7640
7641
7642
7643
7644
7645
7646
7647
7648
7649
7650
7651
7652
7653
7654
7655
7656
7657
7658
7659
7660
7661
7662
7663
7664
7665
7666
7667
7668
7669
7670
7671
7672
7673
7674
7675
7676
7677
7678
7679
7680
7681
7682
7683
7684
7685
7686
7687
7688
7689
7690
7691
7692
7693
7694
7695
7696
7697
7698
7699
7700
7701
7702
7703
7704
7705
7706
7707
7708
7709
7710
7711
7712
7713
7714
7715
7716
7717
7718
7719
7720
7721
7722
7723
7724
7725
7726
7727
7728
7729
7730
7731
7732
7733
7734
7735
7736
7737
7738
7739
7740
7741
7742
7743
7744
7745
7746
7747
7748
7749
7750
7751
7752
7753
7754
7755
7756
7757
7758
7759
7760
7761
7762
7763
7764
7765
7766
7767
7768
7769
7770
7771
7772
7773
7774
7775
7776
7777
7778
7779
7780
7781
7782
7783
7784
7785
7786
7787
7788
7789
7790
7791
7792
7793
7794
7795
7796
7797
7798
7799
7800
7801
7802
7803
7804
7805
7806
7807
7808
7809
7810
7811
7812
7813
7814
7815
7816
7817
7818
7819
7820
7821
7822
7823
7824
7825
7826
7827
7828
7829
7830
7831
7832
7833
7834
7835
7836
7837
7838
7839
7840
7841
7842
7843
7844
7845
7846
7847
7848
7849
7850
7851
7852
7853
7854
7855
7856
7857
7858
7859
7860
7861
7862
7863
7864
7865
7866
7867
7868
7869
7870
7871
7872
7873
7874
7875
7876
7877
7878
7879
7880
7881
7882
7883
7884
7885
7886
7887
7888
7889
7890
7891
7892
7893
7894
7895
7896
7897
7898
7899
7900
7901
7902
7903
7904
7905
7906
7907
7908
7909
7910
7911
7912
7913
7914
7915
7916
7917
7918
7919
7920
7921
7922
7923
7924
7925
7926
7927
7928
7929
7930
7931
7932
7933
7934
7935
7936
7937
7938
7939
7940
7941
7942
7943
7944
7945
7946
7947
7948
7949
7950
7951
7952
7953
7954
7955
7956
7957
7958
7959
7960
7961
7962
7963
7964
7965
7966
7967
7968
7969
7970
7971
7972
7973
7974
7975
7976
7977
7978
7979
7980
7981
7982
7983
7984
7985
7986
7987
7988
7989
7990
7991
7992
7993
7994
7995
7996
7997
7998
7999
8000
8001
8002
8003
8004
8005
8006
8007
8008
8009
8010
8011
8012
8013
8014
8015
8016
8017
8018
8019
8020
8021
8022
8023
8024
8025
8026
8027
8028
8029
8030
8031
8032
8033
8034
8035
8036
8037
8038
8039
8040
8041
8042
8043
8044
8045
8046
8047
8048
8049
8050
8051
8052
8053
8054
8055
8056
8057
8058
8059
8060
8061
8062
8063
8064
8065
8066
8067
8068
8069
8070
8071
8072
8073
8074
8075
8076
8077
8078
8079
8080
8081
8082
8083
8084
8085
8086
8087
8088
8089
8090
8091
8092
8093
8094
8095
8096
8097
8098
8099
8100
8101
8102
8103
8104
8105
8106
8107
8108
8109
8110
8111
8112
8113
8114
8115
8116
8117
8118
8119
8120
8121
8122
8123
8124
8125
8126
8127
8128
8129
8130
8131
8132
8133
8134
8135
/*
* linux/drivers/char/synclink.c
*
* $Id: synclink.c,v 4.38 2005/11/07 16:30:34 paulkf Exp $
*
* Device driver for Microgate SyncLink ISA and PCI
* high speed multiprotocol serial adapters.
*
* written by Paul Fulghum for Microgate Corporation
* paulkf@microgate.com
*
* Microgate and SyncLink are trademarks of Microgate Corporation
*
* Derived from serial.c written by Theodore Ts'o and Linus Torvalds
*
* Original release 01/11/99
*
* This code is released under the GNU General Public License (GPL)
*
* This driver is primarily intended for use in synchronous
* HDLC mode. Asynchronous mode is also provided.
*
* When operating in synchronous mode, each call to mgsl_write()
* contains exactly one complete HDLC frame. Calling mgsl_put_char
* will start assembling an HDLC frame that will not be sent until
* mgsl_flush_chars or mgsl_write is called.
*
* Synchronous receive data is reported as complete frames. To accomplish
* this, the TTY flip buffer is bypassed (too small to hold largest
* frame and may fragment frames) and the line discipline
* receive entry point is called directly.
*
* This driver has been tested with a slightly modified ppp.c driver
* for synchronous PPP.
*
* 2000/02/16
* Added interface for syncppp.c driver (an alternate synchronous PPP
* implementation that also supports Cisco HDLC). Each device instance
* registers as a tty device AND a network device (if dosyncppp option
* is set for the device). The functionality is determined by which
* device interface is opened.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if defined(__i386__)
# define BREAKPOINT() asm(" int $3");
#else
# define BREAKPOINT() { }
#endif
#define MAX_ISA_DEVICES 10
#define MAX_PCI_DEVICES 10
#define MAX_TOTAL_DEVICES 20
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/serial.h>
#include <linux/major.h>
#include <linux/string.h>
#include <linux/fcntl.h>
#include <linux/ptrace.h>
#include <linux/ioport.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/netdevice.h>
#include <linux/vmalloc.h>
#include <linux/init.h>
#include <linux/ioctl.h>
#include <linux/synclink.h>
#include <asm/system.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/dma.h>
#include <linux/bitops.h>
#include <asm/types.h>
#include <linux/termios.h>
#include <linux/workqueue.h>
#include <linux/hdlc.h>
#include <linux/dma-mapping.h>
#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_MODULE))
#define SYNCLINK_GENERIC_HDLC 1
#else
#define SYNCLINK_GENERIC_HDLC 0
#endif
#define GET_USER(error,value,addr) error = get_user(value,addr)
#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
#define PUT_USER(error,value,addr) error = put_user(value,addr)
#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
#include <asm/uaccess.h>
#define RCLRVALUE 0xffff
static MGSL_PARAMS default_params = {
MGSL_MODE_HDLC, /* unsigned long mode */
0, /* unsigned char loopback; */
HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
0, /* unsigned long clock_speed; */
0xff, /* unsigned char addr_filter; */
HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
9600, /* unsigned long data_rate; */
8, /* unsigned char data_bits; */
1, /* unsigned char stop_bits; */
ASYNC_PARITY_NONE /* unsigned char parity; */
};
#define SHARED_MEM_ADDRESS_SIZE 0x40000
#define BUFFERLISTSIZE 4096
#define DMABUFFERSIZE 4096
#define MAXRXFRAMES 7
typedef struct _DMABUFFERENTRY
{
u32 phys_addr; /* 32-bit flat physical address of data buffer */
volatile u16 count; /* buffer size/data count */
volatile u16 status; /* Control/status field */
volatile u16 rcc; /* character count field */
u16 reserved; /* padding required by 16C32 */
u32 link; /* 32-bit flat link to next buffer entry */
char *virt_addr; /* virtual address of data buffer */
u32 phys_entry; /* physical address of this buffer entry */
dma_addr_t dma_addr;
} DMABUFFERENTRY, *DMAPBUFFERENTRY;
/* The queue of BH actions to be performed */
#define BH_RECEIVE 1
#define BH_TRANSMIT 2
#define BH_STATUS 4
#define IO_PIN_SHUTDOWN_LIMIT 100
struct _input_signal_events {
int ri_up;
int ri_down;
int dsr_up;
int dsr_down;
int dcd_up;
int dcd_down;
int cts_up;
int cts_down;
};
/* transmit holding buffer definitions*/
#define MAX_TX_HOLDING_BUFFERS 5
struct tx_holding_buffer {
int buffer_size;
unsigned char * buffer;
};
/*
* Device instance data structure
*/
struct mgsl_struct {
int magic;
struct tty_port port;
int line;
int hw_version;
struct mgsl_icount icount;
int timeout;
int x_char; /* xon/xoff character */
u16 read_status_mask;
u16 ignore_status_mask;
unsigned char *xmit_buf;
int xmit_head;
int xmit_tail;
int xmit_cnt;
wait_queue_head_t status_event_wait_q;
wait_queue_head_t event_wait_q;
struct timer_list tx_timer; /* HDLC transmit timeout timer */
struct mgsl_struct *next_device; /* device list link */
spinlock_t irq_spinlock; /* spinlock for synchronizing with ISR */
struct work_struct task; /* task structure for scheduling bh */
u32 EventMask; /* event trigger mask */
u32 RecordedEvents; /* pending events */
u32 max_frame_size; /* as set by device config */
u32 pending_bh;
bool bh_running; /* Protection from multiple */
int isr_overflow;
bool bh_requested;
int dcd_chkcount; /* check counts to prevent */
int cts_chkcount; /* too many IRQs if a signal */
int dsr_chkcount; /* is floating */
int ri_chkcount;
char *buffer_list; /* virtual address of Rx & Tx buffer lists */
u32 buffer_list_phys;
dma_addr_t buffer_list_dma_addr;
unsigned int rx_buffer_count; /* count of total allocated Rx buffers */
DMABUFFERENTRY *rx_buffer_list; /* list of receive buffer entries */
unsigned int current_rx_buffer;
int num_tx_dma_buffers; /* number of tx dma frames required */
int tx_dma_buffers_used;
unsigned int tx_buffer_count; /* count of total allocated Tx buffers */
DMABUFFERENTRY *tx_buffer_list; /* list of transmit buffer entries */
int start_tx_dma_buffer; /* tx dma buffer to start tx dma operation */
int current_tx_buffer; /* next tx dma buffer to be loaded */
unsigned char *intermediate_rxbuffer;
int num_tx_holding_buffers; /* number of tx holding buffer allocated */
int get_tx_holding_index; /* next tx holding buffer for adapter to load */
int put_tx_holding_index; /* next tx holding buffer to store user request */
int tx_holding_count; /* number of tx holding buffers waiting */
struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS];
bool rx_enabled;
bool rx_overflow;
bool rx_rcc_underrun;
bool tx_enabled;
bool tx_active;
u32 idle_mode;
u16 cmr_value;
u16 tcsr_value;
char device_name[25]; /* device instance name */
unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
unsigned char bus; /* expansion bus number (zero based) */
unsigned char function; /* PCI device number */
unsigned int io_base; /* base I/O address of adapter */
unsigned int io_addr_size; /* size of the I/O address range */
bool io_addr_requested; /* true if I/O address requested */
unsigned int irq_level; /* interrupt level */
unsigned long irq_flags;
bool irq_requested; /* true if IRQ requested */
unsigned int dma_level; /* DMA channel */
bool dma_requested; /* true if dma channel requested */
u16 mbre_bit;
u16 loopback_bits;
u16 usc_idle_mode;
MGSL_PARAMS params; /* communications parameters */
unsigned char serial_signals; /* current serial signal states */
bool irq_occurred; /* for diagnostics use */
unsigned int init_error; /* Initialization startup error (DIAGS) */
int fDiagnosticsmode; /* Driver in Diagnostic mode? (DIAGS) */
u32 last_mem_alloc;
unsigned char* memory_base; /* shared memory address (PCI only) */
u32 phys_memory_base;
bool shared_mem_requested;
unsigned char* lcr_base; /* local config registers (PCI only) */
u32 phys_lcr_base;
u32 lcr_offset;
bool lcr_mem_requested;
u32 misc_ctrl_value;
char flag_buf[MAX_ASYNC_BUFFER_SIZE];
char char_buf[MAX_ASYNC_BUFFER_SIZE];
bool drop_rts_on_tx_done;
bool loopmode_insert_requested;
bool loopmode_send_done_requested;
struct _input_signal_events input_signal_events;
/* generic HDLC device parts */
int netcount;
spinlock_t netlock;
#if SYNCLINK_GENERIC_HDLC
struct net_device *netdev;
#endif
};
#define MGSL_MAGIC 0x5401
/*
* The size of the serial xmit buffer is 1 page, or 4096 bytes
*/
#ifndef SERIAL_XMIT_SIZE
#define SERIAL_XMIT_SIZE 4096
#endif
/*
* These macros define the offsets used in calculating the
* I/O address of the specified USC registers.
*/
#define DCPIN 2 /* Bit 1 of I/O address */
#define SDPIN 4 /* Bit 2 of I/O address */
#define DCAR 0 /* DMA command/address register */
#define CCAR SDPIN /* channel command/address register */
#define DATAREG DCPIN + SDPIN /* serial data register */
#define MSBONLY 0x41
#define LSBONLY 0x40
/*
* These macros define the register address (ordinal number)
* used for writing address/value pairs to the USC.
*/
#define CMR 0x02 /* Channel mode Register */
#define CCSR 0x04 /* Channel Command/status Register */
#define CCR 0x06 /* Channel Control Register */
#define PSR 0x08 /* Port status Register */
#define PCR 0x0a /* Port Control Register */
#define TMDR 0x0c /* Test mode Data Register */
#define TMCR 0x0e /* Test mode Control Register */
#define CMCR 0x10 /* Clock mode Control Register */
#define HCR 0x12 /* Hardware Configuration Register */
#define IVR 0x14 /* Interrupt Vector Register */
#define IOCR 0x16 /* Input/Output Control Register */
#define ICR 0x18 /* Interrupt Control Register */
#define DCCR 0x1a /* Daisy Chain Control Register */
#define MISR 0x1c /* Misc Interrupt status Register */
#define SICR 0x1e /* status Interrupt Control Register */
#define RDR 0x20 /* Receive Data Register */
#define RMR 0x22 /* Receive mode Register */
#define RCSR 0x24 /* Receive Command/status Register */
#define RICR 0x26 /* Receive Interrupt Control Register */
#define RSR 0x28 /* Receive Sync Register */
#define RCLR 0x2a /* Receive count Limit Register */
#define RCCR 0x2c /* Receive Character count Register */
#define TC0R 0x2e /* Time Constant 0 Register */
#define TDR 0x30 /* Transmit Data Register */
#define TMR 0x32 /* Transmit mode Register */
#define TCSR 0x34 /* Transmit Command/status Register */
#define TICR 0x36 /* Transmit Interrupt Control Register */
#define TSR 0x38 /* Transmit Sync Register */
#define TCLR 0x3a /* Transmit count Limit Register */
#define TCCR 0x3c /* Transmit Character count Register */
#define TC1R 0x3e /* Time Constant 1 Register */
/*
* MACRO DEFINITIONS FOR DMA REGISTERS
*/
#define DCR 0x06 /* DMA Control Register (shared) */
#define DACR 0x08 /* DMA Array count Register (shared) */
#define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
#define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
#define DICR 0x18 /* DMA Interrupt Control Register (shared) */
#define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
#define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
#define TDMR 0x02 /* Transmit DMA mode Register */
#define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
#define TBCR 0x2a /* Transmit Byte count Register */
#define TARL 0x2c /* Transmit Address Register (low) */
#define TARU 0x2e /* Transmit Address Register (high) */
#define NTBCR 0x3a /* Next Transmit Byte count Register */
#define NTARL 0x3c /* Next Transmit Address Register (low) */
#define NTARU 0x3e /* Next Transmit Address Register (high) */
#define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
#define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
#define RBCR 0xaa /* Receive Byte count Register */
#define RARL 0xac /* Receive Address Register (low) */
#define RARU 0xae /* Receive Address Register (high) */
#define NRBCR 0xba /* Next Receive Byte count Register */
#define NRARL 0xbc /* Next Receive Address Register (low) */
#define NRARU 0xbe /* Next Receive Address Register (high) */
/*
* MACRO DEFINITIONS FOR MODEM STATUS BITS
*/
#define MODEMSTATUS_DTR 0x80
#define MODEMSTATUS_DSR 0x40
#define MODEMSTATUS_RTS 0x20
#define MODEMSTATUS_CTS 0x10
#define MODEMSTATUS_RI 0x04
#define MODEMSTATUS_DCD 0x01
/*
* Channel Command/Address Register (CCAR) Command Codes
*/
#define RTCmd_Null 0x0000
#define RTCmd_ResetHighestIus 0x1000
#define RTCmd_TriggerChannelLoadDma 0x2000
#define RTCmd_TriggerRxDma 0x2800
#define RTCmd_TriggerTxDma 0x3000
#define RTCmd_TriggerRxAndTxDma 0x3800
#define RTCmd_PurgeRxFifo 0x4800
#define RTCmd_PurgeTxFifo 0x5000
#define RTCmd_PurgeRxAndTxFifo 0x5800
#define RTCmd_LoadRcc 0x6800
#define RTCmd_LoadTcc 0x7000
#define RTCmd_LoadRccAndTcc 0x7800
#define RTCmd_LoadTC0 0x8800
#define RTCmd_LoadTC1 0x9000
#define RTCmd_LoadTC0AndTC1 0x9800
#define RTCmd_SerialDataLSBFirst 0xa000
#define RTCmd_SerialDataMSBFirst 0xa800
#define RTCmd_SelectBigEndian 0xb000
#define RTCmd_SelectLittleEndian 0xb800
/*
* DMA Command/Address Register (DCAR) Command Codes
*/
#define DmaCmd_Null 0x0000
#define DmaCmd_ResetTxChannel 0x1000
#define DmaCmd_ResetRxChannel 0x1200
#define DmaCmd_StartTxChannel 0x2000
#define DmaCmd_StartRxChannel 0x2200
#define DmaCmd_ContinueTxChannel 0x3000
#define DmaCmd_ContinueRxChannel 0x3200
#define DmaCmd_PauseTxChannel 0x4000
#define DmaCmd_PauseRxChannel 0x4200
#define DmaCmd_AbortTxChannel 0x5000
#define DmaCmd_AbortRxChannel 0x5200
#define DmaCmd_InitTxChannel 0x7000
#define DmaCmd_InitRxChannel 0x7200
#define DmaCmd_ResetHighestDmaIus 0x8000
#define DmaCmd_ResetAllChannels 0x9000
#define DmaCmd_StartAllChannels 0xa000
#define DmaCmd_ContinueAllChannels 0xb000
#define DmaCmd_PauseAllChannels 0xc000
#define DmaCmd_AbortAllChannels 0xd000
#define DmaCmd_InitAllChannels 0xf000
#define TCmd_Null 0x0000
#define TCmd_ClearTxCRC 0x2000
#define TCmd_SelectTicrTtsaData 0x4000
#define TCmd_SelectTicrTxFifostatus 0x5000
#define TCmd_SelectTicrIntLevel 0x6000
#define TCmd_SelectTicrdma_level 0x7000
#define TCmd_SendFrame 0x8000
#define TCmd_SendAbort 0x9000
#define TCmd_EnableDleInsertion 0xc000
#define TCmd_DisableDleInsertion 0xd000
#define TCmd_ClearEofEom 0xe000
#define TCmd_SetEofEom 0xf000
#define RCmd_Null 0x0000
#define RCmd_ClearRxCRC 0x2000
#define RCmd_EnterHuntmode 0x3000
#define RCmd_SelectRicrRtsaData 0x4000
#define RCmd_SelectRicrRxFifostatus 0x5000
#define RCmd_SelectRicrIntLevel 0x6000
#define RCmd_SelectRicrdma_level 0x7000
/*
* Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
*/
#define RECEIVE_STATUS BIT5
#define RECEIVE_DATA BIT4
#define TRANSMIT_STATUS BIT3
#define TRANSMIT_DATA BIT2
#define IO_PIN BIT1
#define MISC BIT0
/*
* Receive status Bits in Receive Command/status Register RCSR
*/
#define RXSTATUS_SHORT_FRAME BIT8
#define RXSTATUS_CODE_VIOLATION BIT8
#define RXSTATUS_EXITED_HUNT BIT7
#define RXSTATUS_IDLE_RECEIVED BIT6
#define RXSTATUS_BREAK_RECEIVED BIT5
#define RXSTATUS_ABORT_RECEIVED BIT5
#define RXSTATUS_RXBOUND BIT4
#define RXSTATUS_CRC_ERROR BIT3
#define RXSTATUS_FRAMING_ERROR BIT3
#define RXSTATUS_ABORT BIT2
#define RXSTATUS_PARITY_ERROR BIT2
#define RXSTATUS_OVERRUN BIT1
#define RXSTATUS_DATA_AVAILABLE BIT0
#define RXSTATUS_ALL 0x01f6
#define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
/*
* Values for setting transmit idle mode in
* Transmit Control/status Register (TCSR)
*/
#define IDLEMODE_FLAGS 0x0000
#define IDLEMODE_ALT_ONE_ZERO 0x0100
#define IDLEMODE_ZERO 0x0200
#define IDLEMODE_ONE 0x0300
#define IDLEMODE_ALT_MARK_SPACE 0x0500
#define IDLEMODE_SPACE 0x0600
#define IDLEMODE_MARK 0x0700
#define IDLEMODE_MASK 0x0700
/*
* IUSC revision identifiers
*/
#define IUSC_SL1660 0x4d44
#define IUSC_PRE_SL1660 0x4553
/*
* Transmit status Bits in Transmit Command/status Register (TCSR)
*/
#define TCSR_PRESERVE 0x0F00
#define TCSR_UNDERWAIT BIT11
#define TXSTATUS_PREAMBLE_SENT BIT7
#define TXSTATUS_IDLE_SENT BIT6
#define TXSTATUS_ABORT_SENT BIT5
#define TXSTATUS_EOF_SENT BIT4
#define TXSTATUS_EOM_SENT BIT4
#define TXSTATUS_CRC_SENT BIT3
#define TXSTATUS_ALL_SENT BIT2
#define TXSTATUS_UNDERRUN BIT1
#define TXSTATUS_FIFO_EMPTY BIT0
#define TXSTATUS_ALL 0x00fa
#define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
#define MISCSTATUS_RXC_LATCHED BIT15
#define MISCSTATUS_RXC BIT14
#define MISCSTATUS_TXC_LATCHED BIT13
#define MISCSTATUS_TXC BIT12
#define MISCSTATUS_RI_LATCHED BIT11
#define MISCSTATUS_RI BIT10
#define MISCSTATUS_DSR_LATCHED BIT9
#define MISCSTATUS_DSR BIT8
#define MISCSTATUS_DCD_LATCHED BIT7
#define MISCSTATUS_DCD BIT6
#define MISCSTATUS_CTS_LATCHED BIT5
#define MISCSTATUS_CTS BIT4
#define MISCSTATUS_RCC_UNDERRUN BIT3
#define MISCSTATUS_DPLL_NO_SYNC BIT2
#define MISCSTATUS_BRG1_ZERO BIT1
#define MISCSTATUS_BRG0_ZERO BIT0
#define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
#define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
#define SICR_RXC_ACTIVE BIT15
#define SICR_RXC_INACTIVE BIT14
#define SICR_RXC (BIT15+BIT14)
#define SICR_TXC_ACTIVE BIT13
#define SICR_TXC_INACTIVE BIT12
#define SICR_TXC (BIT13+BIT12)
#define SICR_RI_ACTIVE BIT11
#define SICR_RI_INACTIVE BIT10
#define SICR_RI (BIT11+BIT10)
#define SICR_DSR_ACTIVE BIT9
#define SICR_DSR_INACTIVE BIT8
#define SICR_DSR (BIT9+BIT8)
#define SICR_DCD_ACTIVE BIT7
#define SICR_DCD_INACTIVE BIT6
#define SICR_DCD (BIT7+BIT6)
#define SICR_CTS_ACTIVE BIT5
#define SICR_CTS_INACTIVE BIT4
#define SICR_CTS (BIT5+BIT4)
#define SICR_RCC_UNDERFLOW BIT3
#define SICR_DPLL_NO_SYNC BIT2
#define SICR_BRG1_ZERO BIT1
#define SICR_BRG0_ZERO BIT0
void usc_DisableMasterIrqBit( struct mgsl_struct *info );
void usc_EnableMasterIrqBit( struct mgsl_struct *info );
void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask );
void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask );
void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask );
#define usc_EnableInterrupts( a, b ) \
usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
#define usc_DisableInterrupts( a, b ) \
usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
#define usc_EnableMasterIrqBit(a) \
usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
#define usc_DisableMasterIrqBit(a) \
usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
#define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
/*
* Transmit status Bits in Transmit Control status Register (TCSR)
* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
*/
#define TXSTATUS_PREAMBLE_SENT BIT7
#define TXSTATUS_IDLE_SENT BIT6
#define TXSTATUS_ABORT_SENT BIT5
#define TXSTATUS_EOF BIT4
#define TXSTATUS_CRC_SENT BIT3
#define TXSTATUS_ALL_SENT BIT2
#define TXSTATUS_UNDERRUN BIT1
#define TXSTATUS_FIFO_EMPTY BIT0
#define DICR_MASTER BIT15
#define DICR_TRANSMIT BIT0
#define DICR_RECEIVE BIT1
#define usc_EnableDmaInterrupts(a,b) \
usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
#define usc_DisableDmaInterrupts(a,b) \
usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
#define usc_EnableStatusIrqs(a,b) \
usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
#define usc_DisablestatusIrqs(a,b) \
usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
/* Transmit status Bits in Transmit Control status Register (TCSR) */
/* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
#define DISABLE_UNCONDITIONAL 0
#define DISABLE_END_OF_FRAME 1
#define ENABLE_UNCONDITIONAL 2
#define ENABLE_AUTO_CTS 3
#define ENABLE_AUTO_DCD 3
#define usc_EnableTransmitter(a,b) \
usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
#define usc_EnableReceiver(a,b) \
usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
static u16 usc_InDmaReg( struct mgsl_struct *info, u16 Port );
static void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value );
static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd );
static u16 usc_InReg( struct mgsl_struct *info, u16 Port );
static void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );
static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd );
void usc_RCmd( struct mgsl_struct *info, u16 Cmd );
void usc_TCmd( struct mgsl_struct *info, u16 Cmd );
#define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
#define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
#define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
static void usc_process_rxoverrun_sync( struct mgsl_struct *info );
static void usc_start_receiver( struct mgsl_struct *info );
static void usc_stop_receiver( struct mgsl_struct *info );
static void usc_start_transmitter( struct mgsl_struct *info );
static void usc_stop_transmitter( struct mgsl_struct *info );
static void usc_set_txidle( struct mgsl_struct *info );
static void usc_load_txfifo( struct mgsl_struct *info );
static void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate );
static void usc_enable_loopback( struct mgsl_struct *info, int enable );
static void usc_get_serial_signals( struct mgsl_struct *info );
static void usc_set_serial_signals( struct mgsl_struct *info );
static void usc_reset( struct mgsl_struct *info );
static void usc_set_sync_mode( struct mgsl_struct *info );
static void usc_set_sdlc_mode( struct mgsl_struct *info );
static void usc_set_async_mode( struct mgsl_struct *info );
static void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate );
static void usc_loopback_frame( struct mgsl_struct *info );
static void mgsl_tx_timeout(unsigned long context);
static void usc_loopmode_cancel_transmit( struct mgsl_struct * info );
static void usc_loopmode_insert_request( struct mgsl_struct * info );
static int usc_loopmode_active( struct mgsl_struct * info);
static void usc_loopmode_send_done( struct mgsl_struct * info );
static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg);
#if SYNCLINK_GENERIC_HDLC
#define dev_to_port(D) (dev_to_hdlc(D)->priv)
static void hdlcdev_tx_done(struct mgsl_struct *info);
static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size);
static int hdlcdev_init(struct mgsl_struct *info);
static void hdlcdev_exit(struct mgsl_struct *info);
#endif
/*
* Defines a BUS descriptor value for the PCI adapter
* local bus address ranges.
*/
#define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
(0x00400020 + \
((WrHold) << 30) + \
((WrDly) << 28) + \
((RdDly) << 26) + \
((Nwdd) << 20) + \
((Nwad) << 15) + \
((Nxda) << 13) + \
((Nrdd) << 11) + \
((Nrad) << 6) )
static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit);
/*
* Adapter diagnostic routines
*/
static bool mgsl_register_test( struct mgsl_struct *info );
static bool mgsl_irq_test( struct mgsl_struct *info );
static bool mgsl_dma_test( struct mgsl_struct *info );
static bool mgsl_memory_test( struct mgsl_struct *info );
static int mgsl_adapter_test( struct mgsl_struct *info );
/*
* device and resource management routines
*/
static int mgsl_claim_resources(struct mgsl_struct *info);
static void mgsl_release_resources(struct mgsl_struct *info);
static void mgsl_add_device(struct mgsl_struct *info);
static struct mgsl_struct* mgsl_allocate_device(void);
/*
* DMA buffer manupulation functions.
*/
static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex );
static bool mgsl_get_rx_frame( struct mgsl_struct *info );
static bool mgsl_get_raw_rx_frame( struct mgsl_struct *info );
static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info );
static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info );
static int num_free_tx_dma_buffers(struct mgsl_struct *info);
static void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize);
static void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count);
/*
* DMA and Shared Memory buffer allocation and formatting
*/
static int mgsl_allocate_dma_buffers(struct mgsl_struct *info);
static void mgsl_free_dma_buffers(struct mgsl_struct *info);
static int mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
static int mgsl_alloc_buffer_list_memory(struct mgsl_struct *info);
static void mgsl_free_buffer_list_memory(struct mgsl_struct *info);
static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info);
static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info);
static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info);
static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info);
static bool load_next_tx_holding_buffer(struct mgsl_struct *info);
static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize);
/*
* Bottom half interrupt handlers
*/
static void mgsl_bh_handler(struct work_struct *work);
static void mgsl_bh_receive(struct mgsl_struct *info);
static void mgsl_bh_transmit(struct mgsl_struct *info);
static void mgsl_bh_status(struct mgsl_struct *info);
/*
* Interrupt handler routines and dispatch table.
*/
static void mgsl_isr_null( struct mgsl_struct *info );
static void mgsl_isr_transmit_data( struct mgsl_struct *info );
static void mgsl_isr_receive_data( struct mgsl_struct *info );
static void mgsl_isr_receive_status( struct mgsl_struct *info );
static void mgsl_isr_transmit_status( struct mgsl_struct *info );
static void mgsl_isr_io_pin( struct mgsl_struct *info );
static void mgsl_isr_misc( struct mgsl_struct *info );
static void mgsl_isr_receive_dma( struct mgsl_struct *info );
static void mgsl_isr_transmit_dma( struct mgsl_struct *info );
typedef void (*isr_dispatch_func)(struct mgsl_struct *);
static isr_dispatch_func UscIsrTable[7] =
{
mgsl_isr_null,
mgsl_isr_misc,
mgsl_isr_io_pin,
mgsl_isr_transmit_data,
mgsl_isr_transmit_status,
mgsl_isr_receive_data,
mgsl_isr_receive_status
};
/*
* ioctl call handlers
*/
static int tiocmget(struct tty_struct *tty, struct file *file);
static int tiocmset(struct tty_struct *tty, struct file *file,
unsigned int set, unsigned int clear);
static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount
__user *user_icount);
static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params);
static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params);
static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode);
static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode);
static int mgsl_txenable(struct mgsl_struct * info, int enable);
static int mgsl_txabort(struct mgsl_struct * info);
static int mgsl_rxenable(struct mgsl_struct * info, int enable);
static int mgsl_wait_event(struct mgsl_struct * info, int __user *mask);
static int mgsl_loopmode_send_done( struct mgsl_struct * info );
/* set non-zero on successful registration with PCI subsystem */
static bool pci_registered;
/*
* Global linked list of SyncLink devices
*/
static struct mgsl_struct *mgsl_device_list;
static int mgsl_device_count;
/*
* Set this param to non-zero to load eax with the
* .text section address and breakpoint on module load.
* This is useful for use with gdb and add-symbol-file command.
*/
static int break_on_load;
/*
* Driver major number, defaults to zero to get auto
* assigned major number. May be forced as module parameter.
*/
static int ttymajor;
/*
* Array of user specified options for ISA adapters.
*/
static int io[MAX_ISA_DEVICES];
static int irq[MAX_ISA_DEVICES];
static int dma[MAX_ISA_DEVICES];
static int debug_level;
static int maxframe[MAX_TOTAL_DEVICES];
static int txdmabufs[MAX_TOTAL_DEVICES];
static int txholdbufs[MAX_TOTAL_DEVICES];
module_param(break_on_load, bool, 0);
module_param(ttymajor, int, 0);
module_param_array(io, int, NULL, 0);
module_param_array(irq, int, NULL, 0);
module_param_array(dma, int, NULL, 0);
module_param(debug_level, int, 0);
module_param_array(maxframe, int, NULL, 0);
module_param_array(txdmabufs, int, NULL, 0);
module_param_array(txholdbufs, int, NULL, 0);
static char *driver_name = "SyncLink serial driver";
static char *driver_version = "$Revision: 4.38 $";
static int synclink_init_one (struct pci_dev *dev,
const struct pci_device_id *ent);
static void synclink_remove_one (struct pci_dev *dev);
static struct pci_device_id synclink_pci_tbl[] = {
{ PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, },
{ PCI_VENDOR_ID_MICROGATE, 0x0210, PCI_ANY_ID, PCI_ANY_ID, },
{ 0, }, /* terminate list */
};
MODULE_DEVICE_TABLE(pci, synclink_pci_tbl);
MODULE_LICENSE("GPL");
static struct pci_driver synclink_pci_driver = {
.name = "synclink",
.id_table = synclink_pci_tbl,
.probe = synclink_init_one,
.remove = __devexit_p(synclink_remove_one),
};
static struct tty_driver *serial_driver;
/* number of characters left in xmit buffer before we ask for more */
#define WAKEUP_CHARS 256
static void mgsl_change_params(struct mgsl_struct *info);
static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout);
/*
* 1st function defined in .text section. Calling this function in
* init_module() followed by a breakpoint allows a remote debugger
* (gdb) to get the .text address for the add-symbol-file command.
* This allows remote debugging of dynamically loadable modules.
*/
static void* mgsl_get_text_ptr(void)
{
return mgsl_get_text_ptr;
}
static inline int mgsl_paranoia_check(struct mgsl_struct *info,
char *name, const char *routine)
{
#ifdef MGSL_PARANOIA_CHECK
static const char *badmagic =
"Warning: bad magic number for mgsl struct (%s) in %s\n";
static const char *badinfo =
"Warning: null mgsl_struct for (%s) in %s\n";
if (!info) {
printk(badinfo, name, routine);
return 1;
}
if (info->magic != MGSL_MAGIC) {
printk(badmagic, name, routine);
return 1;
}
#else
if (!info)
return 1;
#endif
return 0;
}
/**
* line discipline callback wrappers
*
* The wrappers maintain line discipline references
* while calling into the line discipline.
*
* ldisc_receive_buf - pass receive data to line discipline
*/
static void ldisc_receive_buf(struct tty_struct *tty,
const __u8 *data, char *flags, int count)
{
struct tty_ldisc *ld;
if (!tty)
return;
ld = tty_ldisc_ref(tty);
if (ld) {
if (ld->ops->receive_buf)
ld->ops->receive_buf(tty, data, flags, count);
tty_ldisc_deref(ld);
}
}
/* mgsl_stop() throttle (stop) transmitter
*
* Arguments: tty pointer to tty info structure
* Return Value: None
*/
static void mgsl_stop(struct tty_struct *tty)
{
struct mgsl_struct *info = tty->driver_data;
unsigned long flags;
if (mgsl_paranoia_check(info, tty->name, "mgsl_stop"))
return;
if ( debug_level >= DEBUG_LEVEL_INFO )
printk("mgsl_stop(%s)\n",info->device_name);
spin_lock_irqsave(&info->irq_spinlock,flags);
if (info->tx_enabled)
usc_stop_transmitter(info);
spin_unlock_irqrestore(&info->irq_spinlock,flags);
} /* end of mgsl_stop() */
/* mgsl_start() release (start) transmitter
*
* Arguments: tty pointer to tty info structure
* Return Value: None
*/
static void mgsl_start(struct tty_struct *tty)
{
struct mgsl_struct *info = tty->driver_data;
unsigned long flags;
if (mgsl_paranoia_check(info, tty->name, "mgsl_start"))
return;
if ( debug_level >= DEBUG_LEVEL_INFO )
printk("mgsl_start(%s)\n",info->device_name);
spin_lock_irqsave(&info->irq_spinlock,flags);
if (!info->tx_enabled)
usc_start_transmitter(info);
spin_unlock_irqrestore(&info->irq_spinlock,flags);
} /* end of mgsl_start() */
/*
* Bottom half work queue access functions
*/
/* mgsl_bh_action() Return next bottom half action to perform.
* Return Value: BH action code or 0 if nothing to do.
*/
static int mgsl_bh_action(struct mgsl_struct *info)
{
unsigned long flags;
int rc = 0;
spin_lock_irqsave(&info->irq_spinlock,flags);
if (info->pending_bh & BH_RECEIVE) {
info->pending_bh &= ~BH_RECEIVE;
rc = BH_RECEIVE;
} else if (info->pending_bh & BH_TRANSMIT) {
info->pending_bh &= ~BH_TRANSMIT;
rc = BH_TRANSMIT;
} else if (info->pending_bh & BH_STATUS) {
info->pending_bh &= ~BH_STATUS;
rc = BH_STATUS;
}
if (!rc) {
/* Mark BH routine as complete */
info->bh_running = false;
info->bh_requested = false;
}
spin_unlock_irqrestore(&info->irq_spinlock,flags);
return rc;
}
/*
* Perform bottom half processing of work items queued by ISR.
*/
static void mgsl_bh_handler(struct work_struct *work)
{
struct mgsl_struct *info =
container_of(work, struct mgsl_struct, task);
int action;
if (!info)
return;
if ( debug_level >= DEBUG_LEVEL_BH )
printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
__FILE__,__LINE__,info->device_name);
info->bh_running = true;
while((action = mgsl_bh_action(info)) != 0) {
/* Process work item */
if ( debug_level >= DEBUG_LEVEL_BH )
printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
__FILE__,__LINE__,action);
switch (action) {
case BH_RECEIVE:
mgsl_bh_receive(info);
break;
case BH_TRANSMIT:
mgsl_bh_transmit(info);
break;
case BH_STATUS:
mgsl_bh_status(info);
break;
default:
/* unknown work item ID */
printk("Unknown work item ID=%08X!\n", action);
break;
}
}
if ( debug_level >= DEBUG_LEVEL_BH )
printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
__FILE__,__LINE__,info->device_name);
}
static void mgsl_bh_receive(struct mgsl_struct *info)
{
bool (*get_rx_frame)(struct mgsl_struct *info) =
(info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame);
if ( debug_level >= DEBUG_LEVEL_BH )
printk( "%s(%d):mgsl_bh_receive(%s)\n",
__FILE__,__LINE__,info->device_name);
do
{
if (info->rx_rcc_underrun) {
unsigned long flags;
spin_lock_irqsave(&info->irq_spinlock,flags);
usc_start_receiver(info);
spin_unlock_irqrestore(&info->irq_spinlock,flags);
return;
}
} while(get_rx_frame(info));
}
static void mgsl_bh_transmit(struct mgsl_struct *info)
{
struct tty_struct *tty = info->port.tty;
unsigned long flags;
if ( debug_level >= DEBUG_LEVEL_BH )
printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
__FILE__,__LINE__,info->device_name);
if (tty)
tty_wakeup(tty);
/* if transmitter idle and loopmode_send_done_requested
* then start echoing RxD to TxD
*/
spin_lock_irqsave(&info->irq_spinlock,flags);
if ( !info->tx_active && info->loopmode_send_done_requested )
usc_loopmode_send_done( info );
spin_unlock_irqrestore(&info->irq_spinlock,flags);
}
static void mgsl_bh_status(struct mgsl_struct *info)
{
if ( debug_level >= DEBUG_LEVEL_BH )
printk( "%s(%d):mgsl_bh_status() entry on %s\n",
__FILE__,__LINE__,info->device_name);
info->ri_chkcount = 0;
info->dsr_chkcount = 0;
info->dcd_chkcount = 0;
info->cts_chkcount = 0;
}
/* mgsl_isr_receive_status()
*
* Service a receive status interrupt. The type of status
* interrupt is indicated by the state of the RCSR.
* This is only used for HDLC mode.
*
* Arguments: info pointer to device instance data
* Return Value: None
*/
static void mgsl_isr_receive_status( struct mgsl_struct *info )
{
u16 status = usc_InReg( info, RCSR );
if ( debug_level >= DEBUG_LEVEL_ISR )
printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
__FILE__,__LINE__,status);
if ( (status & RXSTATUS_ABORT_RECEIVED) &&
info->loopmode_insert_requested &&
usc_loopmode_active(info) )
{
++info->icount.rxabort;
info->loopmode_insert_requested = false;
/* clear CMR:13 to start echoing RxD to TxD */
info->cmr_value &= ~BIT13;
usc_OutReg(info, CMR, info->cmr_value);
/* disable received abort irq (no longer required) */
usc_OutReg(info, RICR,
(usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED));
}
if (status & (RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED)) {
if (status & RXSTATUS_EXITED_HUNT)
info->icount.exithunt++;
if (status & RXSTATUS_IDLE_RECEIVED)
info->icount.rxidle++;
wake_up_interruptible(&info->event_wait_q);
}
if (status & RXSTATUS_OVERRUN){
info->icount.rxover++;
usc_process_rxoverrun_sync( info );
}
usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
usc_UnlatchRxstatusBits( info, status );
} /* end of mgsl_isr_receive_status() */
/* mgsl_isr_transmit_status()
*
* Service a transmit status interrupt
* HDLC mode :end of transmit frame
* Async mode:all data is sent
* transmit status is indicated by bits in the TCSR.
*
* Arguments: info pointer to device instance data
* Return Value: None
*/
static void mgsl_isr_transmit_status( struct mgsl_struct *info )
{
u16 status = usc_InReg( info, TCSR );
if ( debug_level >= DEBUG_LEVEL_ISR )
printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
__FILE__,__LINE__,status);
usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
usc_UnlatchTxstatusBits( info, status );
if ( status & (TXSTATUS_UNDERRUN | TXSTATUS_ABORT_SENT) )
{
/* finished sending HDLC abort. This may leave */
/* the TxFifo with data from the aborted frame */
/* so purge the TxFifo. Also shutdown the DMA */
/* channel in case there is data remaining in */
/* the DMA buffer */
usc_DmaCmd( info, DmaCmd_ResetTxChannel );
usc_RTCmd( info, RTCmd_PurgeTxFifo );
}
if ( status & TXSTATUS_EOF_SENT )
info->icount.txok++;
else if ( status & TXSTATUS_UNDERRUN )
info->icount.txunder++;
else if ( status & TXSTATUS_ABORT_SENT )
info->icount.txabort++;
else
info->icount.txunder++;
info->tx_active = false;
info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
del_timer(&info->tx_timer);
if ( info->drop_rts_on_tx_done ) {
usc_get_serial_signals( info );
if ( info->serial_signals & SerialSignal_RTS ) {
info->serial_signals &= ~SerialSignal_RTS;
usc_set_serial_signals( info );
}
info->drop_rts_on_tx_done = false;
}
#if SYNCLINK_GENERIC_HDLC
if (info->netcount)
hdlcdev_tx_done(info);
else
#endif
{
if (info->port.tty->stopped || info->port.tty->hw_stopped) {
usc_stop_transmitter(info);
return;
}
info->pending_bh |= BH_TRANSMIT;
}
} /* end of mgsl_isr_transmit_status() */
/* mgsl_isr_io_pin()
*
* Service an Input/Output pin interrupt. The type of
* interrupt is indicated by bits in the MISR
*
* Arguments: info pointer to device instance data
* Return Value: None
*/
static void mgsl_isr_io_pin( struct mgsl_struct *info )
{
struct mgsl_icount *icount;
u16 status = usc_InReg( info, MISR );
if ( debug_level >= DEBUG_LEVEL_ISR )
printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
__FILE__,__LINE__,status);
usc_ClearIrqPendingBits( info, IO_PIN );
usc_UnlatchIostatusBits( info, status );
if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
icount = &info->icount;
/* update input line counters */
if (status & MISCSTATUS_RI_LATCHED) {
if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
usc_DisablestatusIrqs(info,SICR_RI);
icount->rng++;
if ( status & MISCSTATUS_RI )
info->input_signal_events.ri_up++;
else
info->input_signal_events.ri_down++;
}
if (status & MISCSTATUS_DSR_LATCHED) {
if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
usc_DisablestatusIrqs(info,SICR_DSR);
icount->dsr++;
if ( status & MISCSTATUS_DSR )
info->input_signal_events.dsr_up++;
else
info->input_signal_events.dsr_down++;
}
if (status & MISCSTATUS_DCD_LATCHED) {
if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
usc_DisablestatusIrqs(info,SICR_DCD);
icount->dcd++;
if (status & MISCSTATUS_DCD) {
info->input_signal_events.dcd_up++;
} else
info->input_signal_events.dcd_down++;
#if SYNCLINK_GENERIC_HDLC
if (info->netcount) {
if (status & MISCSTATUS_DCD)
netif_carrier_on(info->netdev);
else
netif_carrier_off(info->netdev);
}
#endif
}
if (status & MISCSTATUS_CTS_LATCHED)
{
if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
usc_DisablestatusIrqs(info,SICR_CTS);
icount->cts++;
if ( status & MISCSTATUS_CTS )
info->input_signal_events.cts_up++;
else
info->input_signal_events.cts_down++;
}
wake_up_interruptible(&info->status_event_wait_q);
wake_up_interruptible(&info->event_wait_q);
if ( (info->port.flags & ASYNC_CHECK_CD) &&
(status & MISCSTATUS_DCD_LATCHED) ) {
if ( debug_level >= DEBUG_LEVEL_ISR )
printk("%s CD now %s...", info->device_name,
(status & MISCSTATUS_DCD) ? "on" : "off");
if (status & MISCSTATUS_DCD)
wake_up_interruptible(&info->port.open_wait);
else {
if ( debug_level >= DEBUG_LEVEL_ISR )
printk("doing serial hangup...");
if (info->port.tty)
tty_hangup(info->port.tty);
}
}
if ( (info->port.flags & ASYNC_CTS_FLOW) &&
(status & MISCSTATUS_CTS_LATCHED) ) {
if (info->port.tty->hw_stopped) {
if (status & MISCSTATUS_CTS) {
if ( debug_level >= DEBUG_LEVEL_ISR )
printk("CTS tx start...");
if (info->port.tty)
info->port.tty->hw_stopped = 0;
usc_start_transmitter(info);
info->pending_bh |= BH_TRANSMIT;
return;
}
} else {
if (!(status & MISCSTATUS_CTS)) {
if ( debug_level >= DEBUG_LEVEL_ISR )
printk("CTS tx stop...");
if (info->port.tty)
info->port.tty->hw_stopped = 1;
usc_stop_transmitter(info);
}
}
}
}
info->pending_bh |= BH_STATUS;
/* for diagnostics set IRQ flag */
if ( status & MISCSTATUS_TXC_LATCHED ){
usc_OutReg( info, SICR,
(unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) );
usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED );
info->irq_occurred = true;
}
} /* end of mgsl_isr_io_pin() */
/* mgsl_isr_transmit_data()
*
* Service a transmit data interrupt (async mode only).
*
* Arguments: info pointer to device instance data
* Return Value: None
*/
static void mgsl_isr_transmit_data( struct mgsl_struct *info )
{
if ( debug_level >= DEBUG_LEVEL_ISR )
printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
__FILE__,__LINE__,info->xmit_cnt);
usc_ClearIrqPendingBits( info, TRANSMIT_DATA );
if (info->port.tty->stopped || info->port.tty->hw_stopped) {
usc_stop_transmitter(info);
return;
}
if ( info->xmit_cnt )
usc_load_txfifo( info );
else
info->tx_active = false;
if (info->xmit_cnt < WAKEUP_CHARS)
info->pending_bh |= BH_TRANSMIT;
} /* end of mgsl_isr_transmit_data() */
/* mgsl_isr_receive_data()
*
* Service a receive data interrupt. This occurs
* when operating in asynchronous interrupt transfer mode.
* The receive data FIFO is flushed to the receive data buffers.
*
* Arguments: info pointer to device instance data
* Return Value: None
*/
static void mgsl_isr_receive_data( struct mgsl_struct *info )
{
int Fifocount;
u16 status;
int work = 0;
unsigned char DataByte;
struct tty_struct *tty = info->port.tty;
struct mgsl_icount *icount = &info->icount;
if ( debug_level >= DEBUG_LEVEL_ISR )
printk("%s(%d):mgsl_isr_receive_data\n",
__FILE__,__LINE__);
usc_ClearIrqPendingBits( info, RECEIVE_DATA );
/* select FIFO status for RICR readback */
usc_RCmd( info, RCmd_SelectRicrRxFifostatus );
/* clear the Wordstatus bit so that status readback */
/* only reflects the status of this byte */
usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 ));
/* flush the receive FIFO */
while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) {
int flag;
/* read one byte from RxFIFO */
outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
info->io_base + CCAR );
DataByte = inb( info->io_base + CCAR );
/* get the status of the received byte */
status = usc_InReg(info, RCSR);
if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) )
usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
icount->rx++;
flag = 0;
if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) ) {
printk("rxerr=%04X\n",status);
/* update error statistics */
if ( status & RXSTATUS_BREAK_RECEIVED ) {
status &= ~(RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR);
icount->brk++;
} else if (status & RXSTATUS_PARITY_ERROR)
icount->parity++;
else if (status & RXSTATUS_FRAMING_ERROR)
icount->frame++;
else if (status & RXSTATUS_OVERRUN) {
/* must issue purge fifo cmd before */
/* 16C32 accepts more receive chars */
usc_RTCmd(info,RTCmd_PurgeRxFifo);
icount->overrun++;
}
/* discard char if tty control flags say so */
if (status & info->ignore_status_mask)
continue;
status &= info->read_status_mask;
if (status & RXSTATUS_BREAK_RECEIVED) {
flag = TTY_BREAK;
if (info->port.flags & ASYNC_SAK)
do_SAK(tty);
} else if (status & RXSTATUS_PARITY_ERROR)
flag = TTY_PARITY;
else if (status & RXSTATUS_FRAMING_ERROR)
flag = TTY_FRAME;
} /* end of if (error) */
tty_insert_flip_char(tty, DataByte, flag);
if (status & RXSTATUS_OVERRUN) {
/* Overrun is special, since it's
* reported immediately, and doesn't
* affect the current character
*/
work += tty_insert_flip_char(tty, 0, TTY_OVERRUN);
}
}
if ( debug_level >= DEBUG_LEVEL_ISR ) {
printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
__FILE__,__LINE__,icount->rx,icount->brk,
icount->parity,icount->frame,icount->overrun);
}
if(work)
tty_flip_buffer_push(tty);
}
/* mgsl_isr_misc()
*
* Service a miscellaneous interrupt source.
*
* Arguments: info pointer to device extension (instance data)
* Return Value: None
*/
static void mgsl_isr_misc( struct mgsl_struct *info )
{
u16 status = usc_InReg( info, MISR );
if ( debug_level >= DEBUG_LEVEL_ISR )
printk("%s(%d):mgsl_isr_misc status=%04X\n",
__FILE__,__LINE__,status);
if ((status & MISCSTATUS_RCC_UNDERRUN) &&
(info->params.mode == MGSL_MODE_HDLC)) {
/* turn off receiver and rx DMA */
usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
usc_DmaCmd(info, DmaCmd_ResetRxChannel);
usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
usc_DisableInterrupts(info, RECEIVE_DATA + RECEIVE_STATUS);
/* schedule BH handler to restart receiver */
info->pending_bh |= BH_RECEIVE;
info->rx_rcc_underrun = true;
}
usc_ClearIrqPendingBits( info, MISC );
usc_UnlatchMiscstatusBits( info, status );
} /* end of mgsl_isr_misc() */
/* mgsl_isr_null()
*
* Services undefined interrupt vectors from the
* USC. (hence this function SHOULD never be called)
*
* Arguments: info pointer to device extension (instance data)
* Return Value: None
*/
static void mgsl_isr_null( struct mgsl_struct *info )
{
} /* end of mgsl_isr_null() */
/* mgsl_isr_receive_dma()
*
* Service a receive DMA channel interrupt.
* For this driver there are two sources of receive DMA interrupts
* as identified in the Receive DMA mode Register (RDMR):
*
* BIT3 EOA/EOL End of List, all receive buffers in receive
* buffer list have been filled (no more free buffers
* available). The DMA controller has shut down.
*
* BIT2 EOB End of Buffer. This interrupt occurs when a receive
* DMA buffer is terminated in response to completion
* of a good frame or a frame with errors. The status
* of the frame is stored in the buffer entry in the
* list of receive buffer entries.
*
* Arguments: info pointer to device instance data
* Return Value: None
*/
static void mgsl_isr_receive_dma( struct mgsl_struct *info )
{
u16 status;
/* clear interrupt pending and IUS bit for Rx DMA IRQ */
usc_OutDmaReg( info, CDIR, BIT9+BIT1 );
/* Read the receive DMA status to identify interrupt type. */
/* This also clears the status bits. */
status = usc_InDmaReg( info, RDMR );
if ( debug_level >= DEBUG_LEVEL_ISR )
printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
__FILE__,__LINE__,info->device_name,status);
info->pending_bh |= BH_RECEIVE;
if ( status & BIT3 ) {
info->rx_overflow = true;
info->icount.buf_overrun++;
}
} /* end of mgsl_isr_receive_dma() */
/* mgsl_isr_transmit_dma()
*
* This function services a transmit DMA channel interrupt.
*
* For this driver there is one source of transmit DMA interrupts
* as identified in the Transmit DMA Mode Register (TDMR):
*
* BIT2 EOB End of Buffer. This interrupt occurs when a
* transmit DMA buffer has been emptied.
*
* The driver maintains enough transmit DMA buffers to hold at least
* one max frame size transmit frame. When operating in a buffered
* transmit mode, there may be enough transmit DMA buffers to hold at
* least two or more max frame size frames. On an EOB condition,
* determine if there are any queued transmit buffers and copy into
* transmit DMA buffers if we have room.
*
* Arguments: info pointer to device instance data
* Return Value: None
*/
static void mgsl_isr_transmit_dma( struct mgsl_struct *info )
{
u16 status;
/* clear interrupt pending and IUS bit for Tx DMA IRQ */
usc_OutDmaReg(info, CDIR, BIT8+BIT0 );
/* Read the transmit DMA status to identify interrupt type. */
/* This also clears the status bits. */
status = usc_InDmaReg( info, TDMR );
if ( debug_level >= DEBUG_LEVEL_ISR )
printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
__FILE__,__LINE__,info->device_name,status);
if ( status & BIT2 ) {
--info->tx_dma_buffers_used;
/* if there are transmit frames queued,
* try to load the next one
*/
if ( load_next_tx_holding_buffer(info) ) {
/* if call returns non-zero value, we have
* at least one free tx holding buffer
*/
info->pending_bh |= BH_TRANSMIT;
}
}
} /* end of mgsl_isr_transmit_dma() */
/* mgsl_interrupt()
*
* Interrupt service routine entry point.
*
* Arguments:
*
* irq interrupt number that caused interrupt
* dev_id device ID supplied during interrupt registration
*
* Return Value: None
*/
static irqreturn_t mgsl_interrupt(int dummy, void *dev_id)
{
struct mgsl_struct *info = dev_id;
u16 UscVector;
u16 DmaVector;
if ( debug_level >= DEBUG_LEVEL_ISR )
printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)entry.\n",
__FILE__, __LINE__, info->irq_level);
spin_lock(&info->irq_spinlock);
for(;;) {
/* Read the interrupt vectors from hardware. */
UscVector = usc_InReg(info, IVR) >> 9;
DmaVector = usc_InDmaReg(info, DIVR);
if ( debug_level >= DEBUG_LEVEL_ISR )
printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
__FILE__,__LINE__,info->device_name,UscVector,DmaVector);
if ( !UscVector && !DmaVector )
break;
/* Dispatch interrupt vector */
if ( UscVector )
(*UscIsrTable[UscVector])(info);
else if ( (DmaVector&(BIT10|BIT9)) == BIT10)
mgsl_isr_transmit_dma(info);
else
mgsl_isr_receive_dma(info);
if ( info->isr_overflow ) {
printk(KERN_ERR "%s(%d):%s isr overflow irq=%d\n",
__FILE__, __LINE__, info->device_name, info->irq_level);
usc_DisableMasterIrqBit(info);
usc_DisableDmaInterrupts(info,DICR_MASTER);
break;
}
}
/* Request bottom half processing if there's something
* for it to do and the bh is not already running
*/
if ( info->pending_bh && !info->bh_running && !info->bh_requested ) {
if ( debug_level >= DEBUG_LEVEL_ISR )
printk("%s(%d):%s queueing bh task.\n",
__FILE__,__LINE__,info->device_name);
schedule_work(&info->task);
info->bh_requested = true;
}
spin_unlock(&info->irq_spinlock);
if ( debug_level >= DEBUG_LEVEL_ISR )
printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)exit.\n",
__FILE__, __LINE__, info->irq_level);
return IRQ_HANDLED;
} /* end of mgsl_interrupt() */
/* startup()
*
* Initialize and start device.
*
* Arguments: info pointer to device instance data
* Return Value: 0 if success, otherwise error code
*/
static int startup(struct mgsl_struct * info)
{
int retval = 0;
if ( debug_level >= DEBUG_LEVEL_INFO )
printk("%s(%d):mgsl_startup(%s)\n",__FILE__,__LINE__,info->device_name);
if (info->port.flags & ASYNC_INITIALIZED)
return 0;
if (!info->xmit_buf) {
/* allocate a page of memory for a transmit buffer */
info->xmit_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
if (!info->xmit_buf) {
printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
__FILE__,__LINE__,info->device_name);
return -ENOMEM;
}
}
info->pending_bh = 0;
memset(&info->icount, 0, sizeof(info->icount));
setup_timer(&info->tx_timer, mgsl_tx_timeout, (unsigned long)info);
/* Allocate and claim adapter resources */
retval = mgsl_claim_resources(info);
/* perform existence check and diagnostics */
if ( !retval )
retval = mgsl_adapter_test(info);
if ( retval ) {
if (capable(CAP_SYS_ADMIN) && info->port.tty)
set_bit(TTY_IO_ERROR, &info->port.tty->flags);
mgsl_release_resources(info);
return retval;
}
/* program hardware for current parameters */
mgsl_change_params(info);
if (info->port.tty)
clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
info->port.flags |= ASYNC_INITIALIZED;
return 0;
} /* end of startup() */
/* shutdown()
*
* Called by mgsl_close() and mgsl_hangup() to shutdown hardware
*
* Arguments: info pointer to device instance data
* Return Value: None
*/
static void shutdown(struct mgsl_struct * info)
{
unsigned long flags;
if (!(info->port.flags & ASYNC_INITIALIZED))
return;
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):mgsl_shutdown(%s)\n",
__FILE__,__LINE__, info->device_name );
/* clear status wait queue because status changes */
/* can't happen after shutting down the hardware */
wake_up_interruptible(&info->status_event_wait_q);
wake_up_interruptible(&info->event_wait_q);
del_timer_sync(&info->tx_timer);
if (info->xmit_buf) {
free_page((unsigned long) info->xmit_buf);
info->xmit_buf = NULL;
}
spin_lock_irqsave(&info->irq_spinlock,flags);
usc_DisableMasterIrqBit(info);
usc_stop_receiver(info);
usc_stop_transmitter(info);
usc_DisableInterrupts(info,RECEIVE_DATA + RECEIVE_STATUS +
TRANSMIT_DATA + TRANSMIT_STATUS + IO_PIN + MISC );
usc_DisableDmaInterrupts(info,DICR_MASTER + DICR_TRANSMIT + DICR_RECEIVE);
/* Disable DMAEN (Port 7, Bit 14) */
/* This disconnects the DMA request signal from the ISA bus */
/* on the ISA adapter. This has no effect for the PCI adapter */
usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14));
/* Disable INTEN (Port 6, Bit12) */
/* This disconnects the IRQ request signal to the ISA bus */
/* on the ISA adapter. This has no effect for the PCI adapter */
usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));
if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
usc_set_serial_signals(info);
}
spin_unlock_irqrestore(&info->irq_spinlock,flags);
mgsl_release_resources(info);
if (info->port.tty)
set_bit(TTY_IO_ERROR, &info->port.tty->flags);
info->port.flags &= ~ASYNC_INITIALIZED;
} /* end of shutdown() */
static void mgsl_program_hw(struct mgsl_struct *info)
{
unsigned long flags;
spin_lock_irqsave(&info->irq_spinlock,flags);
usc_stop_receiver(info);
usc_stop_transmitter(info);
info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
if (info->params.mode == MGSL_MODE_HDLC ||
info->params.mode == MGSL_MODE_RAW ||
info->netcount)
usc_set_sync_mode(info);
else
usc_set_async_mode(info);
usc_set_serial_signals(info);
info->dcd_chkcount = 0;
info->cts_chkcount = 0;
info->ri_chkcount = 0;
info->dsr_chkcount = 0;
usc_EnableStatusIrqs(info,SICR_CTS+SICR_DSR+SICR_DCD+SICR_RI);
usc_EnableInterrupts(info, IO_PIN);
usc_get_serial_signals(info);
if (info->netcount || info->port.tty->termios->c_cflag & CREAD)
usc_start_receiver(info);
spin_unlock_irqrestore(&info->irq_spinlock,flags);
}
/* Reconfigure adapter based on new parameters
*/
static void mgsl_change_params(struct mgsl_struct *info)
{
unsigned cflag;
int bits_per_char;
if (!info->port.tty || !info->port.tty->termios)
return;
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):mgsl_change_params(%s)\n",
__FILE__,__LINE__, info->device_name );
cflag = info->port.tty->termios->c_cflag;
/* if B0 rate (hangup) specified then negate DTR and RTS */
/* otherwise assert DTR and RTS */
if (cflag & CBAUD)
info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
else
info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
/* byte size and parity */
switch (cflag & CSIZE) {
case CS5: info->params.data_bits = 5; break;
case CS6: info->params.data_bits = 6; break;
case CS7: info->params.data_bits = 7; break;
case CS8: info->params.data_bits = 8; break;
/* Never happens, but GCC is too dumb to figure it out */
default: info->params.data_bits = 7; break;
}
if (cflag & CSTOPB)
info->params.stop_bits = 2;
else
info->params.stop_bits = 1;
info->params.parity = ASYNC_PARITY_NONE;
if (cflag & PARENB) {
if (cflag & PARODD)
info->params.parity = ASYNC_PARITY_ODD;
else
info->params.parity = ASYNC_PARITY_EVEN;
#ifdef CMSPAR
if (cflag & CMSPAR)
info->params.parity = ASYNC_PARITY_SPACE;
#endif
}
/* calculate number of jiffies to transmit a full
* FIFO (32 bytes) at specified data rate
*/
bits_per_char = info->params.data_bits +
info->params.stop_bits + 1;
/* if port data rate is set to 460800 or less then
* allow tty settings to override, otherwise keep the
* current data rate.
*/
if (info->params.data_rate <= 460800)
info->params.data_rate = tty_get_baud_rate(info->port.tty);
if ( info->params.data_rate ) {
info->timeout = (32*HZ*bits_per_char) /
info->params.data_rate;
}
info->timeout += HZ/50; /* Add .02 seconds of slop */
if (cflag & CRTSCTS)
info->port.flags |= ASYNC_CTS_FLOW;
else
info->port.flags &= ~ASYNC_CTS_FLOW;
if (cflag & CLOCAL)
info->port.flags &= ~ASYNC_CHECK_CD;
else
info->port.flags |= ASYNC_CHECK_CD;
/* process tty input control flags */
info->read_status_mask = RXSTATUS_OVERRUN;
if (I_INPCK(info->port.tty))
info->read_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
info->read_status_mask |= RXSTATUS_BREAK_RECEIVED;
if (I_IGNPAR(info->port.tty))
info->ignore_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
if (I_IGNBRK(info->port.tty)) {
info->ignore_status_mask |= RXSTATUS_BREAK_RECEIVED;
/* If ignoring parity and break indicators, ignore
* overruns too. (For real raw support).
*/
if (I_IGNPAR(info->port.tty))
info->ignore_status_mask |= RXSTATUS_OVERRUN;
}
mgsl_program_hw(info);
} /* end of mgsl_change_params() */
/* mgsl_put_char()
*
* Add a character to the transmit buffer.
*
* Arguments: tty pointer to tty information structure
* ch character to add to transmit buffer
*
* Return Value: None
*/
static int mgsl_put_char(struct tty_struct *tty, unsigned char ch)
{
struct mgsl_struct *info = tty->driver_data;
unsigned long flags;
int ret = 0;
if (debug_level >= DEBUG_LEVEL_INFO) {
printk(KERN_DEBUG "%s(%d):mgsl_put_char(%d) on %s\n",
__FILE__, __LINE__, ch, info->device_name);
}
if (mgsl_paranoia_check(info, tty->name, "mgsl_put_char"))
return 0;
if (!tty || !info->xmit_buf)
return 0;
spin_lock_irqsave(&info->irq_spinlock, flags);
if ((info->params.mode == MGSL_MODE_ASYNC ) || !info->tx_active) {
if (info->xmit_cnt < SERIAL_XMIT_SIZE - 1) {
info->xmit_buf[info->xmit_head++] = ch;
info->xmit_head &= SERIAL_XMIT_SIZE-1;
info->xmit_cnt++;
ret = 1;
}
}
spin_unlock_irqrestore(&info->irq_spinlock, flags);
return ret;
} /* end of mgsl_put_char() */
/* mgsl_flush_chars()
*
* Enable transmitter so remaining characters in the
* transmit buffer are sent.
*
* Arguments: tty pointer to tty information structure
* Return Value: None
*/
static void mgsl_flush_chars(struct tty_struct *tty)
{
struct mgsl_struct *info = tty->driver_data;
unsigned long flags;
if ( debug_level >= DEBUG_LEVEL_INFO )
printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
__FILE__,__LINE__,info->device_name,info->xmit_cnt);
if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_chars"))
return;
if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped ||
!info->xmit_buf)
return;
if ( debug_level >= DEBUG_LEVEL_INFO )
printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
__FILE__,__LINE__,info->device_name );
spin_lock_irqsave(&info->irq_spinlock,flags);
if (!info->tx_active) {
if ( (info->params.mode == MGSL_MODE_HDLC ||
info->params.mode == MGSL_MODE_RAW) && info->xmit_cnt ) {
/* operating in synchronous (frame oriented) mode */
/* copy data from circular xmit_buf to */
/* transmit DMA buffer. */
mgsl_load_tx_dma_buffer(info,
info->xmit_buf,info->xmit_cnt);
}
usc_start_transmitter(info);
}
spin_unlock_irqrestore(&info->irq_spinlock,flags);
} /* end of mgsl_flush_chars() */
/* mgsl_write()
*
* Send a block of data
*
* Arguments:
*
* tty pointer to tty information structure
* buf pointer to buffer containing send data
* count size of send data in bytes
*
* Return Value: number of characters written
*/
static int mgsl_write(struct tty_struct * tty,
const unsigned char *buf, int count)
{
int c, ret = 0;
struct mgsl_struct *info = tty->driver_data;
unsigned long flags;
if ( debug_level >= DEBUG_LEVEL_INFO )
printk( "%s(%d):mgsl_write(%s) count=%d\n",
__FILE__,__LINE__,info->device_name,count);
if (mgsl_paranoia_check(info, tty->name, "mgsl_write"))
goto cleanup;
if (!tty || !info->xmit_buf)
goto cleanup;
if ( info->params.mode == MGSL_MODE_HDLC ||
info->params.mode == MGSL_MODE_RAW ) {
/* operating in synchronous (frame oriented) mode */
/* operating in synchronous (frame oriented) mode */
if (info->tx_active) {
if ( info->params.mode == MGSL_MODE_HDLC ) {
ret = 0;
goto cleanup;
}
/* transmitter is actively sending data -
* if we have multiple transmit dma and
* holding buffers, attempt to queue this
* frame for transmission at a later time.
*/
if (info->tx_holding_count >= info->num_tx_holding_buffers ) {
/* no tx holding buffers available */
ret = 0;
goto cleanup;
}
/* queue transmit frame request */
ret = count;
save_tx_buffer_request(info,buf,count);
/* if we have sufficient tx dma buffers,
* load the next buffered tx request
*/
spin_lock_irqsave(&info->irq_spinlock,flags);
load_next_tx_holding_buffer(info);
spin_unlock_irqrestore(&info->irq_spinlock,flags);
goto cleanup;
}
/* if operating in HDLC LoopMode and the adapter */
/* has yet to be inserted into the loop, we can't */
/* transmit */
if ( (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) &&
!usc_loopmode_active(info) )
{
ret = 0;
goto cleanup;
}
if ( info->xmit_cnt ) {
/* Send accumulated from send_char() calls */
/* as frame and wait before accepting more data. */
ret = 0;
/* copy data from circular xmit_buf to */
/* transmit DMA buffer. */
mgsl_load_tx_dma_buffer(info,
info->xmit_buf,info->xmit_cnt);
if ( debug_level >= DEBUG_LEVEL_INFO )
printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
__FILE__,__LINE__,info->device_name);
} else {
if ( debug_level >= DEBUG_LEVEL_INFO )
printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
__FILE__,__LINE__,info->device_name);
ret = count;
info->xmit_cnt = count;
mgsl_load_tx_dma_buffer(info,buf,count);
}
} else {
while (1) {
spin_lock_irqsave(&info->irq_spinlock,flags);
c = min_t(int, count,
min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
SERIAL_XMIT_SIZE - info->xmit_head));
if (c <= 0) {
spin_unlock_irqrestore(&info->irq_spinlock,flags);
break;
}
memcpy(info->xmit_buf + info->xmit_head, buf, c);
info->xmit_head = ((info->xmit_head + c) &
(SERIAL_XMIT_SIZE-1));
info->xmit_cnt += c;
spin_unlock_irqrestore(&info->irq_spinlock,flags);
buf += c;
count -= c;
ret += c;
}
}
if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) {
spin_lock_irqsave(&info->irq_spinlock,flags);
if (!info->tx_active)
usc_start_transmitter(info);
spin_unlock_irqrestore(&info->irq_spinlock,flags);
}
cleanup:
if ( debug_level >= DEBUG_LEVEL_INFO )
printk( "%s(%d):mgsl_write(%s) returning=%d\n",
__FILE__,__LINE__,info->device_name,ret);
return ret;
} /* end of mgsl_write() */
/* mgsl_write_room()
*
* Return the count of free bytes in transmit buffer
*
* Arguments: tty pointer to tty info structure
* Return Value: None
*/
static int mgsl_write_room(struct tty_struct *tty)
{
struct mgsl_struct *info = tty->driver_data;
int ret;
if (mgsl_paranoia_check(info, tty->name, "mgsl_write_room"))
return 0;
ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
if (ret < 0)
ret = 0;
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):mgsl_write_room(%s)=%d\n",
__FILE__,__LINE__, info->device_name,ret );
if ( info->params.mode == MGSL_MODE_HDLC ||
info->params.mode == MGSL_MODE_RAW ) {
/* operating in synchronous (frame oriented) mode */
if ( info->tx_active )
return 0;
else
return HDLC_MAX_FRAME_SIZE;
}
return ret;
} /* end of mgsl_write_room() */
/* mgsl_chars_in_buffer()
*
* Return the count of bytes in transmit buffer
*
* Arguments: tty pointer to tty info structure
* Return Value: None
*/
static int mgsl_chars_in_buffer(struct tty_struct *tty)
{
struct mgsl_struct *info = tty->driver_data;
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
__FILE__,__LINE__, info->device_name );
if (mgsl_paranoia_check(info, tty->name, "mgsl_chars_in_buffer"))
return 0;
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
__FILE__,__LINE__, info->device_name,info->xmit_cnt );
if ( info->params.mode == MGSL_MODE_HDLC ||
info->params.mode == MGSL_MODE_RAW ) {
/* operating in synchronous (frame oriented) mode */
if ( info->tx_active )
return info->max_frame_size;
else
return 0;
}
return info->xmit_cnt;
} /* end of mgsl_chars_in_buffer() */
/* mgsl_flush_buffer()
*
* Discard all data in the send buffer
*
* Arguments: tty pointer to tty info structure
* Return Value: None
*/
static void mgsl_flush_buffer(struct tty_struct *tty)
{
struct mgsl_struct *info = tty->driver_data;
unsigned long flags;
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
__FILE__,__LINE__, info->device_name );
if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_buffer"))
return;
spin_lock_irqsave(&info->irq_spinlock,flags);
info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
del_timer(&info->tx_timer);
spin_unlock_irqrestore(&info->irq_spinlock,flags);
tty_wakeup(tty);
}
/* mgsl_send_xchar()
*
* Send a high-priority XON/XOFF character
*
* Arguments: tty pointer to tty info structure
* ch character to send
* Return Value: None
*/
static void mgsl_send_xchar(struct tty_struct *tty, char ch)
{
struct mgsl_struct *info = tty->driver_data;
unsigned long flags;
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
__FILE__,__LINE__, info->device_name, ch );
if (mgsl_paranoia_check(info, tty->name, "mgsl_send_xchar"))
return;
info->x_char = ch;
if (ch) {
/* Make sure transmit interrupts are on */
spin_lock_irqsave(&info->irq_spinlock,flags);
if (!info->tx_enabled)
usc_start_transmitter(info);
spin_unlock_irqrestore(&info->irq_spinlock,flags);
}
} /* end of mgsl_send_xchar() */
/* mgsl_throttle()
*
* Signal remote device to throttle send data (our receive data)
*
* Arguments: tty pointer to tty info structure
* Return Value: None
*/
static void mgsl_throttle(struct tty_struct * tty)
{
struct mgsl_struct *info = tty->driver_data;
unsigned long flags;
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):mgsl_throttle(%s) entry\n",
__FILE__,__LINE__, info->device_name );
if (mgsl_paranoia_check(info, tty->name, "mgsl_throttle"))
return;
if (I_IXOFF(tty))
mgsl_send_xchar(tty, STOP_CHAR(tty));
if (tty->termios->c_cflag & CRTSCTS) {
spin_lock_irqsave(&info->irq_spinlock,flags);
info->serial_signals &= ~SerialSignal_RTS;
usc_set_serial_signals(info);
spin_unlock_irqrestore(&info->irq_spinlock,flags);
}
} /* end of mgsl_throttle() */
/* mgsl_unthrottle()
*
* Signal remote device to stop throttling send data (our receive data)
*
* Arguments: tty pointer to tty info structure
* Return Value: None
*/
static void mgsl_unthrottle(struct tty_struct * tty)
{
struct mgsl_struct *info = tty->driver_data;
unsigned long flags;
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):mgsl_unthrottle(%s) entry\n",
__FILE__,__LINE__, info->device_name );
if (mgsl_paranoia_check(info, tty->name, "mgsl_unthrottle"))
return;
if (I_IXOFF(tty)) {
if (info->x_char)
info->x_char = 0;
else
mgsl_send_xchar(tty, START_CHAR(tty));
}
if (tty->termios->c_cflag & CRTSCTS) {
spin_lock_irqsave(&info->irq_spinlock,flags);
info->serial_signals |= SerialSignal_RTS;
usc_set_serial_signals(info);
spin_unlock_irqrestore(&info->irq_spinlock,flags);
}
} /* end of mgsl_unthrottle() */
/* mgsl_get_stats()
*
* get the current serial parameters information
*
* Arguments: info pointer to device instance data
* user_icount pointer to buffer to hold returned stats
*
* Return Value: 0 if success, otherwise error code
*/
static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount __user *user_icount)
{
int err;
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):mgsl_get_params(%s)\n",
__FILE__,__LINE__, info->device_name);
if (!user_icount) {
memset(&info->icount, 0, sizeof(info->icount));
} else {
COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
if (err)
return -EFAULT;
}
return 0;
} /* end of mgsl_get_stats() */
/* mgsl_get_params()
*
* get the current serial parameters information
*
* Arguments: info pointer to device instance data
* user_params pointer to buffer to hold returned params
*
* Return Value: 0 if success, otherwise error code
*/
static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params)
{
int err;
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):mgsl_get_params(%s)\n",
__FILE__,__LINE__, info->device_name);
COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
if (err) {
if ( debug_level >= DEBUG_LEVEL_INFO )
printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
__FILE__,__LINE__,info->device_name);
return -EFAULT;
}
return 0;
} /* end of mgsl_get_params() */
/* mgsl_set_params()
*
* set the serial parameters
*
* Arguments:
*
* info pointer to device instance data
* new_params user buffer containing new serial params
*
* Return Value: 0 if success, otherwise error code
*/
static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params)
{
unsigned long flags;
MGSL_PARAMS tmp_params;
int err;
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):mgsl_set_params %s\n", __FILE__,__LINE__,
info->device_name );
COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
if (err) {
if ( debug_level >= DEBUG_LEVEL_INFO )
printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
__FILE__,__LINE__,info->device_name);
return -EFAULT;
}
spin_lock_irqsave(&info->irq_spinlock,flags);
memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
spin_unlock_irqrestore(&info->irq_spinlock,flags);
mgsl_change_params(info);
return 0;
} /* end of mgsl_set_params() */
/* mgsl_get_txidle()
*
* get the current transmit idle mode
*
* Arguments: info pointer to device instance data
* idle_mode pointer to buffer to hold returned idle mode
*
* Return Value: 0 if success, otherwise error code
*/
static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode)
{
int err;
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
__FILE__,__LINE__, info->device_name, info->idle_mode);
COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
if (err) {
if ( debug_level >= DEBUG_LEVEL_INFO )
printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
__FILE__,__LINE__,info->device_name);
return -EFAULT;
}
return 0;
} /* end of mgsl_get_txidle() */
/* mgsl_set_txidle() service ioctl to set transmit idle mode
*
* Arguments: info pointer to device instance data
* idle_mode new idle mode
*
* Return Value: 0 if success, otherwise error code
*/
static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode)
{
unsigned long flags;
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__,__LINE__,
info->device_name, idle_mode );
spin_lock_irqsave(&info->irq_spinlock,flags);
info->idle_mode = idle_mode;
usc_set_txidle( info );
spin_unlock_irqrestore(&info->irq_spinlock,flags);
return 0;
} /* end of mgsl_set_txidle() */
/* mgsl_txenable()
*
* enable or disable the transmitter
*
* Arguments:
*
* info pointer to device instance data
* enable 1 = enable, 0 = disable
*
* Return Value: 0 if success, otherwise error code
*/
static int mgsl_txenable(struct mgsl_struct * info, int enable)
{
unsigned long flags;
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__,__LINE__,
info->device_name, enable);
spin_lock_irqsave(&info->irq_spinlock,flags);
if ( enable ) {
if ( !info->tx_enabled ) {
usc_start_transmitter(info);
/*--------------------------------------------------
* if HDLC/SDLC Loop mode, attempt to insert the
* station in the 'loop' by setting CMR:13. Upon
* receipt of the next GoAhead (RxAbort) sequence,
* the OnLoop indicator (CCSR:7) should go active
* to indicate that we are on the loop
*--------------------------------------------------*/
if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
usc_loopmode_insert_request( info );
}
} else {
if ( info->tx_enabled )
usc_stop_transmitter(info);
}
spin_unlock_irqrestore(&info->irq_spinlock,flags);
return 0;
} /* end of mgsl_txenable() */
/* mgsl_txabort() abort send HDLC frame
*
* Arguments: info pointer to device instance data
* Return Value: 0 if success, otherwise error code
*/
static int mgsl_txabort(struct mgsl_struct * info)
{
unsigned long flags;
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):mgsl_txabort(%s)\n", __FILE__,__LINE__,
info->device_name);
spin_lock_irqsave(&info->irq_spinlock,flags);
if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC )
{
if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
usc_loopmode_cancel_transmit( info );
else
usc_TCmd(info,TCmd_SendAbort);
}
spin_unlock_irqrestore(&info->irq_spinlock,flags);
return 0;
} /* end of mgsl_txabort() */
/* mgsl_rxenable() enable or disable the receiver
*
* Arguments: info pointer to device instance data
* enable 1 = enable, 0 = disable
* Return Value: 0 if success, otherwise error code
*/
static int mgsl_rxenable(struct mgsl_struct * info, int enable)
{
unsigned long flags;
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__,__LINE__,
info->device_name, enable);
spin_lock_irqsave(&info->irq_spinlock,flags);
if ( enable ) {
if ( !info->rx_enabled )
usc_start_receiver(info);
} else {
if ( info->rx_enabled )
usc_stop_receiver(info);
}
spin_unlock_irqrestore(&info->irq_spinlock,flags);
return 0;
} /* end of mgsl_rxenable() */
/* mgsl_wait_event() wait for specified event to occur
*
* Arguments: info pointer to device instance data
* mask pointer to bitmask of events to wait for
* Return Value: 0 if successful and bit mask updated with
* of events triggerred,
* otherwise error code
*/
static int mgsl_wait_event(struct mgsl_struct * info, int __user * mask_ptr)
{
unsigned long flags;
int s;
int rc=0;
struct mgsl_icount cprev, cnow;
int events;
int mask;
struct _input_signal_events oldsigs, newsigs;
DECLARE_WAITQUEUE(wait, current);
COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
if (rc) {
return -EFAULT;
}
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__,__LINE__,
info->device_name, mask);
spin_lock_irqsave(&info->irq_spinlock,flags);
/* return immediately if state matches requested events */
usc_get_serial_signals(info);
s = info->serial_signals;
events = mask &
( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
if (events) {
spin_unlock_irqrestore(&info->irq_spinlock,flags);
goto exit;
}
/* save current irq counts */
cprev = info->icount;
oldsigs = info->input_signal_events;
/* enable hunt and idle irqs if needed */
if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
u16 oldreg = usc_InReg(info,RICR);
u16 newreg = oldreg +
(mask & MgslEvent_ExitHuntMode ? RXSTATUS_EXITED_HUNT:0) +
(mask & MgslEvent_IdleReceived ? RXSTATUS_IDLE_RECEIVED:0);
if (oldreg != newreg)
usc_OutReg(info, RICR, newreg);
}
set_current_state(TASK_INTERRUPTIBLE);
add_wait_queue(&info->event_wait_q, &wait);
spin_unlock_irqrestore(&info->irq_spinlock,flags);
for(;;) {
schedule();
if (signal_pending(current)) {
rc = -ERESTARTSYS;
break;
}
/* get current irq counts */
spin_lock_irqsave(&info->irq_spinlock,flags);
cnow = info->icount;
newsigs = info->input_signal_events;
set_current_state(TASK_INTERRUPTIBLE);
spin_unlock_irqrestore(&info->irq_spinlock,flags);
/* if no change, wait aborted for some reason */
if (newsigs.dsr_up == oldsigs.dsr_up &&
newsigs.dsr_down == oldsigs.dsr_down &&
newsigs.dcd_up == oldsigs.dcd_up &&
newsigs.dcd_down == oldsigs.dcd_down &&
newsigs.cts_up == oldsigs.cts_up &&
newsigs.cts_down == oldsigs.cts_down &&
newsigs.ri_up == oldsigs.ri_up &&
newsigs.ri_down == oldsigs.ri_down &&
cnow.exithunt == cprev.exithunt &&
cnow.rxidle == cprev.rxidle) {
rc = -EIO;
break;
}
events = mask &
( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
(newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
(newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
(newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
(newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
(newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
(newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
(newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
(cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
(cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
if (events)
break;
cprev = cnow;
oldsigs = newsigs;
}
remove_wait_queue(&info->event_wait_q, &wait);
set_current_state(TASK_RUNNING);
if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
spin_lock_irqsave(&info->irq_spinlock,flags);
if (!waitqueue_active(&info->event_wait_q)) {
/* disable enable exit hunt mode/idle rcvd IRQs */
usc_OutReg(info, RICR, usc_InReg(info,RICR) &
~(RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED));
}
spin_unlock_irqrestore(&info->irq_spinlock,flags);
}
exit:
if ( rc == 0 )
PUT_USER(rc, events, mask_ptr);
return rc;
} /* end of mgsl_wait_event() */
static int modem_input_wait(struct mgsl_struct *info,int arg)
{
unsigned long flags;
int rc;
struct mgsl_icount cprev, cnow;
DECLARE_WAITQUEUE(wait, current);
/* save current irq counts */
spin_lock_irqsave(&info->irq_spinlock,flags);
cprev = info->icount;
add_wait_queue(&info->status_event_wait_q, &wait);
set_current_state(TASK_INTERRUPTIBLE);
spin_unlock_irqrestore(&info->irq_spinlock,flags);
for(;;) {
schedule();
if (signal_pending(current)) {
rc = -ERESTARTSYS;
break;
}
/* get new irq counts */
spin_lock_irqsave(&info->irq_spinlock,flags);
cnow = info->icount;
set_current_state(TASK_INTERRUPTIBLE);
spin_unlock_irqrestore(&info->irq_spinlock,flags);
/* if no change, wait aborted for some reason */
if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
rc = -EIO;
break;
}
/* check for change in caller specified modem input */
if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
(arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
(arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
(arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
rc = 0;
break;
}
cprev = cnow;
}
remove_wait_queue(&info->status_event_wait_q, &wait);
set_current_state(TASK_RUNNING);
return rc;
}
/* return the state of the serial control and status signals
*/
static int tiocmget(struct tty_struct *tty, struct file *file)
{
struct mgsl_struct *info = tty->driver_data;
unsigned int result;
unsigned long flags;
spin_lock_irqsave(&info->irq_spinlock,flags);
usc_get_serial_signals(info);
spin_unlock_irqrestore(&info->irq_spinlock,flags);
result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):%s tiocmget() value=%08X\n",
__FILE__,__LINE__, info->device_name, result );
return result;
}
/* set modem control signals (DTR/RTS)
*/
static int tiocmset(struct tty_struct *tty, struct file *file,
unsigned int set, unsigned int clear)
{
struct mgsl_struct *info = tty->driver_data;
unsigned long flags;
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):%s tiocmset(%x,%x)\n",
__FILE__,__LINE__,info->device_name, set, clear);
if (set & TIOCM_RTS)
info->serial_signals |= SerialSignal_RTS;
if (set & TIOCM_DTR)
info->serial_signals |= SerialSignal_DTR;
if (clear & TIOCM_RTS)
info->serial_signals &= ~SerialSignal_RTS;
if (clear & TIOCM_DTR)
info->serial_signals &= ~SerialSignal_DTR;
spin_lock_irqsave(&info->irq_spinlock,flags);
usc_set_serial_signals(info);
spin_unlock_irqrestore(&info->irq_spinlock,flags);
return 0;
}
/* mgsl_break() Set or clear transmit break condition
*
* Arguments: tty pointer to tty instance data
* break_state -1=set break condition, 0=clear
* Return Value: error code
*/
static int mgsl_break(struct tty_struct *tty, int break_state)
{
struct mgsl_struct * info = tty->driver_data;
unsigned long flags;
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):mgsl_break(%s,%d)\n",
__FILE__,__LINE__, info->device_name, break_state);
if (mgsl_paranoia_check(info, tty->name, "mgsl_break"))
return -EINVAL;
spin_lock_irqsave(&info->irq_spinlock,flags);
if (break_state == -1)
usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7));
else
usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7));
spin_unlock_irqrestore(&info->irq_spinlock,flags);
return 0;
} /* end of mgsl_break() */
/* mgsl_ioctl() Service an IOCTL request
*
* Arguments:
*
* tty pointer to tty instance data
* file pointer to associated file object for device
* cmd IOCTL command code
* arg command argument/context
*
* Return Value: 0 if success, otherwise error code
*/
static int mgsl_ioctl(struct tty_struct *tty, struct file * file,
unsigned int cmd, unsigned long arg)
{
struct mgsl_struct * info = tty->driver_data;
int ret;
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
info->device_name, cmd );
if (mgsl_paranoia_check(info, tty->name, "mgsl_ioctl"))
return -ENODEV;
if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
(cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
if (tty->flags & (1 << TTY_IO_ERROR))
return -EIO;
}
lock_kernel();
ret = mgsl_ioctl_common(info, cmd, arg);
unlock_kernel();
return ret;
}
static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg)
{
int error;
struct mgsl_icount cnow; /* kernel counter temps */
void __user *argp = (void __user *)arg;
struct serial_icounter_struct __user *p_cuser; /* user space */
unsigned long flags;
switch (cmd) {
case MGSL_IOCGPARAMS:
return mgsl_get_params(info, argp);
case MGSL_IOCSPARAMS:
return mgsl_set_params(info, argp);
case MGSL_IOCGTXIDLE:
return mgsl_get_txidle(info, argp);
case MGSL_IOCSTXIDLE:
return mgsl_set_txidle(info,(int)arg);
case MGSL_IOCTXENABLE:
return mgsl_txenable(info,(int)arg);
case MGSL_IOCRXENABLE:
return mgsl_rxenable(info,(int)arg);
case MGSL_IOCTXABORT:
return mgsl_txabort(info);
case MGSL_IOCGSTATS:
return mgsl_get_stats(info, argp);
case MGSL_IOCWAITEVENT:
return mgsl_wait_event(info, argp);
case MGSL_IOCLOOPTXDONE:
return mgsl_loopmode_send_done(info);
/* Wait for modem input (DCD,RI,DSR,CTS) change
* as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
*/
case TIOCMIWAIT:
return modem_input_wait(info,(int)arg);
/*
* Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
* Return: write counters to the user passed counter struct
* NB: both 1->0 and 0->1 transitions are counted except for
* RI where only 0->1 is counted.
*/
case TIOCGICOUNT:
spin_lock_irqsave(&info->irq_spinlock,flags);
cnow = info->icount;
spin_unlock_irqrestore(&info->irq_spinlock,flags);
p_cuser = argp;
PUT_USER(error,cnow.cts, &p_cuser->cts);
if (error) return error;
PUT_USER(error,cnow.dsr, &p_cuser->dsr);
if (error) return error;
PUT_USER(error,cnow.rng, &p_cuser->rng);
if (error) return error;
PUT_USER(error,cnow.dcd, &p_cuser->dcd);
if (error) return error;
PUT_USER(error,cnow.rx, &p_cuser->rx);
if (error) return error;
PUT_USER(error,cnow.tx, &p_cuser->tx);
if (error) return error;
PUT_USER(error,cnow.frame, &p_cuser->frame);
if (error) return error;
PUT_USER(error,cnow.overrun, &p_cuser->overrun);
if (error) return error;
PUT_USER(error,cnow.parity, &p_cuser->parity);
if (error) return error;
PUT_USER(error,cnow.brk, &p_cuser->brk);
if (error) return error;
PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
if (error) return error;
return 0;
default:
return -ENOIOCTLCMD;
}
return 0;
}
/* mgsl_set_termios()
*
* Set new termios settings
*
* Arguments:
*
* tty pointer to tty structure
* termios pointer to buffer to hold returned old termios
*
* Return Value: None
*/
static void mgsl_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
{
struct mgsl_struct *info = tty->driver_data;
unsigned long flags;
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):mgsl_set_termios %s\n", __FILE__,__LINE__,
tty->driver->name );
mgsl_change_params(info);
/* Handle transition to B0 status */
if (old_termios->c_cflag & CBAUD &&
!(tty->termios->c_cflag & CBAUD)) {
info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
spin_lock_irqsave(&info->irq_spinlock,flags);
usc_set_serial_signals(info);
spin_unlock_irqrestore(&info->irq_spinlock,flags);
}
/* Handle transition away from B0 status */
if (!(old_termios->c_cflag & CBAUD) &&
tty->termios->c_cflag & CBAUD) {
info->serial_signals |= SerialSignal_DTR;
if (!(tty->termios->c_cflag & CRTSCTS) ||
!test_bit(TTY_THROTTLED, &tty->flags)) {
info->serial_signals |= SerialSignal_RTS;
}
spin_lock_irqsave(&info->irq_spinlock,flags);
usc_set_serial_signals(info);
spin_unlock_irqrestore(&info->irq_spinlock,flags);
}
/* Handle turning off CRTSCTS */
if (old_termios->c_cflag & CRTSCTS &&
!(tty->termios->c_cflag & CRTSCTS)) {
tty->hw_stopped = 0;
mgsl_start(tty);
}
} /* end of mgsl_set_termios() */
/* mgsl_close()
*
* Called when port is closed. Wait for remaining data to be
* sent. Disable port and free resources.
*
* Arguments:
*
* tty pointer to open tty structure
* filp pointer to open file object
*
* Return Value: None
*/
static void mgsl_close(struct tty_struct *tty, struct file * filp)
{
struct mgsl_struct * info = tty->driver_data;
if (mgsl_paranoia_check(info, tty->name, "mgsl_close"))
return;
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
__FILE__,__LINE__, info->device_name, info->port.count);
if (tty_port_close_start(&info->port, tty, filp) == 0)
goto cleanup;
if (info->port.flags & ASYNC_INITIALIZED)
mgsl_wait_until_sent(tty, info->timeout);
mgsl_flush_buffer(tty);
tty_ldisc_flush(tty);
shutdown(info);
tty_port_close_end(&info->port, tty);
info->port.tty = NULL;
cleanup:
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__,__LINE__,
tty->driver->name, info->port.count);
} /* end of mgsl_close() */
/* mgsl_wait_until_sent()
*
* Wait until the transmitter is empty.
*
* Arguments:
*
* tty pointer to tty info structure
* timeout time to wait for send completion
*
* Return Value: None
*/
static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout)
{
struct mgsl_struct * info = tty->driver_data;
unsigned long orig_jiffies, char_time;
if (!info )
return;
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
__FILE__,__LINE__, info->device_name );
if (mgsl_paranoia_check(info, tty->name, "mgsl_wait_until_sent"))
return;
if (!(info->port.flags & ASYNC_INITIALIZED))
goto exit;
orig_jiffies = jiffies;
/* Set check interval to 1/5 of estimated time to
* send a character, and make it at least 1. The check
* interval should also be less than the timeout.
* Note: use tight timings here to satisfy the NIST-PCTS.
*/
lock_kernel();
if ( info->params.data_rate ) {
char_time = info->timeout/(32 * 5);
if (!char_time)
char_time++;
} else
char_time = 1;
if (timeout)
char_time = min_t(unsigned long, char_time, timeout);
if ( info->params.mode == MGSL_MODE_HDLC ||
info->params.mode == MGSL_MODE_RAW ) {
while (info->tx_active) {
msleep_interruptible(jiffies_to_msecs(char_time));
if (signal_pending(current))
break;
if (timeout && time_after(jiffies, orig_jiffies + timeout))
break;
}
} else {
while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) &&
info->tx_enabled) {
msleep_interruptible(jiffies_to_msecs(char_time));
if (signal_pending(current))
break;
if (timeout && time_after(jiffies, orig_jiffies + timeout))
break;
}
}
unlock_kernel();
exit:
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
__FILE__,__LINE__, info->device_name );
} /* end of mgsl_wait_until_sent() */
/* mgsl_hangup()
*
* Called by tty_hangup() when a hangup is signaled.
* This is the same as to closing all open files for the port.
*
* Arguments: tty pointer to associated tty object
* Return Value: None
*/
static void mgsl_hangup(struct tty_struct *tty)
{
struct mgsl_struct * info = tty->driver_data;
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):mgsl_hangup(%s)\n",
__FILE__,__LINE__, info->device_name );
if (mgsl_paranoia_check(info, tty->name, "mgsl_hangup"))
return;
mgsl_flush_buffer(tty);
shutdown(info);
info->port.count = 0;
info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
info->port.tty = NULL;
wake_up_interruptible(&info->port.open_wait);
} /* end of mgsl_hangup() */
/*
* carrier_raised()
*
* Return true if carrier is raised
*/
static int carrier_raised(struct tty_port *port)
{
unsigned long flags;
struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
spin_lock_irqsave(&info->irq_spinlock, flags);
usc_get_serial_signals(info);
spin_unlock_irqrestore(&info->irq_spinlock, flags);
return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
}
static void raise_dtr_rts(struct tty_port *port)
{
struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
unsigned long flags;
spin_lock_irqsave(&info->irq_spinlock,flags);
info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
usc_set_serial_signals(info);
spin_unlock_irqrestore(&info->irq_spinlock,flags);
}
/* block_til_ready()
*
* Block the current process until the specified port
* is ready to be opened.
*
* Arguments:
*
* tty pointer to tty info structure
* filp pointer to open file object
* info pointer to device instance data
*
* Return Value: 0 if success, otherwise error code
*/
static int block_til_ready(struct tty_struct *tty, struct file * filp,
struct mgsl_struct *info)
{
DECLARE_WAITQUEUE(wait, current);
int retval;
bool do_clocal = false;
bool extra_count = false;
unsigned long flags;
int dcd;
struct tty_port *port = &info->port;
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):block_til_ready on %s\n",
__FILE__,__LINE__, tty->driver->name );
if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
/* nonblock mode is set or port is not enabled */
port->flags |= ASYNC_NORMAL_ACTIVE;
return 0;
}
if (tty->termios->c_cflag & CLOCAL)
do_clocal = true;
/* Wait for carrier detect and the line to become
* free (i.e., not in use by the callout). While we are in
* this loop, port->count is dropped by one, so that
* mgsl_close() knows when to free things. We restore it upon
* exit, either normal or abnormal.
*/
retval = 0;
add_wait_queue(&port->open_wait, &wait);
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):block_til_ready before block on %s count=%d\n",
__FILE__,__LINE__, tty->driver->name, port->count );
spin_lock_irqsave(&info->irq_spinlock, flags);
if (!tty_hung_up_p(filp)) {
extra_count = true;
port->count--;
}
spin_unlock_irqrestore(&info->irq_spinlock, flags);
port->blocked_open++;
while (1) {
if (tty->termios->c_cflag & CBAUD)
tty_port_raise_dtr_rts(port);
set_current_state(TASK_INTERRUPTIBLE);
if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
retval = (port->flags & ASYNC_HUP_NOTIFY) ?
-EAGAIN : -ERESTARTSYS;
break;
}
dcd = tty_port_carrier_raised(&info->port);
if (!(port->flags & ASYNC_CLOSING) && (do_clocal || dcd))
break;
if (signal_pending(current)) {
retval = -ERESTARTSYS;
break;
}
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):block_til_ready blocking on %s count=%d\n",
__FILE__,__LINE__, tty->driver->name, port->count );
schedule();
}
set_current_state(TASK_RUNNING);
remove_wait_queue(&port->open_wait, &wait);
/* FIXME: Racy on hangup during close wait */
if (extra_count)
port->count++;
port->blocked_open--;
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
__FILE__,__LINE__, tty->driver->name, port->count );
if (!retval)
port->flags |= ASYNC_NORMAL_ACTIVE;
return retval;
} /* end of block_til_ready() */
/* mgsl_open()
*
* Called when a port is opened. Init and enable port.
* Perform serial-specific initialization for the tty structure.
*
* Arguments: tty pointer to tty info structure
* filp associated file pointer
*
* Return Value: 0 if success, otherwise error code
*/
static int mgsl_open(struct tty_struct *tty, struct file * filp)
{
struct mgsl_struct *info;
int retval, line;
unsigned long flags;
/* verify range of specified line number */
line = tty->index;
if ((line < 0) || (line >= mgsl_device_count)) {
printk("%s(%d):mgsl_open with invalid line #%d.\n",
__FILE__,__LINE__,line);
return -ENODEV;
}
/* find the info structure for the specified line */
info = mgsl_device_list;
while(info && info->line != line)
info = info->next_device;
if (mgsl_paranoia_check(info, tty->name, "mgsl_open"))
return -ENODEV;
tty->driver_data = info;
info->port.tty = tty;
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
__FILE__,__LINE__,tty->driver->name, info->port.count);
/* If port is closing, signal caller to try again */
if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
if (info->port.flags & ASYNC_CLOSING)
interruptible_sleep_on(&info->port.close_wait);
retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
-EAGAIN : -ERESTARTSYS);
goto cleanup;
}
info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
spin_lock_irqsave(&info->netlock, flags);
if (info->netcount) {
retval = -EBUSY;
spin_unlock_irqrestore(&info->netlock, flags);
goto cleanup;
}
info->port.count++;
spin_unlock_irqrestore(&info->netlock, flags);
if (info->port.count == 1) {
/* 1st open on this device, init hardware */
retval = startup(info);
if (retval < 0)
goto cleanup;
}
retval = block_til_ready(tty, filp, info);
if (retval) {
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):block_til_ready(%s) returned %d\n",
__FILE__,__LINE__, info->device_name, retval);
goto cleanup;
}
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s(%d):mgsl_open(%s) success\n",
__FILE__,__LINE__, info->device_name);
retval = 0;
cleanup:
if (retval) {
if (tty->count == 1)
info->port.tty = NULL; /* tty layer will release tty struct */
if(info->port.count)
info->port.count--;
}
return retval;
} /* end of mgsl_open() */
/*
* /proc fs routines....
*/
static inline int line_info(char *buf, struct mgsl_struct *info)
{
char stat_buf[30];
int ret;
unsigned long flags;
if (info->bus_type == MGSL_BUS_TYPE_PCI) {
ret = sprintf(buf, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
info->device_name, info->io_base, info->irq_level,
info->phys_memory_base, info->phys_lcr_base);
} else {
ret = sprintf(buf, "%s:(E)ISA io:%04X irq:%d dma:%d",
info->device_name, info->io_base,
info->irq_level, info->dma_level);
}
/* output current serial signal states */
spin_lock_irqsave(&info->irq_spinlock,flags);
usc_get_serial_signals(info);
spin_unlock_irqrestore(&info->irq_spinlock,flags);
stat_buf[0] = 0;
stat_buf[1] = 0;
if (info->serial_signals & SerialSignal_RTS)
strcat(stat_buf, "|RTS");
if (info->serial_signals & SerialSignal_CTS)
strcat(stat_buf, "|CTS");
if (info->serial_signals & SerialSignal_DTR)
strcat(stat_buf, "|DTR");
if (info->serial_signals & SerialSignal_DSR)
strcat(stat_buf, "|DSR");
if (info->serial_signals & SerialSignal_DCD)
strcat(stat_buf, "|CD");
if (info->serial_signals & SerialSignal_RI)
strcat(stat_buf, "|RI");
if (info->params.mode == MGSL_MODE_HDLC ||
info->params.mode == MGSL_MODE_RAW ) {
ret += sprintf(buf+ret, " HDLC txok:%d rxok:%d",
info->icount.txok, info->icount.rxok);
if (info->icount.txunder)
ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
if (info->icount.txabort)
ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
if (info->icount.rxshort)
ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
if (info->icount.rxlong)
ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
if (info->icount.rxover)
ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
if (info->icount.rxcrc)
ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
} else {
ret += sprintf(buf+ret, " ASYNC tx:%d rx:%d",
info->icount.tx, info->icount.rx);
if (info->icount.frame)
ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
if (info->icount.parity)
ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
if (info->icount.brk)
ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
if (info->icount.overrun)
ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
}
/* Append serial signal status to end */
ret += sprintf(buf+ret, " %s\n", stat_buf+1);
ret += sprintf(buf+ret, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
info->tx_active,info->bh_requested,info->bh_running,
info->pending_bh);
spin_lock_irqsave(&info->irq_spinlock,flags);
{
u16 Tcsr = usc_InReg( info, TCSR );
u16 Tdmr = usc_InDmaReg( info, TDMR );
u16 Ticr = usc_InReg( info, TICR );
u16 Rscr = usc_InReg( info, RCSR );
u16 Rdmr = usc_InDmaReg( info, RDMR );
u16 Ricr = usc_InReg( info, RICR );
u16 Icr = usc_InReg( info, ICR );
u16 Dccr = usc_InReg( info, DCCR );
u16 Tmr = usc_InReg( info, TMR );
u16 Tccr = usc_InReg( info, TCCR );
u16 Ccar = inw( info->io_base + CCAR );
ret += sprintf(buf+ret, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
"ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
Tcsr,Tdmr,Ticr,Rscr,Rdmr,Ricr,Icr,Dccr,Tmr,Tccr,Ccar );
}
spin_unlock_irqrestore(&info->irq_spinlock,flags);
return ret;
} /* end of line_info() */
/* mgsl_read_proc()
*
* Called to print information about devices
*
* Arguments:
* page page of memory to hold returned info
* start
* off
* count
* eof
* data
*
* Return Value:
*/
static int mgsl_read_proc(char *page, char **start, off_t off, int count,
int *eof, void *data)
{
int len = 0, l;
off_t begin = 0;
struct mgsl_struct *info;
len += sprintf(page, "synclink driver:%s\n", driver_version);
info = mgsl_device_list;
while( info ) {
l = line_info(page + len, info);
len += l;
if (len+begin > off+count)
goto done;
if (len+begin < off) {
begin += len;
len = 0;
}
info = info->next_device;
}
*eof = 1;
done:
if (off >= len+begin)
return 0;
*start = page + (off-begin);
return ((count < begin+len-off) ? count : begin+len-off);
} /* end of mgsl_read_proc() */
/* mgsl_allocate_dma_buffers()
*
* Allocate and format DMA buffers (ISA adapter)
* or format shared memory buffers (PCI adapter).
*
* Arguments: info pointer to device instance data
* Return Value: 0 if success, otherwise error
*/
static int mgsl_allocate_dma_buffers(struct mgsl_struct *info)
{
unsigned short BuffersPerFrame;
info->last_mem_alloc = 0;
/* Calculate the number of DMA buffers necessary to hold the */
/* largest allowable frame size. Note: If the max frame size is */
/* not an even multiple of the DMA buffer size then we need to */
/* round the buffer count per frame up one. */
BuffersPerFrame = (unsigned short)(info->max_frame_size/DMABUFFERSIZE);
if ( info->max_frame_size % DMABUFFERSIZE )
BuffersPerFrame++;
if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
/*
* The PCI adapter has 256KBytes of shared memory to use.
* This is 64 PAGE_SIZE buffers.
*
* The first page is used for padding at this time so the
* buffer list does not begin at offset 0 of the PCI
* adapter's shared memory.
*
* The 2nd page is used for the buffer list. A 4K buffer
* list can hold 128 DMA_BUFFER structures at 32 bytes
* each.
*
* This leaves 62 4K pages.
*
* The next N pages are used for transmit frame(s). We
* reserve enough 4K page blocks to hold the required
* number of transmit dma buffers (num_tx_dma_buffers),
* each of MaxFrameSize size.
*
* Of the remaining pages (62-N), determine how many can
* be used to receive full MaxFrameSize inbound frames
*/
info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
info->rx_buffer_count = 62 - info->tx_buffer_count;
} else {
/* Calculate the number of PAGE_SIZE buffers needed for */
/* receive and transmit DMA buffers. */
/* Calculate the number of DMA buffers necessary to */
/* hold 7 max size receive frames and one max size transmit frame. */
/* The receive buffer count is bumped by one so we avoid an */
/* End of List condition if all receive buffers are used when */
/* using linked list DMA buffers. */
info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6;
/*
* limit total TxBuffers & RxBuffers to 62 4K total
* (ala PCI Allocation)
*/
if ( (info->tx_buffer_count + info->rx_buffer_count) > 62 )
info->rx_buffer_count = 62 - info->tx_buffer_count;
}
if ( debug_level >= DEBUG_LEVEL_INFO )
printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
__FILE__,__LINE__, info->tx_buffer_count,info->rx_buffer_count);
if ( mgsl_alloc_buffer_list_memory( info ) < 0 ||
mgsl_alloc_frame_memory(info, info->rx_buffer_list, info->rx_buffer_count) < 0 ||
mgsl_alloc_frame_memory(info, info->tx_buffer_list, info->tx_buffer_count) < 0 ||
mgsl_alloc_intermediate_rxbuffer_memory(info) < 0 ||
mgsl_alloc_intermediate_txbuffer_memory(info) < 0 ) {
printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__,__LINE__);
return -ENOMEM;
}
mgsl_reset_rx_dma_buffers( info );
mgsl_reset_tx_dma_buffers( info );
return 0;
} /* end of mgsl_allocate_dma_buffers() */
/*
* mgsl_alloc_buffer_list_memory()
*
* Allocate a common DMA buffer for use as the
* receive and transmit buffer lists.
*
* A buffer list is a set of buffer entries where each entry contains
* a pointer to an actual buffer and a pointer to the next buffer entry
* (plus some other info about the buffer).
*
* The buffer entries for a list are built to form a circular list so
* that when the entire list has been traversed you start back at the
* beginning.
*
* This function allocates memory for just the buffer entries.
* The links (pointer to next entry) are filled in with the physical
* address of the next entry so the adapter can navigate the list
* using bus master DMA. The pointers to the actual buffers are filled
* out later when the actual buffers are allocated.
*
* Arguments: info pointer to device instance data
* Return Value: 0 if success, otherwise error
*/
static int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info )
{
unsigned int i;
if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
/* PCI adapter uses shared memory. */
info->buffer_list = info->memory_base + info->last_mem_alloc;
info->buffer_list_phys = info->last_mem_alloc;
info->last_mem_alloc += BUFFERLISTSIZE;
} else {
/* ISA adapter uses system memory. */
/* The buffer lists are allocated as a common buffer that both */
/* the processor and adapter can access. This allows the driver to */
/* inspect portions of the buffer while other portions are being */
/* updated by the adapter using Bus Master DMA. */
info->buffer_list = dma_alloc_coherent(NULL, BUFFERLISTSIZE, &info->buffer_list_dma_addr, GFP_KERNEL);
if (info->buffer_list == NULL)
return -ENOMEM;
info->buffer_list_phys = (u32)(info->buffer_list_dma_addr);
}
/* We got the memory for the buffer entry lists. */
/* Initialize the memory block to all zeros. */
memset( info->buffer_list, 0, BUFFERLISTSIZE );
/* Save virtual address pointers to the receive and */
/* transmit buffer lists. (Receive 1st). These pointers will */
/* be used by the processor to access the lists. */
info->rx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
info->tx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
info->tx_buffer_list += info->rx_buffer_count;
/*
* Build the links for the buffer entry lists such that
* two circular lists are built. (Transmit and Receive).
*
* Note: the links are physical addresses
* which are read by the adapter to determine the next
* buffer entry to use.
*/
for ( i = 0; i < info->rx_buffer_count; i++ ) {
/* calculate and store physical address of this buffer entry */
info->rx_buffer_list[i].phys_entry =
info->buffer_list_phys + (i * sizeof(DMABUFFERENTRY));
/* calculate and store physical address of */
/* next entry in cirular list of entries */
info->rx_buffer_list[i].link = info->buffer_list_phys;
if ( i < info->rx_buffer_count - 1 )
info->rx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
}
for ( i = 0; i < info->tx_buffer_count; i++ ) {
/* calculate and store physical address of this buffer entry */
info->tx_buffer_list[i].phys_entry = info->buffer_list_phys +
((info->rx_buffer_count + i) * sizeof(DMABUFFERENTRY));
/* calculate and store physical address of */
/* next entry in cirular list of entries */
info->tx_buffer_list[i].link = info->buffer_list_phys +
info->rx_buffer_count * sizeof(DMABUFFERENTRY);
if ( i < info->tx_buffer_count - 1 )
info->tx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
}
return 0;
} /* end of mgsl_alloc_buffer_list_memory() */
/* Free DMA buffers allocated for use as the
* receive and transmit buffer lists.
* Warning:
*
* The data transfer buffers associated with the buffer list
* MUST be freed before freeing the buffer list itself because
* the buffer list contains the information necessary to free
* the individual buffers!
*/
static void mgsl_free_buffer_list_memory( struct mgsl_struct *info )
{
if (info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI)
dma_free_coherent(NULL, BUFFERLISTSIZE, info->buffer_list, info->buffer_list_dma_addr);
info->buffer_list = NULL;
info->rx_buffer_list = NULL;
info->tx_buffer_list = NULL;
} /* end of mgsl_free_buffer_list_memory() */
/*
* mgsl_alloc_frame_memory()
*
* Allocate the frame DMA buffers used by the specified buffer list.
* Each DMA buffer will be one memory page in size. This is necessary
* because memory can fragment enough that it may be impossible
* contiguous pages.
*
* Arguments:
*
* info pointer to device instance data
* BufferList pointer to list of buffer entries
* Buffercount count of buffer entries in buffer list
*
* Return Value: 0 if success, otherwise -ENOMEM
*/
static int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount)
{
int i;
u32 phys_addr;
/* Allocate page sized buffers for the receive buffer list */
for ( i = 0; i < Buffercount; i++ ) {
if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
/* PCI adapter uses shared memory buffers. */
BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
phys_addr = info->last_mem_alloc;
info->last_mem_alloc += DMABUFFERSIZE;
} else {
/* ISA adapter uses system memory. */
BufferList[i].virt_addr = dma_alloc_coherent(NULL, DMABUFFERSIZE, &BufferList[i].dma_addr, GFP_KERNEL);
if (BufferList[i].virt_addr == NULL)
return -ENOMEM;
phys_addr = (u32)(BufferList[i].dma_addr);
}
BufferList[i].phys_addr = phys_addr;
}
return 0;
} /* end of mgsl_alloc_frame_memory() */
/*
* mgsl_free_frame_memory()
*
* Free the buffers associated with
* each buffer entry of a buffer list.
*
* Arguments:
*
* info pointer to device instance data
* BufferList pointer to list of buffer entries
* Buffercount count of buffer entries in buffer list
*
* Return Value: None
*/
static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList, int Buffercount)
{
int i;
if ( BufferList ) {
for ( i = 0 ; i < Buffercount ; i++ ) {
if ( BufferList[i].virt_addr ) {
if ( info->bus_type != MGSL_BUS_TYPE_PCI )
dma_free_coherent(NULL, DMABUFFERSIZE, BufferList[i].virt_addr, BufferList[i].dma_addr);
BufferList[i].virt_addr = NULL;
}
}
}
} /* end of mgsl_free_frame_memory() */
/* mgsl_free_dma_buffers()
*
* Free DMA buffers
*
* Arguments: info pointer to device instance data
* Return Value: None
*/
static void mgsl_free_dma_buffers( struct mgsl_struct *info )
{
mgsl_free_frame_memory( info, info->rx_buffer_list, info->rx_buffer_count );
mgsl_free_frame_memory( info, info->tx_buffer_list, info->tx_buffer_count );
mgsl_free_buffer_list_memory( info );
} /* end of mgsl_free_dma_buffers() */
/*
* mgsl_alloc_intermediate_rxbuffer_memory()
*
* Allocate a buffer large enough to hold max_frame_size. This buffer
* is used to pass an assembled frame to the line discipline.
*
* Arguments:
*
* info pointer to device instance data
*
* Return Value: 0 if success, otherwise -ENOMEM
*/
static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info)
{
info->intermediate_rxbuffer = kmalloc(info->max_frame_size, GFP_KERNEL | GFP_DMA);
if ( info->intermediate_rxbuffer == NULL )
return -ENOMEM;
return 0;
} /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
/*
* mgsl_free_intermediate_rxbuffer_memory()
*
*
* Arguments:
*
* info pointer to device instance data
*
* Return Value: None
*/
static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info)
{
kfree(info->intermediate_rxbuffer);
info->intermediate_rxbuffer = NULL;
} /* end of mgsl_free_intermediate_rxbuffer_memory() */
/*
* mgsl_alloc_intermediate_txbuffer_memory()
*
* Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
* This buffer is used to load transmit frames into the adapter's dma transfer
* buffers when there is sufficient space.
*
* Arguments:
*
* info pointer to device instance data
*
* Return Value: 0 if success, otherwise -ENOMEM
*/
static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info)
{
int i;
if ( debug_level >= DEBUG_LEVEL_INFO )
printk("%s %s(%d) allocating %d tx holding buffers\n",
info->device_name, __FILE__,__LINE__,info->num_tx_holding_buffers);
memset(info->tx_holding_buffers,0,sizeof(info->tx_holding_buffers));
for ( i=0; i<info->num_tx_holding_buffers; ++i) {
info->tx_holding_buffers[i].buffer =
kmalloc(info->max_frame_size, GFP_KERNEL);
if (info->tx_holding_buffers[i].buffer == NULL) {
for (--i; i >= 0; i--) {
kfree(info->tx_holding_buffers[i].buffer);
info->tx_holding_buffers[i].buffer = NULL;
}
return -ENOMEM;
}
}
return 0;
} /* end of mgsl_alloc_intermediate_txbuffer_memory() */
/*
* mgsl_free_intermediate_txbuffer_memory()
*
*
* Arguments:
*
* info pointer to device instance data
*
* Return Value: None
*/
static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info)
{
int i;
for ( i=0; i<info->num_tx_holding_buffers; ++i ) {
kfree(info->tx_holding_buffers[i].buffer);
info->tx_holding_buffers[i].buffer = NULL;
}
info->get_tx_holding_index = 0;
info->put_tx_holding_index = 0;
info->tx_holding_count = 0;
} /* end of mgsl_free_intermediate_txbuffer_memory() */
/*
* load_next_tx_holding_buffer()
*
* attempts to load the next buffered tx request into the
* tx dma buffers
*
* Arguments:
*
* info pointer to device instance data
*
* Return Value: true if next buffered tx request loaded
* into adapter's tx dma buffer,
* false otherwise
*/
static bool load_next_tx_holding_buffer(struct mgsl_struct *info)
{
bool ret = false;
if ( info->tx_holding_count ) {
/* determine if we have enough tx dma buffers
* to accommodate the next tx frame
*/
struct tx_holding_buffer *ptx =
&info->tx_holding_buffers[info->get_tx_holding_index];
int num_free = num_free_tx_dma_buffers(info);
int num_needed = ptx->buffer_size / DMABUFFERSIZE;
if ( ptx->buffer_size % DMABUFFERSIZE )
++num_needed;
if (num_needed <= num_free) {
info->xmit_cnt = ptx->buffer_size;
mgsl_load_tx_dma_buffer(info,ptx->buffer,ptx->buffer_size);
--info->tx_holding_count;
if ( ++info->get_tx_holding_index >= info->num_tx_holding_buffers)
info->get_tx_holding_index=0;
/* restart transmit timer */
mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(5000));
ret = true;
}
}
return ret;
}
/*
* save_tx_buffer_request()
*
* attempt to store transmit frame request for later transmission
*
* Arguments:
*
* info pointer to device instance data
* Buffer pointer to buffer containing frame to load
* BufferSize size in bytes of frame in Buffer
*
* Return Value: 1 if able to store, 0 otherwise
*/
static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize)
{
struct tx_holding_buffer *ptx;
if ( info->tx_holding_count >= info->num_tx_holding_buffers ) {
return 0; /* all buffers in use */
}
ptx = &info->tx_holding_buffers[info->put_tx_holding_index];
ptx->buffer_size = BufferSize;
memcpy( ptx->buffer, Buffer, BufferSize);
++info->tx_holding_count;
if ( ++info->put_tx_holding_index >= info->num_tx_holding_buffers)
info->put_tx_holding_index=0;
return 1;
}
static int mgsl_claim_resources(struct mgsl_struct *info)
{
if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {
printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
__FILE__,__LINE__,info->device_name, info->io_base);
return -ENODEV;
}
info->io_addr_requested = true;
if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags,
info->device_name, info ) < 0 ) {
printk( "%s(%d):Cant request interrupt on device %s IRQ=%d\n",
__FILE__,__LINE__,info->device_name, info->irq_level );
goto errout;
}
info->irq_requested = true;
if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
__FILE__,__LINE__,info->device_name, info->phys_memory_base);
goto errout;
}
info->shared_mem_requested = true;
if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) {
printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
__FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset);
goto errout;
}
info->lcr_mem_requested = true;
info->memory_base = ioremap_nocache(info->phys_memory_base,
0x40000);
if (!info->memory_base) {
printk( "%s(%d):Cant map shared memory on device %s MemAddr=%08X\n",
__FILE__,__LINE__,info->device_name, info->phys_memory_base );
goto errout;
}
if ( !mgsl_memory_test(info) ) {
printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
__FILE__,__LINE__,info->device_name, info->phys_memory_base );
goto errout;
}
info->lcr_base = ioremap_nocache(info->phys_lcr_base,
PAGE_SIZE);
if (!info->lcr_base) {
printk( "%s(%d):Cant map LCR memory on device %s MemAddr=%08X\n",
__FILE__,__LINE__,info->device_name, info->phys_lcr_base );
goto errout;
}
info->lcr_base += info->lcr_offset;
} else {
/* claim DMA channel */
if (request_dma(info->dma_level,info->device_name) < 0){
printk( "%s(%d):Cant request DMA channel on device %s DMA=%d\n",
__FILE__,__LINE__,info->device_name, info->dma_level );
mgsl_release_resources( info );
return -ENODEV;
}
info->dma_requested = true;
/* ISA adapter uses bus master DMA */
set_dma_mode(info->dma_level,DMA_MODE_CASCADE);
enable_dma(info->dma_level);
}
if ( mgsl_allocate_dma_buffers(info) < 0 ) {
printk( "%s(%d):Cant allocate DMA buffers on device %s DMA=%d\n",
__FILE__,__LINE__,info->device_name, info->dma_level );
goto errout;
}
return 0;
errout:
mgsl_release_resources(info);
return -ENODEV;
} /* end of mgsl_claim_resources() */
static void mgsl_release_resources(struct mgsl_struct *info)
{
if ( debug_level >= DEBUG_LEVEL_INFO )
printk( "%s(%d):mgsl_release_resources(%s) entry\n",
__FILE__,__LINE__,info->device_name );
if ( info->irq_requested ) {
free_irq(info->irq_level, info);
info->irq_requested = false;
}
if ( info->dma_requested ) {
disable_dma(info->dma_level);
free_dma(info->dma_level);
info->dma_requested = false;
}
mgsl_free_dma_buffers(info);
mgsl_free_intermediate_rxbuffer_memory(info);
mgsl_free_intermediate_txbuffer_memory(info);
if ( info->io_addr_requested ) {
release_region(info->io_base,info->io_addr_size);
info->io_addr_requested = false;
}
if ( info->shared_mem_requested ) {
release_mem_region(info->phys_memory_base,0x40000);
info->shared_mem_requested = false;
}
if ( info->lcr_mem_requested ) {
release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
info->lcr_mem_requested = false;
}
if (info->memory_base){
iounmap(info->memory_base);
info->memory_base = NULL;
}
if (info->lcr_base){
iounmap(info->lcr_base - info->lcr_offset);
info->lcr_base = NULL;
}
if ( debug_level >= DEBUG_LEVEL_INFO )
printk( "%s(%d):mgsl_release_resources(%s) exit\n",
__FILE__,__LINE__,info->device_name );
} /* end of mgsl_release_resources() */
/* mgsl_add_device()
*
* Add the specified device instance data structure to the
* global linked list of devices and increment the device count.
*
* Arguments: info pointer to device instance data
* Return Value: None
*/
static void mgsl_add_device( struct mgsl_struct *info )
{
info->next_device = NULL;
info->line = mgsl_device_count;
sprintf(info->device_name,"ttySL%d",info->line);
if (info->line < MAX_TOTAL_DEVICES) {
if (maxframe[info->line])
info->max_frame_size = maxframe[info->line];
if (txdmabufs[info->line]) {
info->num_tx_dma_buffers = txdmabufs[info->line];
if (info->num_tx_dma_buffers < 1)
info->num_tx_dma_buffers = 1;
}
if (txholdbufs[info->line]) {
info->num_tx_holding_buffers = txholdbufs[info->line];
if (info->num_tx_holding_buffers < 1)
info->num_tx_holding_buffers = 1;
else if (info->num_tx_holding_buffers > MAX_TX_HOLDING_BUFFERS)
info->num_tx_holding_buffers = MAX_TX_HOLDING_BUFFERS;
}
}
mgsl_device_count++;
if ( !mgsl_device_list )
mgsl_device_list = info;
else {
struct mgsl_struct *current_dev = mgsl_device_list;
while( current_dev->next_device )
current_dev = current_dev->next_device;
current_dev->next_device = info;
}
if ( info->max_frame_size < 4096 )
info->max_frame_size = 4096;
else if ( info->max_frame_size > 65535 )
info->max_frame_size = 65535;
if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
info->phys_memory_base, info->phys_lcr_base,
info->max_frame_size );
} else {
printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
info->device_name, info->io_base, info->irq_level, info->dma_level,
info->max_frame_size );
}
#if SYNCLINK_GENERIC_HDLC
hdlcdev_init(info);
#endif
} /* end of mgsl_add_device() */
static const struct tty_port_operations mgsl_port_ops = {
.carrier_raised = carrier_raised,
.raise_dtr_rts = raise_dtr_rts,
};
/* mgsl_allocate_device()
*
* Allocate and initialize a device instance structure
*
* Arguments: none
* Return Value: pointer to mgsl_struct if success, otherwise NULL
*/
static struct mgsl_struct* mgsl_allocate_device(void)
{
struct mgsl_struct *info;
info = kzalloc(sizeof(struct mgsl_struct),
GFP_KERNEL);
if (!info) {
printk("Error can't allocate device instance data\n");
} else {
tty_port_init(&info->port);
info->port.ops = &mgsl_port_ops;
info->magic = MGSL_MAGIC;
INIT_WORK(&info->task, mgsl_bh_handler);
info->max_frame_size = 4096;
info->port.close_delay = 5*HZ/10;
info->port.closing_wait = 30*HZ;
init_waitqueue_head(&info->status_event_wait_q);
init_waitqueue_head(&info->event_wait_q);
spin_lock_init(&info->irq_spinlock);
spin_lock_init(&info->netlock);
memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
info->idle_mode = HDLC_TXIDLE_FLAGS;
info->num_tx_dma_buffers = 1;
info->num_tx_holding_buffers = 0;
}
return info;
} /* end of mgsl_allocate_device()*/
static const struct tty_operations mgsl_ops = {
.open = mgsl_open,
.close = mgsl_close,
.write = mgsl_write,
.put_char = mgsl_put_char,
.flush_chars = mgsl_flush_chars,
.write_room = mgsl_write_room,
.chars_in_buffer = mgsl_chars_in_buffer,
.flush_buffer = mgsl_flush_buffer,
.ioctl = mgsl_ioctl,
.throttle = mgsl_throttle,
.unthrottle = mgsl_unthrottle,
.send_xchar = mgsl_send_xchar,
.break_ctl = mgsl_break,
.wait_until_sent = mgsl_wait_until_sent,
.read_proc = mgsl_read_proc,
.set_termios = mgsl_set_termios,
.stop = mgsl_stop,
.start = mgsl_start,
.hangup = mgsl_hangup,
.tiocmget = tiocmget,
.tiocmset = tiocmset,
};
/*
* perform tty device initialization
*/
static int mgsl_init_tty(void)
{
int rc;
serial_driver = alloc_tty_driver(128);
if (!serial_driver)
return -ENOMEM;
serial_driver->owner = THIS_MODULE;
serial_driver->driver_name = "synclink";
serial_driver->name = "ttySL";
serial_driver->major = ttymajor;
serial_driver->minor_start = 64;
serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
serial_driver->subtype = SERIAL_TYPE_NORMAL;
serial_driver->init_termios = tty_std_termios;
serial_driver->init_termios.c_cflag =
B9600 | CS8 | CREAD | HUPCL | CLOCAL;
serial_driver->init_termios.c_ispeed = 9600;
serial_driver->init_termios.c_ospeed = 9600;
serial_driver->flags = TTY_DRIVER_REAL_RAW;
tty_set_operations(serial_driver, &mgsl_ops);
if ((rc = tty_register_driver(serial_driver)) < 0) {
printk("%s(%d):Couldn't register serial driver\n",
__FILE__,__LINE__);
put_tty_driver(serial_driver);
serial_driver = NULL;
return rc;
}
printk("%s %s, tty major#%d\n",
driver_name, driver_version,
serial_driver->major);
return 0;
}
/* enumerate user specified ISA adapters
*/
static void mgsl_enum_isa_devices(void)
{
struct mgsl_struct *info;
int i;
/* Check for user specified ISA devices */
for (i=0 ;(i < MAX_ISA_DEVICES) && io[i] && irq[i]; i++){
if ( debug_level >= DEBUG_LEVEL_INFO )
printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
io[i], irq[i], dma[i] );
info = mgsl_allocate_device();
if ( !info ) {
/* error allocating device instance data */
if ( debug_level >= DEBUG_LEVEL_ERROR )
printk( "can't allocate device instance data.\n");
continue;
}
/* Copy user configuration info to device instance data */
info->io_base = (unsigned int)io[i];
info->irq_level = (unsigned int)irq[i];
info->irq_level = irq_canonicalize(info->irq_level);
info->dma_level = (unsigned int)dma[i];
info->bus_type = MGSL_BUS_TYPE_ISA;
info->io_addr_size = 16;
info->irq_flags = 0;
mgsl_add_device( info );
}
}
static void synclink_cleanup(void)
{
int rc;
struct mgsl_struct *info;
struct mgsl_struct *tmp;
printk("Unloading %s: %s\n", driver_name, driver_version);
if (serial_driver) {
if ((rc = tty_unregister_driver(serial_driver)))
printk("%s(%d) failed to unregister tty driver err=%d\n",
__FILE__,__LINE__,rc);
put_tty_driver(serial_driver);
}
info = mgsl_device_list;
while(info) {
#if SYNCLINK_GENERIC_HDLC
hdlcdev_exit(info);
#endif
mgsl_release_resources(info);
tmp = info;
info = info->next_device;
kfree(tmp);
}
if (pci_registered)
pci_unregister_driver(&synclink_pci_driver);
}
static int __init synclink_init(void)
{
int rc;
if (break_on_load) {
mgsl_get_text_ptr();
BREAKPOINT();
}
printk("%s %s\n", driver_name, driver_version);
mgsl_enum_isa_devices();
if ((rc = pci_register_driver(&synclink_pci_driver)) < 0)
printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
else
pci_registered = true;
if ((rc = mgsl_init_tty()) < 0)
goto error;
return 0;
error:
synclink_cleanup();
return rc;
}
static void __exit synclink_exit(void)
{
synclink_cleanup();
}
module_init(synclink_init);
module_exit(synclink_exit);
/*
* usc_RTCmd()
*
* Issue a USC Receive/Transmit command to the
* Channel Command/Address Register (CCAR).
*
* Notes:
*
* The command is encoded in the most significant 5 bits <15..11>
* of the CCAR value. Bits <10..7> of the CCAR must be preserved
* and Bits <6..0> must be written as zeros.
*
* Arguments:
*
* info pointer to device information structure
* Cmd command mask (use symbolic macros)
*
* Return Value:
*
* None
*/
static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd )
{
/* output command to CCAR in bits <15..11> */
/* preserve bits <10..7>, bits <6..0> must be zero */
outw( Cmd + info->loopback_bits, info->io_base + CCAR );
/* Read to flush write to CCAR */
if ( info->bus_type == MGSL_BUS_TYPE_PCI )
inw( info->io_base + CCAR );
} /* end of usc_RTCmd() */
/*
* usc_DmaCmd()
*
* Issue a DMA command to the DMA Command/Address Register (DCAR).
*
* Arguments:
*
* info pointer to device information structure
* Cmd DMA command mask (usc_DmaCmd_XX Macros)
*
* Return Value:
*
* None
*/
static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd )
{
/* write command mask to DCAR */
outw( Cmd + info->mbre_bit, info->io_base );
/* Read to flush write to DCAR */
if ( info->bus_type == MGSL_BUS_TYPE_PCI )
inw( info->io_base );
} /* end of usc_DmaCmd() */
/*
* usc_OutDmaReg()
*
* Write a 16-bit value to a USC DMA register
*
* Arguments:
*
* info pointer to device info structure
* RegAddr register address (number) for write
* RegValue 16-bit value to write to register
*
* Return Value:
*
* None
*
*/
static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
{
/* Note: The DCAR is located at the adapter base address */
/* Note: must preserve state of BIT8 in DCAR */
outw( RegAddr + info->mbre_bit, info->io_base );
outw( RegValue, info->io_base );
/* Read to flush write to DCAR */
if ( info->bus_type == MGSL_BUS_TYPE_PCI )
inw( info->io_base );
} /* end of usc_OutDmaReg() */
/*
* usc_InDmaReg()
*
* Read a 16-bit value from a DMA register
*
* Arguments:
*
* info pointer to device info structure
* RegAddr register address (number) to read from
*
* Return Value:
*
* The 16-bit value read from register
*
*/
static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr )
{
/* Note: The DCAR is located at the adapter base address */
/* Note: must preserve state of BIT8 in DCAR */
outw( RegAddr + info->mbre_bit, info->io_base );
return inw( info->io_base );
} /* end of usc_InDmaReg() */
/*
*
* usc_OutReg()
*
* Write a 16-bit value to a USC serial channel register
*
* Arguments:
*
* info pointer to device info structure
* RegAddr register address (number) to write to
* RegValue 16-bit value to write to register
*
* Return Value:
*
* None
*
*/
static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
{
outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
outw( RegValue, info->io_base + CCAR );
/* Read to flush write to CCAR */
if ( info->bus_type == MGSL_BUS_TYPE_PCI )
inw( info->io_base + CCAR );
} /* end of usc_OutReg() */
/*
* usc_InReg()
*
* Reads a 16-bit value from a USC serial channel register
*
* Arguments:
*
* info pointer to device extension
* RegAddr register address (number) to read from
*
* Return Value:
*
* 16-bit value read from register
*/
static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr )
{
outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
return inw( info->io_base + CCAR );
} /* end of usc_InReg() */
/* usc_set_sdlc_mode()
*
* Set up the adapter for SDLC DMA communications.
*
* Arguments: info pointer to device instance data
* Return Value: NONE
*/
static void usc_set_sdlc_mode( struct mgsl_struct *info )
{
u16 RegValue;
bool PreSL1660;
/*
* determine if the IUSC on the adapter is pre-SL1660. If
* not, take advantage of the UnderWait feature of more
* modern chips. If an underrun occurs and this bit is set,
* the transmitter will idle the programmed idle pattern
* until the driver has time to service the underrun. Otherwise,
* the dma controller may get the cycles previously requested
* and begin transmitting queued tx data.
*/
usc_OutReg(info,TMCR,0x1f);
RegValue=usc_InReg(info,TMDR);
PreSL1660 = (RegValue == IUSC_PRE_SL1660);
if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
{
/*
** Channel Mode Register (CMR)
**
** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
** <13> 0 0 = Transmit Disabled (initially)
** <12> 0 1 = Consecutive Idles share common 0
** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
** <3..0> 0110 Receiver Mode = HDLC/SDLC
**
** 1000 1110 0000 0110 = 0x8e06
*/
RegValue = 0x8e06;
/*--------------------------------------------------
* ignore user options for UnderRun Actions and
* preambles
*--------------------------------------------------*/
}
else
{
/* Channel mode Register (CMR)
*
* <15..14> 00 Tx Sub modes, Underrun Action
* <13> 0 1 = Send Preamble before opening flag
* <12> 0 1 = Consecutive Idles share common 0
* <11..8> 0110 Transmitter mode = HDLC/SDLC
* <7..4> 0000 Rx Sub modes, addr/ctrl field handling
* <3..0> 0110 Receiver mode = HDLC/SDLC
*
* 0000 0110 0000 0110 = 0x0606
*/
if (info->params.mode == MGSL_MODE_RAW) {
RegValue = 0x0001; /* Set Receive mode = external sync */
usc_OutReg( info, IOCR, /* Set IOCR DCD is RxSync Detect Input */
(unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12));
/*
* TxSubMode:
* CMR <15> 0 Don't send CRC on Tx Underrun
* CMR <14> x undefined
* CMR <13> 0 Send preamble before openning sync
* CMR <12> 0 Send 8-bit syncs, 1=send Syncs per TxLength
*
* TxMode:
* CMR <11-8) 0100 MonoSync
*
* 0x00 0100 xxxx xxxx 04xx
*/
RegValue |= 0x0400;
}
else {
RegValue = 0x0606;
if ( info->params.flags & HDLC_FLAG_UNDERRUN_ABORT15 )
RegValue |= BIT14;
else if ( info->params.flags & HDLC_FLAG_UNDERRUN_FLAG )
RegValue |= BIT15;
else if ( info->params.flags & HDLC_FLAG_UNDERRUN_CRC )
RegValue |= BIT15 + BIT14;
}
if ( info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE )
RegValue |= BIT13;
}
if ( info->params.mode == MGSL_MODE_HDLC &&
(info->params.flags & HDLC_FLAG_SHARE_ZERO) )
RegValue |= BIT12;
if ( info->params.addr_filter != 0xff )
{
/* set up receive address filtering */
usc_OutReg( info, RSR, info->params.addr_filter );
RegValue |= BIT4;
}
usc_OutReg( info, CMR, RegValue );
info->cmr_value = RegValue;
/* Receiver mode Register (RMR)
*
* <15..13> 000 encoding
* <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
* <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
* <9> 0 1 = Include Receive chars in CRC
* <8> 1 1 = Use Abort/PE bit as abort indicator
* <7..6> 00 Even parity
* <5> 0 parity disabled
* <4..2> 000 Receive Char Length = 8 bits
* <1..0> 00 Disable Receiver
*
* 0000 0101 0000 0000 = 0x0500
*/
RegValue = 0x0500;
switch ( info->params.encoding ) {
case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
}
if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
RegValue |= BIT9;
else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
RegValue |= ( BIT12 | BIT10 | BIT9 );
usc_OutReg( info, RMR, RegValue );
/* Set the Receive count Limit Register (RCLR) to 0xffff. */
/* When an opening flag of an SDLC frame is recognized the */
/* Receive Character count (RCC) is loaded with the value in */
/* RCLR. The RCC is decremented for each received byte. The */
/* value of RCC is stored after the closing flag of the frame */
/* allowing the frame size to be computed. */
usc_OutReg( info, RCLR, RCLRVALUE );
usc_RCmd( info, RCmd_SelectRicrdma_level );
/* Receive Interrupt Control Register (RICR)
*
* <15..8> ? RxFIFO DMA Request Level
* <7> 0 Exited Hunt IA (Interrupt Arm)
* <6> 0 Idle Received IA
* <5> 0 Break/Abort IA
* <4> 0 Rx Bound IA
* <3> 1 Queued status reflects oldest 2 bytes in FIFO
* <2> 0 Abort/PE IA
* <1> 1 Rx Overrun IA
* <0> 0 Select TC0 value for readback
*
* 0000 0000 0000 1000 = 0x000a
*/
/* Carry over the Exit Hunt and Idle Received bits */
/* in case they have been armed by usc_ArmEvents. */
RegValue = usc_InReg( info, RICR ) & 0xc0;
if ( info->bus_type == MGSL_BUS_TYPE_PCI )
usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
else
usc_OutReg( info, RICR, (u16)(0x140a | RegValue) );
/* Unlatch all Rx status bits and clear Rx status IRQ Pending */
usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
/* Transmit mode Register (TMR)
*
* <15..13> 000 encoding
* <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
* <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
* <9> 0 1 = Tx CRC Enabled
* <8> 0 1 = Append CRC to end of transmit frame
* <7..6> 00 Transmit parity Even
* <5> 0 Transmit parity Disabled
* <4..2> 000 Tx Char Length = 8 bits
* <1..0> 00 Disable Transmitter
*
* 0000 0100 0000 0000 = 0x0400
*/
RegValue = 0x0400;
switch ( info->params.encoding ) {
case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
}
if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
RegValue |= BIT9 + BIT8;
else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
usc_OutReg( info, TMR, RegValue );
usc_set_txidle( info );
usc_TCmd( info, TCmd_SelectTicrdma_level );
/* Transmit Interrupt Control Register (TICR)
*
* <15..8> ? Transmit FIFO DMA Level
* <7> 0 Present IA (Interrupt Arm)
* <6> 0 Idle Sent IA
* <5> 1 Abort Sent IA
* <4> 1 EOF/EOM Sent IA
* <3> 0 CRC Sent IA
* <2> 1 1 = Wait for SW Trigger to Start Frame
* <1> 1 Tx Underrun IA
* <0> 0 TC0 constant on read back
*
* 0000 0000 0011 0110 = 0x0036
*/
if ( info->bus_type == MGSL_BUS_TYPE_PCI )
usc_OutReg( info, TICR, 0x0736 );
else
usc_OutReg( info, TICR, 0x1436 );
usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
/*
** Transmit Command/Status Register (TCSR)
**
** <15..12> 0000 TCmd
** <11> 0/1 UnderWait
** <10..08> 000 TxIdle
** <7> x PreSent
** <6> x IdleSent
** <5> x AbortSent
** <4> x EOF/EOM Sent
** <3> x CRC Sent
** <2> x All Sent
** <1> x TxUnder
** <0> x TxEmpty
**
** 0000 0000 0000 0000 = 0x0000
*/
info->tcsr_value = 0;
if ( !PreSL1660 )
info->tcsr_value |= TCSR_UNDERWAIT;
usc_OutReg( info, TCSR, info->tcsr_value );
/* Clock mode Control Register (CMCR)
*
* <15..14> 00 counter 1 Source = Disabled
* <13..12> 00 counter 0 Source = Disabled
* <11..10> 11 BRG1 Input is TxC Pin
* <9..8> 11 BRG0 Input is TxC Pin
* <7..6> 01 DPLL Input is BRG1 Output
* <5..3> XXX TxCLK comes from Port 0
* <2..0> XXX RxCLK comes from Port 1
*
* 0000 1111 0111 0111 = 0x0f77
*/
RegValue = 0x0f40;
if ( info->params.flags & HDLC_FLAG_RXC_DPLL )
RegValue |= 0x0003; /* RxCLK from DPLL */
else if ( info->params.flags & HDLC_FLAG_RXC_BRG )
RegValue |= 0x0004; /* RxCLK from BRG0 */
else if ( info->params.flags & HDLC_FLAG_RXC_TXCPIN)
RegValue |= 0x0006; /* RxCLK from TXC Input */
else
RegValue |= 0x0007; /* RxCLK from Port1 */
if ( info->params.flags & HDLC_FLAG_TXC_DPLL )
RegValue |= 0x0018; /* TxCLK from DPLL */
else if ( info->params.flags & HDLC_FLAG_TXC_BRG )
RegValue |= 0x0020; /* TxCLK from BRG0 */
else if ( info->params.flags & HDLC_FLAG_TXC_RXCPIN)
RegValue |= 0x0038; /* RxCLK from TXC Input */
else
RegValue |= 0x0030; /* TxCLK from Port0 */
usc_OutReg( info, CMCR, RegValue );
/* Hardware Configuration Register (HCR)
*
* <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
* <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
* <12> 0 CVOK:0=report code violation in biphase
* <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
* <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
* <7..6> 00 reserved
* <5> 0 BRG1 mode:0=continuous,1=single cycle
* <4> X BRG1 Enable
* <3..2> 00 reserved
* <1> 0 BRG0 mode:0=continuous,1=single cycle
* <0> 0 BRG0 Enable
*/
RegValue = 0x0000;
if ( info->params.flags & (HDLC_FLAG_RXC_DPLL + HDLC_FLAG_TXC_DPLL) ) {
u32 XtalSpeed;
u32 DpllDivisor;
u16 Tc;
/* DPLL is enabled. Use BRG1 to provide continuous reference clock */
/* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
if ( info->bus_type == MGSL_BUS_TYPE_PCI )
XtalSpeed = 11059200;
else
XtalSpeed = 14745600;
if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
DpllDivisor = 16;
RegValue |= BIT10;
}
else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
DpllDivisor = 8;
RegValue |= BIT11;
}
else
DpllDivisor = 32;
/* Tc = (Xtal/Speed) - 1 */
/* If twice the remainder of (Xtal/Speed) is greater than Speed */
/* then rounding up gives a more precise time constant. Instead */
/* of rounding up and then subtracting 1 we just don't subtract */
/* the one in this case. */
/*--------------------------------------------------
* ejz: for DPLL mode, application should use the
* same clock speed as the partner system, even
* though clocking is derived from the input RxData.
* In case the user uses a 0 for the clock speed,
* default to 0xffffffff and don't try to divide by
* zero
*--------------------------------------------------*/
if ( info->params.clock_speed )
{
Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed);
if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2)
/ info->params.clock_speed) )
Tc--;
}
else
Tc = -1;
/* Write 16-bit Time Constant for BRG1 */
usc_OutReg( info, TC1R, Tc );
RegValue |= BIT4; /* enable BRG1 */
switch ( info->params.encoding ) {
case HDLC_ENCODING_NRZ:
case HDLC_ENCODING_NRZB:
case HDLC_ENCODING_NRZI_MARK:
case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
case HDLC_ENCODING_BIPHASE_MARK:
case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break;
case HDLC_ENCODING_BIPHASE_LEVEL:
case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 + BIT8; break;
}
}
usc_OutReg( info, HCR, RegValue );
/* Channel Control/status Register (CCSR)
*
* <15> X RCC FIFO Overflow status (RO)
* <14> X RCC FIFO Not Empty status (RO)
* <13> 0 1 = Clear RCC FIFO (WO)
* <12> X DPLL Sync (RW)
* <11> X DPLL 2 Missed Clocks status (RO)
* <10> X DPLL 1 Missed Clock status (RO)
* <9..8> 00 DPLL Resync on rising and falling edges (RW)
* <7> X SDLC Loop On status (RO)
* <6> X SDLC Loop Send status (RO)
* <5> 1 Bypass counters for TxClk and RxClk (RW)
* <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
* <1..0> 00 reserved
*
* 0000 0000 0010 0000 = 0x0020
*/
usc_OutReg( info, CCSR, 0x1020 );
if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) {
usc_OutReg( info, SICR,
(u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) );
}
/* enable Master Interrupt Enable bit (MIE) */
usc_EnableMasterIrqBit( info );
usc_ClearIrqPendingBits( info, RECEIVE_STATUS + RECEIVE_DATA +
TRANSMIT_STATUS + TRANSMIT_DATA + MISC);
/* arm RCC underflow interrupt */
usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3));
usc_EnableInterrupts(info, MISC);
info->mbre_bit = 0;
outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
info->mbre_bit = BIT8;
outw( BIT8, info->io_base ); /* set Master Bus Enable (DCAR) */
if (info->bus_type == MGSL_BUS_TYPE_ISA) {
/* Enable DMAEN (Port 7, Bit 14) */
/* This connects the DMA request signal to the ISA bus */
usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14));
}
/* DMA Control Register (DCR)
*
* <15..14> 10 Priority mode = Alternating Tx/Rx
* 01 Rx has priority
* 00 Tx has priority
*
* <13> 1 Enable Priority Preempt per DCR<15..14>
* (WARNING DCR<11..10> must be 00 when this is 1)
* 0 Choose activate channel per DCR<11..10>
*
* <12> 0 Little Endian for Array/List
* <11..10> 00 Both Channels can use each bus grant
* <9..6> 0000 reserved
* <5> 0 7 CLK - Minimum Bus Re-request Interval
* <4> 0 1 = drive D/C and S/D pins
* <3> 1 1 = Add one wait state to all DMA cycles.
* <2> 0 1 = Strobe /UAS on every transfer.
* <1..0> 11 Addr incrementing only affects LS24 bits
*
* 0110 0000 0000 1011 = 0x600b
*/
if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
/* PCI adapter does not need DMA wait state */
usc_OutDmaReg( info, DCR, 0xa00b );
}
else
usc_OutDmaReg( info, DCR, 0x800b );
/* Receive DMA mode Register (RDMR)
*
* <15..14> 11 DMA mode = Linked List Buffer mode
* <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
* <12> 1 Clear count of List Entry after fetching
* <11..10> 00 Address mode = Increment
* <9> 1 Terminate Buffer on RxBound
* <8> 0 Bus Width = 16bits
* <7..0> ? status Bits (write as 0s)
*
* 1111 0010 0000 0000 = 0xf200
*/
usc_OutDmaReg( info, RDMR, 0xf200 );
/* Transmit DMA mode Register (TDMR)
*
* <15..14> 11 DMA mode = Linked List Buffer mode
* <13> 1 TCBinA/L = fetch Tx Control Block from List entry
* <12> 1 Clear count of List Entry after fetching
* <11..10> 00 Address mode = Increment
* <9> 1 Terminate Buffer on end of frame
* <8> 0 Bus Width = 16bits
* <7..0> ? status Bits (Read Only so write as 0)
*
* 1111 0010 0000 0000 = 0xf200
*/
usc_OutDmaReg( info, TDMR, 0xf200 );
/* DMA Interrupt Control Register (DICR)
*
* <15> 1 DMA Interrupt Enable
* <14> 0 1 = Disable IEO from USC
* <13> 0 1 = Don't provide vector during IntAck
* <12> 1 1 = Include status in Vector
* <10..2> 0 reserved, Must be 0s
* <1> 0 1 = Rx DMA Interrupt Enabled
* <0> 0 1 = Tx DMA Interrupt Enabled
*
* 1001 0000 0000 0000 = 0x9000
*/
usc_OutDmaReg( info, DICR, 0x9000 );
usc_InDmaReg( info, RDMR ); /* clear pending receive DMA IRQ bits */
usc_InDmaReg( info, TDMR ); /* clear pending transmit DMA IRQ bits */
usc_OutDmaReg( info, CDIR, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
/* Channel Control Register (CCR)
*
* <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
* <13> 0 Trigger Tx on SW Command Disabled
* <12> 0 Flag Preamble Disabled
* <11..10> 00 Preamble Length
* <9..8> 00 Preamble Pattern
* <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
* <5> 0 Trigger Rx on SW Command Disabled
* <4..0> 0 reserved
*
* 1000 0000 1000 0000 = 0x8080
*/
RegValue = 0x8080;
switch ( info->params.preamble_length ) {
case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break;
case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break;
case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 + BIT10; break;
}
switch ( info->params.preamble ) {
case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 + BIT12; break;
case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break;
case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break;
case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 + BIT8; break;
}
usc_OutReg( info, CCR, RegValue );
/*
* Burst/Dwell Control Register
*
* <15..8> 0x20 Maximum number of transfers per bus grant
* <7..0> 0x00 Maximum number of clock cycles per bus grant
*/
if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
/* don't limit bus occupancy on PCI adapter */
usc_OutDmaReg( info, BDCR, 0x0000 );
}
else
usc_OutDmaReg( info, BDCR, 0x2000 );
usc_stop_transmitter(info);
usc_stop_receiver(info);
} /* end of usc_set_sdlc_mode() */
/* usc_enable_loopback()
*
* Set the 16C32 for internal loopback mode.
* The TxCLK and RxCLK signals are generated from the BRG0 and
* the TxD is looped back to the RxD internally.
*
* Arguments: info pointer to device instance data
* enable 1 = enable loopback, 0 = disable
* Return Value: None
*/
static void usc_enable_loopback(struct mgsl_struct *info, int enable)
{
if (enable) {
/* blank external TXD output */
usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7+BIT6));
/* Clock mode Control Register (CMCR)
*
* <15..14> 00 counter 1 Disabled
* <13..12> 00 counter 0 Disabled
* <11..10> 11 BRG1 Input is TxC Pin
* <9..8> 11 BRG0 Input is TxC Pin
* <7..6> 01 DPLL Input is BRG1 Output
* <5..3> 100 TxCLK comes from BRG0
* <2..0> 100 RxCLK comes from BRG0
*
* 0000 1111 0110 0100 = 0x0f64
*/
usc_OutReg( info, CMCR, 0x0f64 );
/* Write 16-bit Time Constant for BRG0 */
/* use clock speed if available, otherwise use 8 for diagnostics */
if (info->params.clock_speed) {
if (info->bus_type == MGSL_BUS_TYPE_PCI)
usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
else
usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1));
} else
usc_OutReg(info, TC0R, (u16)8);
/* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
mode = Continuous Set Bit 0 to enable BRG0. */
usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
/* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004));
/* set Internal Data loopback mode */
info->loopback_bits = 0x300;
outw( 0x0300, info->io_base + CCAR );
} else {
/* enable external TXD output */
usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7+BIT6));
/* clear Internal Data loopback mode */
info->loopback_bits = 0;
outw( 0,info->io_base + CCAR );
}
} /* end of usc_enable_loopback() */
/* usc_enable_aux_clock()
*
* Enabled the AUX clock output at the specified frequency.
*
* Arguments:
*
* info pointer to device extension
* data_rate data rate of clock in bits per second
* A data rate of 0 disables the AUX clock.
*
* Return Value: None
*/
static void usc_enable_aux_clock( struct mgsl_struct *info, u32 data_rate )
{
u32 XtalSpeed;
u16 Tc;
if ( data_rate ) {
if ( info->bus_type == MGSL_BUS_TYPE_PCI )
XtalSpeed = 11059200;
else
XtalSpeed = 14745600;
/* Tc = (Xtal/Speed) - 1 */
/* If twice the remainder of (Xtal/Speed) is greater than Speed */
/* then rounding up gives a more precise time constant. Instead */
/* of rounding up and then subtracting 1 we just don't subtract */
/* the one in this case. */
Tc = (u16)(XtalSpeed/data_rate);
if ( !(((XtalSpeed % data_rate) * 2) / data_rate) )
Tc--;
/* Write 16-bit Time Constant for BRG0 */
usc_OutReg( info, TC0R, Tc );
/*
* Hardware Configuration Register (HCR)
* Clear Bit 1, BRG0 mode = Continuous
* Set Bit 0 to enable BRG0.
*/
usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
/* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
} else {
/* data rate == 0 so turn off BRG0 */
usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
}
} /* end of usc_enable_aux_clock() */
/*
*
* usc_process_rxoverrun_sync()
*
* This function processes a receive overrun by resetting the
* receive DMA buffers and issuing a Purge Rx FIFO command
* to allow the receiver to continue receiving.
*
* Arguments:
*
* info pointer to device extension
*
* Return Value: None
*/
static void usc_process_rxoverrun_sync( struct mgsl_struct *info )
{
int start_index;
int end_index;
int frame_start_index;
bool start_of_frame_found = false;
bool end_of_frame_found = false;
bool reprogram_dma = false;
DMABUFFERENTRY *buffer_list = info->rx_buffer_list;
u32 phys_addr;
usc_DmaCmd( info, DmaCmd_PauseRxChannel );
usc_RCmd( info, RCmd_EnterHuntmode );
usc_RTCmd( info, RTCmd_PurgeRxFifo );
/* CurrentRxBuffer points to the 1st buffer of the next */
/* possibly available receive frame. */
frame_start_index = start_index = end_index = info->current_rx_buffer;
/* Search for an unfinished string of buffers. This means */
/* that a receive frame started (at least one buffer with */
/* count set to zero) but there is no terminiting buffer */
/* (status set to non-zero). */
while( !buffer_list[end_index].count )
{
/* Count field has been reset to zero by 16C32. */
/* This buffer is currently in use. */
if ( !start_of_frame_found )
{
start_of_frame_found = true;
frame_start_index = end_index;
end_of_frame_found = false;
}
if ( buffer_list[end_index].status )
{
/* Status field has been set by 16C32. */
/* This is the last buffer of a received frame. */
/* We want to leave the buffers for this frame intact. */
/* Move on to next possible frame. */
start_of_frame_found = false;
end_of_frame_found = true;
}
/* advance to next buffer entry in linked list */
end_index++;
if ( end_index == info->rx_buffer_count )
end_index = 0;
if ( start_index == end_index )
{
/* The entire list has been searched with all Counts == 0 and */
/* all Status == 0. The receive buffers are */
/* completely screwed, reset all receive buffers! */
mgsl_reset_rx_dma_buffers( info );
frame_start_index = 0;
start_of_frame_found = false;
reprogram_dma = true;
break;
}
}
if ( start_of_frame_found && !end_of_frame_found )
{
/* There is an unfinished string of receive DMA buffers */
/* as a result of the receiver overrun. */
/* Reset the buffers for the unfinished frame */
/* and reprogram the receive DMA controller to start */
/* at the 1st buffer of unfinished frame. */
start_index = frame_start_index;
do
{
*((unsigned long *)&(info->rx_buffer_list[start_index++].count)) = DMABUFFERSIZE;
/* Adjust index for wrap around. */
if ( start_index == info->rx_buffer_count )
start_index = 0;
} while( start_index != end_index );
reprogram_dma = true;
}
if ( reprogram_dma )
{
usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
usc_ClearIrqPendingBits(info, RECEIVE_DATA|RECEIVE_STATUS);
usc_UnlatchRxstatusBits(info, RECEIVE_DATA|RECEIVE_STATUS);
usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
/* This empties the receive FIFO and loads the RCC with RCLR */
usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
/* program 16C32 with physical address of 1st DMA buffer entry */
phys_addr = info->rx_buffer_list[frame_start_index].phys_entry;
usc_OutDmaReg( info, NRARL, (u16)phys_addr );
usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
usc_EnableInterrupts( info, RECEIVE_STATUS );
/* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
/* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
usc_DmaCmd( info, DmaCmd_InitRxChannel );
if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
usc_EnableReceiver(info,ENABLE_AUTO_DCD);
else
usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
}
else
{
/* This empties the receive FIFO and loads the RCC with RCLR */
usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
usc_RTCmd( info, RTCmd_PurgeRxFifo );
}
} /* end of usc_process_rxoverrun_sync() */
/* usc_stop_receiver()
*
* Disable USC receiver
*
* Arguments: info pointer to device instance data
* Return Value: None
*/
static void usc_stop_receiver( struct mgsl_struct *info )
{
if (debug_level >= DEBUG_LEVEL_ISR)
printk("%s(%d):usc_stop_receiver(%s)\n",
__FILE__,__LINE__, info->device_name );
/* Disable receive DMA channel. */
/* This also disables receive DMA channel interrupts */
usc_DmaCmd( info, DmaCmd_ResetRxChannel );
usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
usc_DisableInterrupts( info, RECEIVE_DATA + RECEIVE_STATUS );
usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
/* This empties the receive FIFO and loads the RCC with RCLR */
usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
usc_RTCmd( info, RTCmd_PurgeRxFifo );
info->rx_enabled = false;
info->rx_overflow = false;
info->rx_rcc_underrun = false;
} /* end of stop_receiver() */
/* usc_start_receiver()
*
* Enable the USC receiver
*
* Arguments: info pointer to device instance data
* Return Value: None
*/
static void usc_start_receiver( struct mgsl_struct *info )
{
u32 phys_addr;
if (debug_level >= DEBUG_LEVEL_ISR)
printk("%s(%d):usc_start_receiver(%s)\n",
__FILE__,__LINE__, info->device_name );
mgsl_reset_rx_dma_buffers( info );
usc_stop_receiver( info );
usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
usc_RTCmd( info, RTCmd_PurgeRxFifo );
if ( info->params.mode == MGSL_MODE_HDLC ||
info->params.mode == MGSL_MODE_RAW ) {
/* DMA mode Transfers */
/* Program the DMA controller. */
/* Enable the DMA controller end of buffer interrupt. */
/* program 16C32 with physical address of 1st DMA buffer entry */
phys_addr = info->rx_buffer_list[0].phys_entry;
usc_OutDmaReg( info, NRARL, (u16)phys_addr );
usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
usc_EnableInterrupts( info, RECEIVE_STATUS );
/* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
/* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
usc_DmaCmd( info, DmaCmd_InitRxChannel );
if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
usc_EnableReceiver(info,ENABLE_AUTO_DCD);
else
usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
} else {
usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
usc_EnableInterrupts(info, RECEIVE_DATA);
usc_RTCmd( info, RTCmd_PurgeRxFifo );
usc_RCmd( info, RCmd_EnterHuntmode );
usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
}
usc_OutReg( info, CCSR, 0x1020 );
info->rx_enabled = true;
} /* end of usc_start_receiver() */
/* usc_start_transmitter()
*
* Enable the USC transmitter and send a transmit frame if
* one is loaded in the DMA buffers.
*
* Arguments: info pointer to device instance data
* Return Value: None
*/
static void usc_start_transmitter( struct mgsl_struct *info )
{
u32 phys_addr;
unsigned int FrameSize;
if (debug_level >= DEBUG_LEVEL_ISR)
printk("%s(%d):usc_start_transmitter(%s)\n",
__FILE__,__LINE__, info->device_name );
if ( info->xmit_cnt ) {
/* If auto RTS enabled and RTS is inactive, then assert */
/* RTS and set a flag indicating that the driver should */
/* negate RTS when the transmission completes. */
info->drop_rts_on_tx_done = false;
if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
usc_get_serial_signals( info );
if ( !(info->serial_signals & SerialSignal_RTS) ) {
info->serial_signals |= SerialSignal_RTS;
usc_set_serial_signals( info );
info->drop_rts_on_tx_done = true;
}
}
if ( info->params.mode == MGSL_MODE_ASYNC ) {
if ( !info->tx_active ) {
usc_UnlatchTxstatusBits(info, TXSTATUS_ALL);
usc_ClearIrqPendingBits(info, TRANSMIT_STATUS + TRANSMIT_DATA);
usc_EnableInterrupts(info, TRANSMIT_DATA);
usc_load_txfifo(info);
}
} else {
/* Disable transmit DMA controller while programming. */
usc_DmaCmd( info, DmaCmd_ResetTxChannel );
/* Transmit DMA buffer is loaded, so program USC */
/* to send the frame contained in the buffers. */
FrameSize = info->tx_buffer_list[info->start_tx_dma_buffer].rcc;
/* if operating in Raw sync mode, reset the rcc component
* of the tx dma buffer entry, otherwise, the serial controller
* will send a closing sync char after this count.
*/
if ( info->params.mode == MGSL_MODE_RAW )
info->tx_buffer_list[info->start_tx_dma_buffer].rcc = 0;
/* Program the Transmit Character Length Register (TCLR) */
/* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
usc_OutReg( info, TCLR, (u16)FrameSize );
usc_RTCmd( info, RTCmd_PurgeTxFifo );
/* Program the address of the 1st DMA Buffer Entry in linked list */
phys_addr = info->tx_buffer_list[info->start_tx_dma_buffer].phys_entry;
usc_OutDmaReg( info, NTARL, (u16)phys_addr );
usc_OutDmaReg( info, NTARU, (u16)(phys_addr >> 16) );
usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
usc_EnableInterrupts( info, TRANSMIT_STATUS );
if ( info->params.mode == MGSL_MODE_RAW &&
info->num_tx_dma_buffers > 1 ) {
/* When running external sync mode, attempt to 'stream' transmit */
/* by filling tx dma buffers as they become available. To do this */
/* we need to enable Tx DMA EOB Status interrupts : */
/* */
/* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
/* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
usc_OutDmaReg( info, TDIAR, BIT2|BIT3 );
usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) );
}
/* Initialize Transmit DMA Channel */
usc_DmaCmd( info, DmaCmd_InitTxChannel );
usc_TCmd( info, TCmd_SendFrame );
mod_timer(&info->tx_timer, jiffies +
msecs_to_jiffies(5000));
}
info->tx_active = true;
}
if ( !info->tx_enabled ) {
info->tx_enabled = true;
if ( info->params.flags & HDLC_FLAG_AUTO_CTS )
usc_EnableTransmitter(info,ENABLE_AUTO_CTS);
else
usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
}
} /* end of usc_start_transmitter() */
/* usc_stop_transmitter()
*
* Stops the transmitter and DMA
*
* Arguments: info pointer to device isntance data
* Return Value: None
*/
static void usc_stop_transmitter( struct mgsl_struct *info )
{
if (debug_level >= DEBUG_LEVEL_ISR)
printk("%s(%d):usc_stop_transmitter(%s)\n",
__FILE__,__LINE__, info->device_name );
del_timer(&info->tx_timer);
usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA );
usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA );
usc_EnableTransmitter(info,DISABLE_UNCONDITIONAL);
usc_DmaCmd( info, DmaCmd_ResetTxChannel );
usc_RTCmd( info, RTCmd_PurgeTxFifo );
info->tx_enabled = false;
info->tx_active = false;
} /* end of usc_stop_transmitter() */
/* usc_load_txfifo()
*
* Fill the transmit FIFO until the FIFO is full or
* there is no more data to load.
*
* Arguments: info pointer to device extension (instance data)
* Return Value: None
*/
static void usc_load_txfifo( struct mgsl_struct *info )
{
int Fifocount;
u8 TwoBytes[2];
if ( !info->xmit_cnt && !info->x_char )
return;
/* Select transmit FIFO status readback in TICR */
usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
/* load the Transmit FIFO until FIFOs full or all data sent */
while( (Fifocount = usc_InReg(info, TICR) >> 8) && info->xmit_cnt ) {
/* there is more space in the transmit FIFO and */
/* there is more data in transmit buffer */
if ( (info->xmit_cnt > 1) && (Fifocount > 1) && !info->x_char ) {
/* write a 16-bit word from transmit buffer to 16C32 */
TwoBytes[0] = info->xmit_buf[info->xmit_tail++];
info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
TwoBytes[1] = info->xmit_buf[info->xmit_tail++];
info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
outw( *((u16 *)TwoBytes), info->io_base + DATAREG);
info->xmit_cnt -= 2;
info->icount.tx += 2;
} else {
/* only 1 byte left to transmit or 1 FIFO slot left */
outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),
info->io_base + CCAR );
if (info->x_char) {
/* transmit pending high priority char */
outw( info->x_char,info->io_base + CCAR );
info->x_char = 0;
} else {
outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );
info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
info->xmit_cnt--;
}
info->icount.tx++;
}
}
} /* end of usc_load_txfifo() */
/* usc_reset()
*
* Reset the adapter to a known state and prepare it for further use.
*
* Arguments: info pointer to device instance data
* Return Value: None
*/
static void usc_reset( struct mgsl_struct *info )
{
if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
int i;
u32 readval;
/* Set BIT30 of Misc Control Register */
/* (Local Control Register 0x50) to force reset of USC. */
volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28);
info->misc_ctrl_value |= BIT30;
*MiscCtrl = info->misc_ctrl_value;
/*
* Force at least 170ns delay before clearing
* reset bit. Each read from LCR takes at least
* 30ns so 10 times for 300ns to be safe.
*/
for(i=0;i<10;i++)
readval = *MiscCtrl;
info->misc_ctrl_value &= ~BIT30;
*MiscCtrl = info->misc_ctrl_value;
*LCR0BRDR = BUS_DESCRIPTOR(
1, // Write Strobe Hold (0-3)
2, // Write Strobe Delay (0-3)
2, // Read Strobe Delay (0-3)
0, // NWDD (Write data-data) (0-3)
4, // NWAD (Write Addr-data) (0-31)
0, // NXDA (Read/Write Data-Addr) (0-3)
0, // NRDD (Read Data-Data) (0-3)
5 // NRAD (Read Addr-Data) (0-31)
);
} else {
/* do HW reset */
outb( 0,info->io_base + 8 );
}
info->mbre_bit = 0;
info->loopback_bits = 0;
info->usc_idle_mode = 0;
/*
* Program the Bus Configuration Register (BCR)
*
* <15> 0 Don't use separate address
* <14..6> 0 reserved
* <5..4> 00 IAckmode = Default, don't care
* <3> 1 Bus Request Totem Pole output
* <2> 1 Use 16 Bit data bus
* <1> 0 IRQ Totem Pole output
* <0> 0 Don't Shift Right Addr
*
* 0000 0000 0000 1100 = 0x000c
*
* By writing to io_base + SDPIN the Wait/Ack pin is
* programmed to work as a Wait pin.
*/
outw( 0x000c,info->io_base + SDPIN );
outw( 0,info->io_base );
outw( 0,info->io_base + CCAR );
/* select little endian byte ordering */
usc_RTCmd( info, RTCmd_SelectLittleEndian );
/* Port Control Register (PCR)
*
* <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
* <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
* <11..10> 00 Port 5 is Input (No Connect, Don't Care)
* <9..8> 00 Port 4 is Input (No Connect, Don't Care)
* <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
* <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
* <3..2> 01 Port 1 is Input (Dedicated RxC)
* <1..0> 01 Port 0 is Input (Dedicated TxC)
*
* 1111 0000 1111 0101 = 0xf0f5
*/
usc_OutReg( info, PCR, 0xf0f5 );
/*
* Input/Output Control Register
*
* <15..14> 00 CTS is active low input
* <13..12> 00 DCD is active low input
* <11..10> 00 TxREQ pin is input (DSR)
* <9..8> 00 RxREQ pin is input (RI)
* <7..6> 00 TxD is output (Transmit Data)
* <5..3> 000 TxC Pin in Input (14.7456MHz Clock)
* <2..0> 100 RxC is Output (drive with BRG0)
*
* 0000 0000 0000 0100 = 0x0004
*/
usc_OutReg( info, IOCR, 0x0004 );
} /* end of usc_reset() */
/* usc_set_async_mode()
*
* Program adapter for asynchronous communications.
*
* Arguments: info pointer to device instance data
* Return Value: None
*/
static void usc_set_async_mode( struct mgsl_struct *info )
{
u16 RegValue;
/* disable interrupts while programming USC */
usc_DisableMasterIrqBit( info );
outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
usc_loopback_frame( info );
/* Channel mode Register (CMR)
*
* <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit
* <13..12> 00 00 = 16X Clock
* <11..8> 0000 Transmitter mode = Asynchronous
* <7..6> 00 reserved?
* <5..4> 00 Rx Sub modes, 00 = 16X Clock
* <3..0> 0000 Receiver mode = Asynchronous
*
* 0000 0000 0000 0000 = 0x0
*/
RegValue = 0;
if ( info->params.stop_bits != 1 )
RegValue |= BIT14;
usc_OutReg( info, CMR, RegValue );
/* Receiver mode Register (RMR)
*
* <15..13> 000 encoding = None
* <12..08> 00000 reserved (Sync Only)
* <7..6> 00 Even parity
* <5> 0 parity disabled
* <4..2> 000 Receive Char Length = 8 bits
* <1..0> 00 Disable Receiver
*
* 0000 0000 0000 0000 = 0x0
*/
RegValue = 0;
if ( info->params.data_bits != 8 )
RegValue |= BIT4+BIT3+BIT2;
if ( info->params.parity != ASYNC_PARITY_NONE ) {
RegValue |= BIT5;
if ( info->params.parity != ASYNC_PARITY_ODD )
RegValue |= BIT6;
}
usc_OutReg( info, RMR, RegValue );
/* Set IRQ trigger level */
usc_RCmd( info, RCmd_SelectRicrIntLevel );
/* Receive Interrupt Control Register (RICR)
*
* <15..8> ? RxFIFO IRQ Request Level
*
* Note: For async mode the receive FIFO level must be set
* to 0 to avoid the situation where the FIFO contains fewer bytes
* than the trigger level and no more data is expected.
*
* <7> 0 Exited Hunt IA (Interrupt Arm)
* <6> 0 Idle Received IA
* <5> 0 Break/Abort IA
* <4> 0 Rx Bound IA
* <3> 0 Queued status reflects oldest byte in FIFO
* <2> 0 Abort/PE IA
* <1> 0 Rx Overrun IA
* <0> 0 Select TC0 value for readback
*
* 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
*/
usc_OutReg( info, RICR, 0x0000 );
usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
/* Transmit mode Register (TMR)
*
* <15..13> 000 encoding = None
* <12..08> 00000 reserved (Sync Only)
* <7..6> 00 Transmit parity Even
* <5> 0 Transmit parity Disabled
* <4..2> 000 Tx Char Length = 8 bits
* <1..0> 00 Disable Transmitter
*
* 0000 0000 0000 0000 = 0x0
*/
RegValue = 0;
if ( info->params.data_bits != 8 )
RegValue |= BIT4+BIT3+BIT2;
if ( info->params.parity != ASYNC_PARITY_NONE ) {
RegValue |= BIT5;
if ( info->params.parity != ASYNC_PARITY_ODD )
RegValue |= BIT6;
}
usc_OutReg( info, TMR, RegValue );
usc_set_txidle( info );
/* Set IRQ trigger level */
usc_TCmd( info, TCmd_SelectTicrIntLevel );
/* Transmit Interrupt Control Register (TICR)
*
* <15..8> ? Transmit FIFO IRQ Level
* <7> 0 Present IA (Interrupt Arm)
* <6> 1 Idle Sent IA
* <5> 0 Abort Sent IA
* <4> 0 EOF/EOM Sent IA
* <3> 0 CRC Sent IA
* <2> 0 1 = Wait for SW Trigger to Start Frame
* <1> 0 Tx Underrun IA
* <0> 0 TC0 constant on read back
*
* 0000 0000 0100 0000 = 0x0040
*/
usc_OutReg( info, TICR, 0x1f40 );
usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
usc_enable_async_clock( info, info->params.data_rate );
/* Channel Control/status Register (CCSR)
*
* <15> X RCC FIFO Overflow status (RO)
* <14> X RCC FIFO Not Empty status (RO)
* <13> 0 1 = Clear RCC FIFO (WO)
* <12> X DPLL in Sync status (RO)
* <11> X DPLL 2 Missed Clocks status (RO)
* <10> X DPLL 1 Missed Clock status (RO)
* <9..8> 00 DPLL Resync on rising and falling edges (RW)
* <7> X SDLC Loop On status (RO)
* <6> X SDLC Loop Send status (RO)
* <5> 1 Bypass counters for TxClk and RxClk (RW)
* <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
* <1..0> 00 reserved
*
* 0000 0000 0010 0000 = 0x0020
*/
usc_OutReg( info, CCSR, 0x0020 );
usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA +
RECEIVE_DATA + RECEIVE_STATUS );
usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA +
RECEIVE_DATA + RECEIVE_STATUS );
usc_EnableMasterIrqBit( info );
if (info->bus_type == MGSL_BUS_TYPE_ISA) {
/* Enable INTEN (Port 6, Bit12) */
/* This connects the IRQ request signal to the ISA bus */
usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
}
if (info->params.loopback) {
info->loopback_bits = 0x300;
outw(0x0300, info->io_base + CCAR);
}
} /* end of usc_set_async_mode() */
/* usc_loopback_frame()
*
* Loop back a small (2 byte) dummy SDLC frame.
* Interrupts and DMA are NOT used. The purpose of this is to
* clear any 'stale' status info left over from running in async mode.
*
* The 16C32 shows the strange behaviour of marking the 1st
* received SDLC frame with a CRC error even when there is no
* CRC error. To get around this a small dummy from of 2 bytes
* is looped back when switching from async to sync mode.
*
* Arguments: info pointer to device instance data
* Return Value: None
*/
static void usc_loopback_frame( struct mgsl_struct *info )
{
int i;
unsigned long oldmode = info->params.mode;
info->params.mode = MGSL_MODE_HDLC;
usc_DisableMasterIrqBit( info );
usc_set_sdlc_mode( info );
usc_enable_loopback( info, 1 );
/* Write 16-bit Time Constant for BRG0 */
usc_OutReg( info, TC0R, 0 );
/* Channel Control Register (CCR)
*
* <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
* <13> 0 Trigger Tx on SW Command Disabled
* <12> 0 Flag Preamble Disabled
* <11..10> 00 Preamble Length = 8-Bits
* <9..8> 01 Preamble Pattern = flags
* <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs)
* <5> 0 Trigger Rx on SW Command Disabled
* <4..0> 0 reserved
*
* 0000 0001 0000 0000 = 0x0100
*/
usc_OutReg( info, CCR, 0x0100 );
/* SETUP RECEIVER */
usc_RTCmd( info, RTCmd_PurgeRxFifo );
usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
/* SETUP TRANSMITTER */
/* Program the Transmit Character Length Register (TCLR) */
/* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
usc_OutReg( info, TCLR, 2 );
usc_RTCmd( info, RTCmd_PurgeTxFifo );
/* unlatch Tx status bits, and start transmit channel. */
usc_UnlatchTxstatusBits(info,TXSTATUS_ALL);
outw(0,info->io_base + DATAREG);
/* ENABLE TRANSMITTER */
usc_TCmd( info, TCmd_SendFrame );
usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
/* WAIT FOR RECEIVE COMPLETE */
for (i=0 ; i<1000 ; i++)
if (usc_InReg( info, RCSR ) & (BIT8 + BIT4 + BIT3 + BIT1))
break;
/* clear Internal Data loopback mode */
usc_enable_loopback(info, 0);
usc_EnableMasterIrqBit(info);
info->params.mode = oldmode;
} /* end of usc_loopback_frame() */
/* usc_set_sync_mode() Programs the USC for SDLC communications.
*
* Arguments: info pointer to adapter info structure
* Return Value: None
*/
static void usc_set_sync_mode( struct mgsl_struct *info )
{
usc_loopback_frame( info );
usc_set_sdlc_mode( info );
if (info->bus_type == MGSL_BUS_TYPE_ISA) {
/* Enable INTEN (Port 6, Bit12) */
/* This connects the IRQ request signal to the ISA bus */
usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
}
usc_enable_aux_clock(info, info->params.clock_speed);
if (info->params.loopback)
usc_enable_loopback(info,1);
} /* end of mgsl_set_sync_mode() */
/* usc_set_txidle() Set the HDLC idle mode for the transmitter.
*
* Arguments: info pointer to device instance data
* Return Value: None
*/
static void usc_set_txidle( struct mgsl_struct *info )
{
u16 usc_idle_mode = IDLEMODE_FLAGS;
/* Map API idle mode to USC register bits */
switch( info->idle_mode ){
case HDLC_TXIDLE_FLAGS: usc_idle_mode = IDLEMODE_FLAGS; break;
case HDLC_TXIDLE_ALT_ZEROS_ONES: usc_idle_mode = IDLEMODE_ALT_ONE_ZERO; break;
case HDLC_TXIDLE_ZEROS: usc_idle_mode = IDLEMODE_ZERO; break;
case HDLC_TXIDLE_ONES: usc_idle_mode = IDLEMODE_ONE; break;
case HDLC_TXIDLE_ALT_MARK_SPACE: usc_idle_mode = IDLEMODE_ALT_MARK_SPACE; break;
case HDLC_TXIDLE_SPACE: usc_idle_mode = IDLEMODE_SPACE; break;
case HDLC_TXIDLE_MARK: usc_idle_mode = IDLEMODE_MARK; break;
}
info->usc_idle_mode = usc_idle_mode;
//usc_OutReg(info, TCSR, usc_idle_mode);
info->tcsr_value &= ~IDLEMODE_MASK; /* clear idle mode bits */
info->tcsr_value += usc_idle_mode;
usc_OutReg(info, TCSR, info->tcsr_value);
/*
* if SyncLink WAN adapter is running in external sync mode, the
* transmitter has been set to Monosync in order to try to mimic
* a true raw outbound bit stream. Monosync still sends an open/close
* sync char at the start/end of a frame. Try to match those sync
* patterns to the idle mode set here
*/
if ( info->params.mode == MGSL_MODE_RAW ) {
unsigned char syncpat = 0;
switch( info->idle_mode ) {
case HDLC_TXIDLE_FLAGS:
syncpat = 0x7e;
break;
case HDLC_TXIDLE_ALT_ZEROS_ONES:
syncpat = 0x55;
break;
case HDLC_TXIDLE_ZEROS:
case HDLC_TXIDLE_SPACE:
syncpat = 0x00;
break;
case HDLC_TXIDLE_ONES:
case HDLC_TXIDLE_MARK:
syncpat = 0xff;
break;
case HDLC_TXIDLE_ALT_MARK_SPACE:
syncpat = 0xaa;
break;
}
usc_SetTransmitSyncChars(info,syncpat,syncpat);
}
} /* end of usc_set_txidle() */
/* usc_get_serial_signals()
*
* Query the adapter for the state of the V24 status (input) signals.
*
* Arguments: info pointer to device instance data
* Return Value: None
*/
static void usc_get_serial_signals( struct mgsl_struct *info )
{
u16 status;
/* clear all serial signals except DTR and RTS */
info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
/* Read the Misc Interrupt status Register (MISR) to get */
/* the V24 status signals. */
status = usc_InReg( info, MISR );
/* set serial signal bits to reflect MISR */
if ( status & MISCSTATUS_CTS )
info->serial_signals |= SerialSignal_CTS;
if ( status & MISCSTATUS_DCD )
info->serial_signals |= SerialSignal_DCD;
if ( status & MISCSTATUS_RI )
info->serial_signals |= SerialSignal_RI;
if ( status & MISCSTATUS_DSR )
info->serial_signals |= SerialSignal_DSR;
} /* end of usc_get_serial_signals() */
/* usc_set_serial_signals()
*
* Set the state of DTR and RTS based on contents of
* serial_signals member of device extension.
*
* Arguments: info pointer to device instance data
* Return Value: None
*/
static void usc_set_serial_signals( struct mgsl_struct *info )
{
u16 Control;
unsigned char V24Out = info->serial_signals;
/* get the current value of the Port Control Register (PCR) */
Control = usc_InReg( info, PCR );
if ( V24Out & SerialSignal_RTS )
Control &= ~(BIT6);
else
Control |= BIT6;
if ( V24Out & SerialSignal_DTR )
Control &= ~(BIT4);
else
Control |= BIT4;
usc_OutReg( info, PCR, Control );
} /* end of usc_set_serial_signals() */
/* usc_enable_async_clock()
*
* Enable the async clock at the specified frequency.
*
* Arguments: info pointer to device instance data
* data_rate data rate of clock in bps
* 0 disables the AUX clock.
* Return Value: None
*/
static void usc_enable_async_clock( struct mgsl_struct *info, u32 data_rate )
{
if ( data_rate ) {
/*
* Clock mode Control Register (CMCR)
*
* <15..14> 00 counter 1 Disabled
* <13..12> 00 counter 0 Disabled
* <11..10> 11 BRG1 Input is TxC Pin
* <9..8> 11 BRG0 Input is TxC Pin
* <7..6> 01 DPLL Input is BRG1 Output
* <5..3> 100 TxCLK comes from BRG0
* <2..0> 100 RxCLK comes from BRG0
*
* 0000 1111 0110 0100 = 0x0f64
*/
usc_OutReg( info, CMCR, 0x0f64 );
/*
* Write 16-bit Time Constant for BRG0
* Time Constant = (ClkSpeed / data_rate) - 1
* ClkSpeed = 921600 (ISA), 691200 (PCI)
*/
if ( info->bus_type == MGSL_BUS_TYPE_PCI )
usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) );
else
usc_OutReg( info, TC0R, (u16)((921600/data_rate) - 1) );
/*
* Hardware Configuration Register (HCR)
* Clear Bit 1, BRG0 mode = Continuous
* Set Bit 0 to enable BRG0.
*/
usc_OutReg( info, HCR,
(u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
/* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
usc_OutReg( info, IOCR,
(u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
} else {
/* data rate == 0 so turn off BRG0 */
usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
}
} /* end of usc_enable_async_clock() */
/*
* Buffer Structures:
*
* Normal memory access uses virtual addresses that can make discontiguous
* physical memory pages appear to be contiguous in the virtual address
* space (the processors memory mapping handles the conversions).
*
* DMA transfers require physically contiguous memory. This is because
* the DMA system controller and DMA bus masters deal with memory using
* only physical addresses.
*
* This causes a problem under Windows NT when large DMA buffers are
* needed. Fragmentation of the nonpaged pool prevents allocations of
* physically contiguous buffers larger than the PAGE_SIZE.
*
* However the 16C32 supports Bus Master Scatter/Gather DMA which
* allows DMA transfers to physically discontiguous buffers. Information
* about each data transfer buffer is contained in a memory structure
* called a 'buffer entry'. A list of buffer entries is maintained
* to track and control the use of the data transfer buffers.
*
* To support this strategy we will allocate sufficient PAGE_SIZE
* contiguous memory buffers to allow for the total required buffer
* space.
*
* The 16C32 accesses the list of buffer entries using Bus Master
* DMA. Control information is read from the buffer entries by the
* 16C32 to control data transfers. status information is written to
* the buffer entries by the 16C32 to indicate the status of completed
* transfers.
*
* The CPU writes control information to the buffer entries to control
* the 16C32 and reads status information from the buffer entries to
* determine information about received and transmitted frames.
*
* Because the CPU and 16C32 (adapter) both need simultaneous access
* to the buffer entries, the buffer entry memory is allocated with
* HalAllocateCommonBuffer(). This restricts the size of the buffer
* entry list to PAGE_SIZE.
*
* The actual data buffers on the other hand will only be accessed
* by the CPU or the adapter but not by both simultaneously. This allows
* Scatter/Gather packet based DMA procedures for using physically
* discontiguous pages.
*/
/*
* mgsl_reset_tx_dma_buffers()
*
* Set the count for all transmit buffers to 0 to indicate the
* buffer is available for use and set the current buffer to the
* first buffer. This effectively makes all buffers free and
* discards any data in buffers.
*
* Arguments: info pointer to device instance data
* Return Value: None
*/
static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info )
{
unsigned int i;
for ( i = 0; i < info->tx_buffer_count; i++ ) {
*((unsigned long *)&(info->tx_buffer_list[i].count)) = 0;
}
info->current_tx_buffer = 0;
info->start_tx_dma_buffer = 0;
info->tx_dma_buffers_used = 0;
info->get_tx_holding_index = 0;
info->put_tx_holding_index = 0;
info->tx_holding_count = 0;
} /* end of mgsl_reset_tx_dma_buffers() */
/*
* num_free_tx_dma_buffers()
*
* returns the number of free tx dma buffers available
*
* Arguments: info pointer to device instance data
* Return Value: number of free tx dma buffers
*/
static int num_free_tx_dma_buffers(struct mgsl_struct *info)
{
return info->tx_buffer_count - info->tx_dma_buffers_used;
}
/*
* mgsl_reset_rx_dma_buffers()
*
* Set the count for all receive buffers to DMABUFFERSIZE
* and set the current buffer to the first buffer. This effectively
* makes all buffers free and discards any data in buffers.
*
* Arguments: info pointer to device instance data
* Return Value: None
*/
static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info )
{
unsigned int i;
for ( i = 0; i < info->rx_buffer_count; i++ ) {
*((unsigned long *)&(info->rx_buffer_list[i].count)) = DMABUFFERSIZE;
// info->rx_buffer_list[i].count = DMABUFFERSIZE;
// info->rx_buffer_list[i].status = 0;
}
info->current_rx_buffer = 0;
} /* end of mgsl_reset_rx_dma_buffers() */
/*
* mgsl_free_rx_frame_buffers()
*
* Free the receive buffers used by a received SDLC
* frame such that the buffers can be reused.
*
* Arguments:
*
* info pointer to device instance data
* StartIndex index of 1st receive buffer of frame
* EndIndex index of last receive buffer of frame
*
* Return Value: None
*/
static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex )
{
bool Done = false;
DMABUFFERENTRY *pBufEntry;
unsigned int Index;
/* Starting with 1st buffer entry of the frame clear the status */
/* field and set the count field to DMA Buffer Size. */
Index = StartIndex;
while( !Done ) {
pBufEntry = &(info->rx_buffer_list[Index]);
if ( Index == EndIndex ) {
/* This is the last buffer of the frame! */
Done = true;
}
/* reset current buffer for reuse */
// pBufEntry->status = 0;
// pBufEntry->count = DMABUFFERSIZE;
*((unsigned long *)&(pBufEntry->count)) = DMABUFFERSIZE;
/* advance to next buffer entry in linked list */
Index++;
if ( Index == info->rx_buffer_count )
Index = 0;
}
/* set current buffer to next buffer after last buffer of frame */
info->current_rx_buffer = Index;
} /* end of free_rx_frame_buffers() */
/* mgsl_get_rx_frame()
*
* This function attempts to return a received SDLC frame from the
* receive DMA buffers. Only frames received without errors are returned.
*
* Arguments: info pointer to device extension
* Return Value: true if frame returned, otherwise false
*/
static bool mgsl_get_rx_frame(struct mgsl_struct *info)
{
unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
unsigned short status;
DMABUFFERENTRY *pBufEntry;
unsigned int framesize = 0;
bool ReturnCode = false;
unsigned long flags;
struct tty_struct *tty = info->port.tty;
bool return_frame = false;
/*
* current_rx_buffer points to the 1st buffer of the next available
* receive frame. To find the last buffer of the frame look for
* a non-zero status field in the buffer entries. (The status
* field is set by the 16C32 after completing a receive frame.
*/
StartIndex = EndIndex = info->current_rx_buffer;
while( !info->rx_buffer_list[EndIndex].status ) {
/*
* If the count field of the buffer entry is non-zero then
* this buffer has not been used. (The 16C32 clears the count
* field when it starts using the buffer.) If an unused buffer
* is encountered then there are no frames available.
*/
if ( info->rx_buffer_list[EndIndex].count )
goto Cleanup;
/* advance to next buffer entry in linked list */
EndIndex++;
if ( EndIndex == info->rx_buffer_count )
EndIndex = 0;
/* if entire list searched then no frame available */
if ( EndIndex == StartIndex ) {
/* If this occurs then something bad happened,
* all buffers have been 'used' but none mark
* the end of a frame. Reset buffers and receiver.
*/
if ( info->rx_enabled ){
spin_lock_irqsave(&info->irq_spinlock,flags);
usc_start_receiver(info);
spin_unlock_irqrestore(&info->irq_spinlock,flags);
}
goto Cleanup;
}
}
/* check status of receive frame */
status = info->rx_buffer_list[EndIndex].status;
if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
if ( status & RXSTATUS_SHORT_FRAME )
info->icount.rxshort++;
else if ( status & RXSTATUS_ABORT )
info->icount.rxabort++;
else if ( status & RXSTATUS_OVERRUN )
info->icount.rxover++;
else {
info->icount.rxcrc++;
if ( info->params.crc_type & HDLC_CRC_RETURN_EX )
return_frame = true;
}
framesize = 0;
#if SYNCLINK_GENERIC_HDLC
{
info->netdev->stats.rx_errors++;
info->netdev->stats.rx_frame_errors++;
}
#endif
} else
return_frame = true;
if ( return_frame ) {
/* receive frame has no errors, get frame size.
* The frame size is the starting value of the RCC (which was
* set to 0xffff) minus the ending value of the RCC (decremented
* once for each receive character) minus 2 for the 16-bit CRC.
*/
framesize = RCLRVALUE - info->rx_buffer_list[EndIndex].rcc;
/* adjust frame size for CRC if any */
if ( info->params.crc_type == HDLC_CRC_16_CCITT )
framesize -= 2;
else if ( info->params.crc_type == HDLC_CRC_32_CCITT )
framesize -= 4;
}
if ( debug_level >= DEBUG_LEVEL_BH )
printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
__FILE__,__LINE__,info->device_name,status,framesize);
if ( debug_level >= DEBUG_LEVEL_DATA )
mgsl_trace_block(info,info->rx_buffer_list[StartIndex].virt_addr,
min_t(int, framesize, DMABUFFERSIZE),0);
if (framesize) {
if ( ( (info->params.crc_type & HDLC_CRC_RETURN_EX) &&
((framesize+1) > info->max_frame_size) ) ||
(framesize > info->max_frame_size) )
info->icount.rxlong++;
else {
/* copy dma buffer(s) to contiguous intermediate buffer */
int copy_count = framesize;
int index = StartIndex;
unsigned char *ptmp = info->intermediate_rxbuffer;
if ( !(status & RXSTATUS_CRC_ERROR))
info->icount.rxok++;
while(copy_count) {
int partial_count;
if ( copy_count > DMABUFFERSIZE )
partial_count = DMABUFFERSIZE;
else
partial_count = copy_count;
pBufEntry = &(info->rx_buffer_list[index]);
memcpy( ptmp, pBufEntry->virt_addr, partial_count );
ptmp += partial_count;
copy_count -= partial_count;
if ( ++index == info->rx_buffer_count )
index = 0;
}
if ( info->params.crc_type & HDLC_CRC_RETURN_EX ) {
++framesize;
*ptmp = (status & RXSTATUS_CRC_ERROR ?
RX_CRC_ERROR :
RX_OK);
if ( debug_level >= DEBUG_LEVEL_DATA )
printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
__FILE__,__LINE__,info->device_name,
*ptmp);
}
#if SYNCLINK_GENERIC_HDLC
if (info->netcount)
hdlcdev_rx(info,info->intermediate_rxbuffer,framesize);
else
#endif
ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
}
}
/* Free the buffers used by this frame. */
mgsl_free_rx_frame_buffers( info, StartIndex, EndIndex );
ReturnCode = true;
Cleanup:
if ( info->rx_enabled && info->rx_overflow ) {
/* The receiver needs to restarted because of
* a receive overflow (buffer or FIFO). If the
* receive buffers are now empty, then restart receiver.
*/
if ( !info->rx_buffer_list[EndIndex].status &&
info->rx_buffer_list[EndIndex].count ) {
spin_lock_irqsave(&info->irq_spinlock,flags);
usc_start_receiver(info);
spin_unlock_irqrestore(&info->irq_spinlock,flags);
}
}
return ReturnCode;
} /* end of mgsl_get_rx_frame() */
/* mgsl_get_raw_rx_frame()
*
* This function attempts to return a received frame from the
* receive DMA buffers when running in external loop mode. In this mode,
* we will return at most one DMABUFFERSIZE frame to the application.
* The USC receiver is triggering off of DCD going active to start a new
* frame, and DCD going inactive to terminate the frame (similar to
* processing a closing flag character).
*
* In this routine, we will return DMABUFFERSIZE "chunks" at a time.
* If DCD goes inactive, the last Rx DMA Buffer will have a non-zero
* status field and the RCC field will indicate the length of the
* entire received frame. We take this RCC field and get the modulus
* of RCC and DMABUFFERSIZE to determine if number of bytes in the
* last Rx DMA buffer and return that last portion of the frame.
*
* Arguments: info pointer to device extension
* Return Value: true if frame returned, otherwise false
*/
static bool mgsl_get_raw_rx_frame(struct mgsl_struct *info)
{
unsigned int CurrentIndex, NextIndex;
unsigned short status;
DMABUFFERENTRY *pBufEntry;
unsigned int framesize = 0;
bool ReturnCode = false;
unsigned long flags;
struct tty_struct *tty = info->port.tty;
/*
* current_rx_buffer points to the 1st buffer of the next available
* receive frame. The status field is set by the 16C32 after
* completing a receive frame. If the status field of this buffer
* is zero, either the USC is still filling this buffer or this
* is one of a series of buffers making up a received frame.
*
* If the count field of this buffer is zero, the USC is either
* using this buffer or has used this buffer. Look at the count
* field of the next buffer. If that next buffer's count is
* non-zero, the USC is still actively using the current buffer.
* Otherwise, if the next buffer's count field is zero, the
* current buffer is complete and the USC is using the next
* buffer.
*/
CurrentIndex = NextIndex = info->current_rx_buffer;
++NextIndex;
if ( NextIndex == info->rx_buffer_count )
NextIndex = 0;
if ( info->rx_buffer_list[CurrentIndex].status != 0 ||
(info->rx_buffer_list[CurrentIndex].count == 0 &&
info->rx_buffer_list[NextIndex].count == 0)) {
/*
* Either the status field of this dma buffer is non-zero
* (indicating the last buffer of a receive frame) or the next
* buffer is marked as in use -- implying this buffer is complete
* and an intermediate buffer for this received frame.
*/
status = info->rx_buffer_list[CurrentIndex].status;
if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
if ( status & RXSTATUS_SHORT_FRAME )
info->icount.rxshort++;
else if ( status & RXSTATUS_ABORT )
info->icount.rxabort++;
else if ( status & RXSTATUS_OVERRUN )
info->icount.rxover++;
else
info->icount.rxcrc++;
framesize = 0;
} else {
/*
* A receive frame is available, get frame size and status.
*
* The frame size is the starting value of the RCC (which was
* set to 0xffff) minus the ending value of the RCC (decremented
* once for each receive character) minus 2 or 4 for the 16-bit
* or 32-bit CRC.
*
* If the status field is zero, this is an intermediate buffer.
* It's size is 4K.
*
* If the DMA Buffer Entry's Status field is non-zero, the
* receive operation completed normally (ie: DCD dropped). The
* RCC field is valid and holds the received frame size.
* It is possible that the RCC field will be zero on a DMA buffer
* entry with a non-zero status. This can occur if the total
* frame size (number of bytes between the time DCD goes active
* to the time DCD goes inactive) exceeds 65535 bytes. In this
* case the 16C32 has underrun on the RCC count and appears to
* stop updating this counter to let us know the actual received
* frame size. If this happens (non-zero status and zero RCC),
* simply return the entire RxDMA Buffer
*/
if ( status ) {
/*
* In the event that the final RxDMA Buffer is
* terminated with a non-zero status and the RCC
* field is zero, we interpret this as the RCC
* having underflowed (received frame > 65535 bytes).
*
* Signal the event to the user by passing back
* a status of RxStatus_CrcError returning the full
* buffer and let the app figure out what data is
* actually valid
*/
if ( info->rx_buffer_list[CurrentIndex].rcc )
framesize = RCLRVALUE - info->rx_buffer_list[CurrentIndex].rcc;
else
framesize = DMABUFFERSIZE;
}
else
framesize = DMABUFFERSIZE;
}
if ( framesize > DMABUFFERSIZE ) {
/*
* if running in raw sync mode, ISR handler for
* End Of Buffer events terminates all buffers at 4K.
* If this frame size is said to be >4K, get the
* actual number of bytes of the frame in this buffer.
*/
framesize = framesize % DMABUFFERSIZE;
}
if ( debug_level >= DEBUG_LEVEL_BH )
printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
__FILE__,__LINE__,info->device_name,status,framesize);
if ( debug_level >= DEBUG_LEVEL_DATA )
mgsl_trace_block(info,info->rx_buffer_list[CurrentIndex].virt_addr,
min_t(int, framesize, DMABUFFERSIZE),0);
if (framesize) {
/* copy dma buffer(s) to contiguous intermediate buffer */
/* NOTE: we never copy more than DMABUFFERSIZE bytes */
pBufEntry = &(info->rx_buffer_list[CurrentIndex]);
memcpy( info->intermediate_rxbuffer, pBufEntry->virt_addr, framesize);
info->icount.rxok++;
ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
}
/* Free the buffers used by this frame. */
mgsl_free_rx_frame_buffers( info, CurrentIndex, CurrentIndex );
ReturnCode = true;
}
if ( info->rx_enabled && info->rx_overflow ) {
/* The receiver needs to restarted because of
* a receive overflow (buffer or FIFO). If the
* receive buffers are now empty, then restart receiver.
*/
if ( !info->rx_buffer_list[CurrentIndex].status &&
info->rx_buffer_list[CurrentIndex].count ) {
spin_lock_irqsave(&info->irq_spinlock,flags);
usc_start_receiver(info);
spin_unlock_irqrestore(&info->irq_spinlock,flags);
}
}
return ReturnCode;
} /* end of mgsl_get_raw_rx_frame() */
/* mgsl_load_tx_dma_buffer()
*
* Load the transmit DMA buffer with the specified data.
*
* Arguments:
*
* info pointer to device extension
* Buffer pointer to buffer containing frame to load
* BufferSize size in bytes of frame in Buffer
*
* Return Value: None
*/
static void mgsl_load_tx_dma_buffer(struct mgsl_struct *info,
const char *Buffer, unsigned int BufferSize)
{
unsigned short Copycount;
unsigned int i = 0;
DMABUFFERENTRY *pBufEntry;
if ( debug_level >= DEBUG_LEVEL_DATA )
mgsl_trace_block(info,Buffer, min_t(int, BufferSize, DMABUFFERSIZE), 1);
if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
/* set CMR:13 to start transmit when
* next GoAhead (abort) is received
*/
info->cmr_value |= BIT13;
}
/* begin loading the frame in the next available tx dma
* buffer, remember it's starting location for setting
* up tx dma operation
*/
i = info->current_tx_buffer;
info->start_tx_dma_buffer = i;
/* Setup the status and RCC (Frame Size) fields of the 1st */
/* buffer entry in the transmit DMA buffer list. */
info->tx_buffer_list[i].status = info->cmr_value & 0xf000;
info->tx_buffer_list[i].rcc = BufferSize;
info->tx_buffer_list[i].count = BufferSize;
/* Copy frame data from 1st source buffer to the DMA buffers. */
/* The frame data may span multiple DMA buffers. */
while( BufferSize ){
/* Get a pointer to next DMA buffer entry. */
pBufEntry = &info->tx_buffer_list[i++];
if ( i == info->tx_buffer_count )
i=0;
/* Calculate the number of bytes that can be copied from */
/* the source buffer to this DMA buffer. */
if ( BufferSize > DMABUFFERSIZE )
Copycount = DMABUFFERSIZE;
else
Copycount = BufferSize;
/* Actually copy data from source buffer to DMA buffer. */
/* Also set the data count for this individual DMA buffer. */
if ( info->bus_type == MGSL_BUS_TYPE_PCI )
mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount);
else
memcpy(pBufEntry->virt_addr, Buffer, Copycount);
pBufEntry->count = Copycount;
/* Advance source pointer and reduce remaining data count. */
Buffer += Copycount;
BufferSize -= Copycount;
++info->tx_dma_buffers_used;
}
/* remember next available tx dma buffer */
info->current_tx_buffer = i;
} /* end of mgsl_load_tx_dma_buffer() */
/*
* mgsl_register_test()
*
* Performs a register test of the 16C32.
*
* Arguments: info pointer to device instance data
* Return Value: true if test passed, otherwise false
*/
static bool mgsl_register_test( struct mgsl_struct *info )
{
static unsigned short BitPatterns[] =
{ 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
static unsigned int Patterncount = ARRAY_SIZE(BitPatterns);
unsigned int i;
bool rc = true;
unsigned long flags;
spin_lock_irqsave(&info->irq_spinlock,flags);
usc_reset(info);
/* Verify the reset state of some registers. */
if ( (usc_InReg( info, SICR ) != 0) ||
(usc_InReg( info, IVR ) != 0) ||
(usc_InDmaReg( info, DIVR ) != 0) ){
rc = false;
}
if ( rc ){
/* Write bit patterns to various registers but do it out of */
/* sync, then read back and verify values. */
for ( i = 0 ; i < Patterncount ; i++ ) {
usc_OutReg( info, TC0R, BitPatterns[i] );
usc_OutReg( info, TC1R, BitPatterns[(i+1)%Patterncount] );
usc_OutReg( info, TCLR, BitPatterns[(i+2)%Patterncount] );
usc_OutReg( info, RCLR, BitPatterns[(i+3)%Patterncount] );
usc_OutReg( info, RSR, BitPatterns[(i+4)%Patterncount] );
usc_OutDmaReg( info, TBCR, BitPatterns[(i+5)%Patterncount] );
if ( (usc_InReg( info, TC0R ) != BitPatterns[i]) ||
(usc_InReg( info, TC1R ) != BitPatterns[(i+1)%Patterncount]) ||
(usc_InReg( info, TCLR ) != BitPatterns[(i+2)%Patterncount]) ||
(usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) ||
(usc_InReg( info, RSR ) != BitPatterns[(i+4)%Patterncount]) ||
(usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){
rc = false;
break;
}
}
}
usc_reset(info);
spin_unlock_irqrestore(&info->irq_spinlock,flags);
return rc;
} /* end of mgsl_register_test() */
/* mgsl_irq_test() Perform interrupt test of the 16C32.
*
* Arguments: info pointer to device instance data
* Return Value: true if test passed, otherwise false
*/
static bool mgsl_irq_test( struct mgsl_struct *info )
{
unsigned long EndTime;
unsigned long flags;
spin_lock_irqsave(&info->irq_spinlock,flags);
usc_reset(info);
/*
* Setup 16C32 to interrupt on TxC pin (14MHz clock) transition.
* The ISR sets irq_occurred to true.
*/
info->irq_occurred = false;
/* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
/* Enable INTEN (Port 6, Bit12) */
/* This connects the IRQ request signal to the ISA bus */
/* on the ISA adapter. This has no effect for the PCI adapter */
usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) );
usc_EnableMasterIrqBit(info);
usc_EnableInterrupts(info, IO_PIN);
usc_ClearIrqPendingBits(info, IO_PIN);
usc_UnlatchIostatusBits(info, MISCSTATUS_TXC_LATCHED);
usc_EnableStatusIrqs(info, SICR_TXC_ACTIVE + SICR_TXC_INACTIVE);
spin_unlock_irqrestore(&info->irq_spinlock,flags);
EndTime=100;
while( EndTime-- && !info->irq_occurred ) {
msleep_interruptible(10);
}
spin_lock_irqsave(&info->irq_spinlock,flags);
usc_reset(info);
spin_unlock_irqrestore(&info->irq_spinlock,flags);
return info->irq_occurred;
} /* end of mgsl_irq_test() */
/* mgsl_dma_test()
*
* Perform a DMA test of the 16C32. A small frame is
* transmitted via DMA from a transmit buffer to a receive buffer
* using single buffer DMA mode.
*
* Arguments: info pointer to device instance data
* Return Value: true if test passed, otherwise false
*/
static bool mgsl_dma_test( struct mgsl_struct *info )
{
unsigned short FifoLevel;
unsigned long phys_addr;
unsigned int FrameSize;
unsigned int i;
char *TmpPtr;
bool rc = true;
unsigned short status=0;
unsigned long EndTime;
unsigned long flags;
MGSL_PARAMS tmp_params;
/* save current port options */
memcpy(&tmp_params,&info->params,sizeof(MGSL_PARAMS));
/* load default port options */
memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
#define TESTFRAMESIZE 40
spin_lock_irqsave(&info->irq_spinlock,flags);
/* setup 16C32 for SDLC DMA transfer mode */
usc_reset(info);
usc_set_sdlc_mode(info);
usc_enable_loopback(info,1);
/* Reprogram the RDMR so that the 16C32 does NOT clear the count
* field of the buffer entry after fetching buffer address. This
* way we can detect a DMA failure for a DMA read (which should be
* non-destructive to system memory) before we try and write to
* memory (where a failure could corrupt system memory).
*/
/* Receive DMA mode Register (RDMR)
*
* <15..14> 11 DMA mode = Linked List Buffer mode
* <13> 1 RSBinA/L = store Rx status Block in List entry
* <12> 0 1 = Clear count of List Entry after fetching
* <11..10> 00 Address mode = Increment
* <9> 1 Terminate Buffer on RxBound
* <8> 0 Bus Width = 16bits
* <7..0> ? status Bits (write as 0s)
*
* 1110 0010 0000 0000 = 0xe200
*/
usc_OutDmaReg( info, RDMR, 0xe200 );
spin_unlock_irqrestore(&info->irq_spinlock,flags);
/* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
FrameSize = TESTFRAMESIZE;
/* setup 1st transmit buffer entry: */
/* with frame size and transmit control word */
info->tx_buffer_list[0].count = FrameSize;
info->tx_buffer_list[0].rcc = FrameSize;
info->tx_buffer_list[0].status = 0x4000;
/* build a transmit frame in 1st transmit DMA buffer */
TmpPtr = info->tx_buffer_list[0].virt_addr;
for (i = 0; i < FrameSize; i++ )
*TmpPtr++ = i;
/* setup 1st receive buffer entry: */
/* clear status, set max receive buffer size */
info->rx_buffer_list[0].status = 0;
info->rx_buffer_list[0].count = FrameSize + 4;
/* zero out the 1st receive buffer */
memset( info->rx_buffer_list[0].virt_addr, 0, FrameSize + 4 );
/* Set count field of next buffer entries to prevent */
/* 16C32 from using buffers after the 1st one. */
info->tx_buffer_list[1].count = 0;
info->rx_buffer_list[1].count = 0;
/***************************/
/* Program 16C32 receiver. */
/***************************/
spin_lock_irqsave(&info->irq_spinlock,flags);
/* setup DMA transfers */
usc_RTCmd( info, RTCmd_PurgeRxFifo );
/* program 16C32 receiver with physical address of 1st DMA buffer entry */
phys_addr = info->rx_buffer_list[0].phys_entry;
usc_OutDmaReg( info, NRARL, (unsigned short)phys_addr );
usc_OutDmaReg( info, NRARU, (unsigned short)(phys_addr >> 16) );
/* Clear the Rx DMA status bits (read RDMR) and start channel */
usc_InDmaReg( info, RDMR );
usc_DmaCmd( info, DmaCmd_InitRxChannel );
/* Enable Receiver (RMR <1..0> = 10) */
usc_OutReg( info, RMR, (unsigned short)((usc_InReg(info, RMR) & 0xfffc) | 0x0002) );
spin_unlock_irqrestore(&info->irq_spinlock,flags);
/*************************************************************/
/* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
/*************************************************************/
/* Wait 100ms for interrupt. */
EndTime = jiffies + msecs_to_jiffies(100);
for(;;) {
if (time_after(jiffies, EndTime)) {
rc = false;
break;
}
spin_lock_irqsave(&info->irq_spinlock,flags);
status = usc_InDmaReg( info, RDMR );
spin_unlock_irqrestore(&info->irq_spinlock,flags);
if ( !(status & BIT4) && (status & BIT5) ) {
/* INITG (BIT 4) is inactive (no entry read in progress) AND */
/* BUSY (BIT 5) is active (channel still active). */
/* This means the buffer entry read has completed. */
break;
}
}
/******************************/
/* Program 16C32 transmitter. */
/******************************/
spin_lock_irqsave(&info->irq_spinlock,flags);
/* Program the Transmit Character Length Register (TCLR) */
/* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
usc_OutReg( info, TCLR, (unsigned short)info->tx_buffer_list[0].count );
usc_RTCmd( info, RTCmd_PurgeTxFifo );
/* Program the address of the 1st DMA Buffer Entry in linked list */
phys_addr = info->tx_buffer_list[0].phys_entry;
usc_OutDmaReg( info, NTARL, (unsigned short)phys_addr );
usc_OutDmaReg( info, NTARU, (unsigned short)(phys_addr >> 16) );
/* unlatch Tx status bits, and start transmit channel. */
usc_OutReg( info, TCSR, (unsigned short)(( usc_InReg(info, TCSR) & 0x0f00) | 0xfa) );
usc_DmaCmd( info, DmaCmd_InitTxChannel );
/* wait for DMA controller to fill transmit FIFO */
usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
spin_unlock_irqrestore(&info->irq_spinlock,flags);
/**********************************/
/* WAIT FOR TRANSMIT FIFO TO FILL */
/**********************************/
/* Wait 100ms */
EndTime = jiffies + msecs_to_jiffies(100);
for(;;) {
if (time_after(jiffies, EndTime)) {
rc = false;
break;
}
spin_lock_irqsave(&info->irq_spinlock,flags);
FifoLevel = usc_InReg(info, TICR) >> 8;
spin_unlock_irqrestore(&info->irq_spinlock,flags);
if ( FifoLevel < 16 )
break;
else
if ( FrameSize < 32 ) {
/* This frame is smaller than the entire transmit FIFO */
/* so wait for the entire frame to be loaded. */
if ( FifoLevel <= (32 - FrameSize) )
break;
}
}
if ( rc )
{
/* Enable 16C32 transmitter. */
spin_lock_irqsave(&info->irq_spinlock,flags);
/* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
usc_TCmd( info, TCmd_SendFrame );
usc_OutReg( info, TMR, (unsigned short)((usc_InReg(info, TMR) & 0xfffc) | 0x0002) );
spin_unlock_irqrestore(&info->irq_spinlock,flags);
/******************************/
/* WAIT FOR TRANSMIT COMPLETE */
/******************************/
/* Wait 100ms */
EndTime = jiffies + msecs_to_jiffies(100);
/* While timer not expired wait for transmit complete */
spin_lock_irqsave(&info->irq_spinlock,flags);
status = usc_InReg( info, TCSR );
spin_unlock_irqrestore(&info->irq_spinlock,flags);
while ( !(status & (BIT6+BIT5+BIT4+BIT2+BIT1)) ) {
if (time_after(jiffies, EndTime)) {
rc = false;
break;
}
spin_lock_irqsave(&info->irq_spinlock,flags);
status = usc_InReg( info, TCSR );
spin_unlock_irqrestore(&info->irq_spinlock,flags);
}
}
if ( rc ){
/* CHECK FOR TRANSMIT ERRORS */
if ( status & (BIT5 + BIT1) )
rc = false;
}
if ( rc ) {
/* WAIT FOR RECEIVE COMPLETE */
/* Wait 100ms */
EndTime = jiffies + msecs_to_jiffies(100);
/* Wait for 16C32 to write receive status to buffer entry. */
status=info->rx_buffer_list[0].status;
while ( status == 0 ) {
if (time_after(jiffies, EndTime)) {
rc = false;
break;
}
status=info->rx_buffer_list[0].status;
}
}
if ( rc ) {
/* CHECK FOR RECEIVE ERRORS */
status = info->rx_buffer_list[0].status;
if ( status & (BIT8 + BIT3 + BIT1) ) {
/* receive error has occurred */
rc = false;
} else {
if ( memcmp( info->tx_buffer_list[0].virt_addr ,
info->rx_buffer_list[0].virt_addr, FrameSize ) ){
rc = false;
}
}
}
spin_lock_irqsave(&info->irq_spinlock,flags);
usc_reset( info );
spin_unlock_irqrestore(&info->irq_spinlock,flags);
/* restore current port options */
memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
return rc;
} /* end of mgsl_dma_test() */
/* mgsl_adapter_test()
*
* Perform the register, IRQ, and DMA tests for the 16C32.
*
* Arguments: info pointer to device instance data
* Return Value: 0 if success, otherwise -ENODEV
*/
static int mgsl_adapter_test( struct mgsl_struct *info )
{
if ( debug_level >= DEBUG_LEVEL_INFO )
printk( "%s(%d):Testing device %s\n",
__FILE__,__LINE__,info->device_name );
if ( !mgsl_register_test( info ) ) {
info->init_error = DiagStatus_AddressFailure;
printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
__FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
return -ENODEV;
}
if ( !mgsl_irq_test( info ) ) {
info->init_error = DiagStatus_IrqFailure;
printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
__FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
return -ENODEV;
}
if ( !mgsl_dma_test( info ) ) {
info->init_error = DiagStatus_DmaFailure;
printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
__FILE__,__LINE__,info->device_name, (unsigned short)(info->dma_level) );
return -ENODEV;
}
if ( debug_level >= DEBUG_LEVEL_INFO )
printk( "%s(%d):device %s passed diagnostics\n",
__FILE__,__LINE__,info->device_name );
return 0;
} /* end of mgsl_adapter_test() */
/* mgsl_memory_test()
*
* Test the shared memory on a PCI adapter.
*
* Arguments: info pointer to device instance data
* Return Value: true if test passed, otherwise false
*/
static bool mgsl_memory_test( struct mgsl_struct *info )
{
static unsigned long BitPatterns[] =
{ 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
unsigned long Patterncount = ARRAY_SIZE(BitPatterns);
unsigned long i;
unsigned long TestLimit = SHARED_MEM_ADDRESS_SIZE/sizeof(unsigned long);
unsigned long * TestAddr;
if ( info->bus_type != MGSL_BUS_TYPE_PCI )
return true;
TestAddr = (unsigned long *)info->memory_base;
/* Test data lines with test pattern at one location. */
for ( i = 0 ; i < Patterncount ; i++ ) {
*TestAddr = BitPatterns[i];
if ( *TestAddr != BitPatterns[i] )
return false;
}
/* Test address lines with incrementing pattern over */
/* entire address range. */
for ( i = 0 ; i < TestLimit ; i++ ) {
*TestAddr = i * 4;
TestAddr++;
}
TestAddr = (unsigned long *)info->memory_base;
for ( i = 0 ; i < TestLimit ; i++ ) {
if ( *TestAddr != i * 4 )
return false;
TestAddr++;
}
memset( info->memory_base, 0, SHARED_MEM_ADDRESS_SIZE );
return true;
} /* End Of mgsl_memory_test() */
/* mgsl_load_pci_memory()
*
* Load a large block of data into the PCI shared memory.
* Use this instead of memcpy() or memmove() to move data
* into the PCI shared memory.
*
* Notes:
*
* This function prevents the PCI9050 interface chip from hogging
* the adapter local bus, which can starve the 16C32 by preventing
* 16C32 bus master cycles.
*
* The PCI9050 documentation says that the 9050 will always release
* control of the local bus after completing the current read
* or write operation.
*
* It appears that as long as the PCI9050 write FIFO is full, the
* PCI9050 treats all of the writes as a single burst transaction
* and will not release the bus. This causes DMA latency problems
* at high speeds when copying large data blocks to the shared
* memory.
*
* This function in effect, breaks the a large shared memory write
* into multiple transations by interleaving a shared memory read
* which will flush the write FIFO and 'complete' the write
* transation. This allows any pending DMA request to gain control
* of the local bus in a timely fasion.
*
* Arguments:
*
* TargetPtr pointer to target address in PCI shared memory
* SourcePtr pointer to source buffer for data
* count count in bytes of data to copy
*
* Return Value: None
*/
static void mgsl_load_pci_memory( char* TargetPtr, const char* SourcePtr,
unsigned short count )
{
/* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */
#define PCI_LOAD_INTERVAL 64
unsigned short Intervalcount = count / PCI_LOAD_INTERVAL;
unsigned short Index;
unsigned long Dummy;
for ( Index = 0 ; Index < Intervalcount ; Index++ )
{
memcpy(TargetPtr, SourcePtr, PCI_LOAD_INTERVAL);
Dummy = *((volatile unsigned long *)TargetPtr);
TargetPtr += PCI_LOAD_INTERVAL;
SourcePtr += PCI_LOAD_INTERVAL;
}
memcpy( TargetPtr, SourcePtr, count % PCI_LOAD_INTERVAL );
} /* End Of mgsl_load_pci_memory() */
static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit)
{
int i;
int linecount;
if (xmit)
printk("%s tx data:\n",info->device_name);
else
printk("%s rx data:\n",info->device_name);
while(count) {
if (count > 16)
linecount = 16;
else
linecount = count;
for(i=0;i<linecount;i++)
printk("%02X ",(unsigned char)data[i]);
for(;i<17;i++)
printk(" ");
for(i=0;i<linecount;i++) {
if (data[i]>=040 && data[i]<=0176)
printk("%c",data[i]);
else
printk(".");
}
printk("\n");
data += linecount;
count -= linecount;
}
} /* end of mgsl_trace_block() */
/* mgsl_tx_timeout()
*
* called when HDLC frame times out
* update stats and do tx completion processing
*
* Arguments: context pointer to device instance data
* Return Value: None
*/
static void mgsl_tx_timeout(unsigned long context)
{
struct mgsl_struct *info = (struct mgsl_struct*)context;
unsigned long flags;
if ( debug_level >= DEBUG_LEVEL_INFO )
printk( "%s(%d):mgsl_tx_timeout(%s)\n",
__FILE__,__LINE__,info->device_name);
if(info->tx_active &&
(info->params.mode == MGSL_MODE_HDLC ||
info->params.mode == MGSL_MODE_RAW) ) {
info->icount.txtimeout++;
}
spin_lock_irqsave(&info->irq_spinlock,flags);
info->tx_active = false;
info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
usc_loopmode_cancel_transmit( info );
spin_unlock_irqrestore(&info->irq_spinlock,flags);
#if SYNCLINK_GENERIC_HDLC
if (info->netcount)
hdlcdev_tx_done(info);
else
#endif
mgsl_bh_transmit(info);
} /* end of mgsl_tx_timeout() */
/* signal that there are no more frames to send, so that
* line is 'released' by echoing RxD to TxD when current
* transmission is complete (or immediately if no tx in progress).
*/
static int mgsl_loopmode_send_done( struct mgsl_struct * info )
{
unsigned long flags;
spin_lock_irqsave(&info->irq_spinlock,flags);
if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
if (info->tx_active)
info->loopmode_send_done_requested = true;
else
usc_loopmode_send_done(info);
}
spin_unlock_irqrestore(&info->irq_spinlock,flags);
return 0;
}
/* release the line by echoing RxD to TxD
* upon completion of a transmit frame
*/
static void usc_loopmode_send_done( struct mgsl_struct * info )
{
info->loopmode_send_done_requested = false;
/* clear CMR:13 to 0 to start echoing RxData to TxData */
info->cmr_value &= ~BIT13;
usc_OutReg(info, CMR, info->cmr_value);
}
/* abort a transmit in progress while in HDLC LoopMode
*/
static void usc_loopmode_cancel_transmit( struct mgsl_struct * info )
{
/* reset tx dma channel and purge TxFifo */
usc_RTCmd( info, RTCmd_PurgeTxFifo );
usc_DmaCmd( info, DmaCmd_ResetTxChannel );
usc_loopmode_send_done( info );
}
/* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
* is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
* we must clear CMR:13 to begin repeating TxData to RxData
*/
static void usc_loopmode_insert_request( struct mgsl_struct * info )
{
info->loopmode_insert_requested = true;
/* enable RxAbort irq. On next RxAbort, clear CMR:13 to
* begin repeating TxData on RxData (complete insertion)
*/
usc_OutReg( info, RICR,
(usc_InReg( info, RICR ) | RXSTATUS_ABORT_RECEIVED ) );
/* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
info->cmr_value |= BIT13;
usc_OutReg(info, CMR, info->cmr_value);
}
/* return 1 if station is inserted into the loop, otherwise 0
*/
static int usc_loopmode_active( struct mgsl_struct * info)
{
return usc_InReg( info, CCSR ) & BIT7 ? 1 : 0 ;
}
#if SYNCLINK_GENERIC_HDLC
/**
* called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
* set encoding and frame check sequence (FCS) options
*
* dev pointer to network device structure
* encoding serial encoding setting
* parity FCS setting
*
* returns 0 if success, otherwise error code
*/
static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
unsigned short parity)
{
struct mgsl_struct *info = dev_to_port(dev);
unsigned char new_encoding;
unsigned short new_crctype;
/* return error if TTY interface open */
if (info->port.count)
return -EBUSY;
switch (encoding)
{
case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
default: return -EINVAL;
}
switch (parity)
{
case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
default: return -EINVAL;
}
info->params.encoding = new_encoding;
info->params.crc_type = new_crctype;
/* if network interface up, reprogram hardware */
if (info->netcount)
mgsl_program_hw(info);
return 0;
}
/**
* called by generic HDLC layer to send frame
*
* skb socket buffer containing HDLC frame
* dev pointer to network device structure
*
* returns 0 if success, otherwise error code
*/
static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
{
struct mgsl_struct *info = dev_to_port(dev);
unsigned long flags;
if (debug_level >= DEBUG_LEVEL_INFO)
printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
/* stop sending until this frame completes */
netif_stop_queue(dev);
/* copy data to device buffers */
info->xmit_cnt = skb->len;
mgsl_load_tx_dma_buffer(info, skb->data, skb->len);
/* update network statistics */
dev->stats.tx_packets++;
dev->stats.tx_bytes += skb->len;
/* done with socket buffer, so free it */
dev_kfree_skb(skb);
/* save start time for transmit timeout detection */
dev->trans_start = jiffies;
/* start hardware transmitter if necessary */
spin_lock_irqsave(&info->irq_spinlock,flags);
if (!info->tx_active)
usc_start_transmitter(info);
spin_unlock_irqrestore(&info->irq_spinlock,flags);
return 0;
}
/**
* called by network layer when interface enabled
* claim resources and initialize hardware
*
* dev pointer to network device structure
*
* returns 0 if success, otherwise error code
*/
static int hdlcdev_open(struct net_device *dev)
{
struct mgsl_struct *info = dev_to_port(dev);
int rc;
unsigned long flags;
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
/* generic HDLC layer open processing */
if ((rc = hdlc_open(dev)))
return rc;
/* arbitrate between network and tty opens */
spin_lock_irqsave(&info->netlock, flags);
if (info->port.count != 0 || info->netcount != 0) {
printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
spin_unlock_irqrestore(&info->netlock, flags);
return -EBUSY;
}
info->netcount=1;
spin_unlock_irqrestore(&info->netlock, flags);
/* claim resources and init adapter */
if ((rc = startup(info)) != 0) {
spin_lock_irqsave(&info->netlock, flags);
info->netcount=0;
spin_unlock_irqrestore(&info->netlock, flags);
return rc;
}
/* assert DTR and RTS, apply hardware settings */
info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
mgsl_program_hw(info);
/* enable network layer transmit */
dev->trans_start = jiffies;
netif_start_queue(dev);
/* inform generic HDLC layer of current DCD status */
spin_lock_irqsave(&info->irq_spinlock, flags);
usc_get_serial_signals(info);
spin_unlock_irqrestore(&info->irq_spinlock, flags);
if (info->serial_signals & SerialSignal_DCD)
netif_carrier_on(dev);
else
netif_carrier_off(dev);
return 0;
}
/**
* called by network layer when interface is disabled
* shutdown hardware and release resources
*
* dev pointer to network device structure
*
* returns 0 if success, otherwise error code
*/
static int hdlcdev_close(struct net_device *dev)
{
struct mgsl_struct *info = dev_to_port(dev);
unsigned long flags;
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
netif_stop_queue(dev);
/* shutdown adapter and release resources */
shutdown(info);
hdlc_close(dev);
spin_lock_irqsave(&info->netlock, flags);
info->netcount=0;
spin_unlock_irqrestore(&info->netlock, flags);
return 0;
}
/**
* called by network layer to process IOCTL call to network device
*
* dev pointer to network device structure
* ifr pointer to network interface request structure
* cmd IOCTL command code
*
* returns 0 if success, otherwise error code
*/
static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
{
const size_t size = sizeof(sync_serial_settings);
sync_serial_settings new_line;
sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
struct mgsl_struct *info = dev_to_port(dev);
unsigned int flags;
if (debug_level >= DEBUG_LEVEL_INFO)
printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
/* return error if TTY interface open */
if (info->port.count)
return -EBUSY;
if (cmd != SIOCWANDEV)
return hdlc_ioctl(dev, ifr, cmd);
switch(ifr->ifr_settings.type) {
case IF_GET_IFACE: /* return current sync_serial_settings */
ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
if (ifr->ifr_settings.size < size) {
ifr->ifr_settings.size = size; /* data size wanted */
return -ENOBUFS;
}
flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
switch (flags){
case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
default: new_line.clock_type = CLOCK_DEFAULT;
}
new_line.clock_rate = info->params.clock_speed;
new_line.loopback = info->params.loopback ? 1:0;
if (copy_to_user(line, &new_line, size))
return -EFAULT;
return 0;
case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
if(!capable(CAP_NET_ADMIN))
return -EPERM;
if (copy_from_user(&new_line, line, size))
return -EFAULT;
switch (new_line.clock_type)
{
case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
case CLOCK_DEFAULT: flags = info->params.flags &
(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
default: return -EINVAL;
}
if (new_line.loopback != 0 && new_line.loopback != 1)
return -EINVAL;
info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
info->params.flags |= flags;
info->params.loopback = new_line.loopback;
if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
info->params.clock_speed = new_line.clock_rate;
else
info->params.clock_speed = 0;
/* if network interface up, reprogram hardware */
if (info->netcount)
mgsl_program_hw(info);
return 0;
default:
return hdlc_ioctl(dev, ifr, cmd);
}
}
/**
* called by network layer when transmit timeout is detected
*
* dev pointer to network device structure
*/
static void hdlcdev_tx_timeout(struct net_device *dev)
{
struct mgsl_struct *info = dev_to_port(dev);
unsigned long flags;
if (debug_level >= DEBUG_LEVEL_INFO)
printk("hdlcdev_tx_timeout(%s)\n",dev->name);
dev->stats.tx_errors++;
dev->stats.tx_aborted_errors++;
spin_lock_irqsave(&info->irq_spinlock,flags);
usc_stop_transmitter(info);
spin_unlock_irqrestore(&info->irq_spinlock,flags);
netif_wake_queue(dev);
}
/**
* called by device driver when transmit completes
* reenable network layer transmit if stopped
*
* info pointer to device instance information
*/
static void hdlcdev_tx_done(struct mgsl_struct *info)
{
if (netif_queue_stopped(info->netdev))
netif_wake_queue(info->netdev);
}
/**
* called by device driver when frame received
* pass frame to network layer
*
* info pointer to device instance information
* buf pointer to buffer contianing frame data
* size count of data bytes in buf
*/
static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size)
{
struct sk_buff *skb = dev_alloc_skb(size);
struct net_device *dev = info->netdev;
if (debug_level >= DEBUG_LEVEL_INFO)
printk("hdlcdev_rx(%s)\n", dev->name);
if (skb == NULL) {
printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
dev->name);
dev->stats.rx_dropped++;
return;
}
memcpy(skb_put(skb, size), buf, size);
skb->protocol = hdlc_type_trans(skb, dev);
dev->stats.rx_packets++;
dev->stats.rx_bytes += size;
netif_rx(skb);
dev->last_rx = jiffies;
}
/**
* called by device driver when adding device instance
* do generic HDLC initialization
*
* info pointer to device instance information
*
* returns 0 if success, otherwise error code
*/
static int hdlcdev_init(struct mgsl_struct *info)
{
int rc;
struct net_device *dev;
hdlc_device *hdlc;
/* allocate and initialize network and HDLC layer objects */
if (!(dev = alloc_hdlcdev(info))) {
printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
return -ENOMEM;
}
/* for network layer reporting purposes only */
dev->base_addr = info->io_base;
dev->irq = info->irq_level;
dev->dma = info->dma_level;
/* network layer callbacks and settings */
dev->do_ioctl = hdlcdev_ioctl;
dev->open = hdlcdev_open;
dev->stop = hdlcdev_close;
dev->tx_timeout = hdlcdev_tx_timeout;
dev->watchdog_timeo = 10*HZ;
dev->tx_queue_len = 50;
/* generic HDLC layer callbacks and settings */
hdlc = dev_to_hdlc(dev);
hdlc->attach = hdlcdev_attach;
hdlc->xmit = hdlcdev_xmit;
/* register objects with HDLC layer */
if ((rc = register_hdlc_device(dev))) {
printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
free_netdev(dev);
return rc;
}
info->netdev = dev;
return 0;
}
/**
* called by device driver when removing device instance
* do generic HDLC cleanup
*
* info pointer to device instance information
*/
static void hdlcdev_exit(struct mgsl_struct *info)
{
unregister_hdlc_device(info->netdev);
free_netdev(info->netdev);
info->netdev = NULL;
}
#endif /* CONFIG_HDLC */
static int __devinit synclink_init_one (struct pci_dev *dev,
const struct pci_device_id *ent)
{
struct mgsl_struct *info;
if (pci_enable_device(dev)) {
printk("error enabling pci device %p\n", dev);
return -EIO;
}
if (!(info = mgsl_allocate_device())) {
printk("can't allocate device instance data.\n");
return -EIO;
}
/* Copy user configuration info to device instance data */
info->io_base = pci_resource_start(dev, 2);
info->irq_level = dev->irq;
info->phys_memory_base = pci_resource_start(dev, 3);
/* Because veremap only works on page boundaries we must map
* a larger area than is actually implemented for the LCR
* memory range. We map a full page starting at the page boundary.
*/
info->phys_lcr_base = pci_resource_start(dev, 0);
info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
info->phys_lcr_base &= ~(PAGE_SIZE-1);
info->bus_type = MGSL_BUS_TYPE_PCI;
info->io_addr_size = 8;
info->irq_flags = IRQF_SHARED;
if (dev->device == 0x0210) {
/* Version 1 PCI9030 based universal PCI adapter */
info->misc_ctrl_value = 0x007c4080;
info->hw_version = 1;
} else {
/* Version 0 PCI9050 based 5V PCI adapter
* A PCI9050 bug prevents reading LCR registers if
* LCR base address bit 7 is set. Maintain shadow
* value so we can write to LCR misc control reg.
*/
info->misc_ctrl_value = 0x087e4546;
info->hw_version = 0;
}
mgsl_add_device(info);
return 0;
}
static void __devexit synclink_remove_one (struct pci_dev *dev)
{
}