sunxvr500.c 11.3 KB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462
/* sunxvr500.c: Sun 3DLABS XVR-500 Expert3D driver for sparc64 systems
 *
 * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/fb.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/of_device.h>

#include <asm/io.h>

/* XXX This device has a 'dev-comm' property which apparently is
 * XXX a pointer into the openfirmware's address space which is
 * XXX a shared area the kernel driver can use to keep OBP
 * XXX informed about the current resolution setting.  The idea
 * XXX is that the kernel can change resolutions, and as long
 * XXX as the values in the 'dev-comm' area are accurate then
 * XXX OBP can still render text properly to the console.
 * XXX
 * XXX I'm still working out the layout of this and whether there
 * XXX are any signatures we need to look for etc.
 */
struct e3d_info {
	struct fb_info		*info;
	struct pci_dev		*pdev;

	spinlock_t		lock;

	char __iomem		*fb_base;
	unsigned long		fb_base_phys;

	unsigned long		fb8_buf_diff;
	unsigned long		regs_base_phys;

	void __iomem		*ramdac;

	struct device_node	*of_node;

	unsigned int		width;
	unsigned int		height;
	unsigned int		depth;
	unsigned int		fb_size;

	u32			fb_base_reg;
	u32			fb8_0_off;
	u32			fb8_1_off;

	u32			pseudo_palette[16];
};

static int e3d_get_props(struct e3d_info *ep)
{
	ep->width = of_getintprop_default(ep->of_node, "width", 0);
	ep->height = of_getintprop_default(ep->of_node, "height", 0);
	ep->depth = of_getintprop_default(ep->of_node, "depth", 8);

	if (!ep->width || !ep->height) {
		printk(KERN_ERR "e3d: Critical properties missing for %s\n",
		       pci_name(ep->pdev));
		return -EINVAL;
	}

	return 0;
}

/* My XVR-500 comes up, at 1280x768 and a FB base register value of
 * 0x04000000, the following video layout register values:
 *
 * RAMDAC_VID_WH	0x03ff04ff
 * RAMDAC_VID_CFG	0x1a0b0088
 * RAMDAC_VID_32FB_0	0x04000000
 * RAMDAC_VID_32FB_1	0x04800000
 * RAMDAC_VID_8FB_0	0x05000000
 * RAMDAC_VID_8FB_1	0x05200000
 * RAMDAC_VID_XXXFB	0x05400000
 * RAMDAC_VID_YYYFB	0x05c00000
 * RAMDAC_VID_ZZZFB	0x05e00000
 */
/* Video layout registers */
#define RAMDAC_VID_WH		0x00000070UL /* (height-1)<<16 | (width-1) */
#define RAMDAC_VID_CFG		0x00000074UL /* 0x1a000088|(linesz_log2<<16) */
#define RAMDAC_VID_32FB_0	0x00000078UL /* PCI base 32bpp FB buffer 0 */
#define RAMDAC_VID_32FB_1	0x0000007cUL /* PCI base 32bpp FB buffer 1 */
#define RAMDAC_VID_8FB_0	0x00000080UL /* PCI base 8bpp FB buffer 0 */
#define RAMDAC_VID_8FB_1	0x00000084UL /* PCI base 8bpp FB buffer 1 */
#define RAMDAC_VID_XXXFB	0x00000088UL /* PCI base of XXX FB */
#define RAMDAC_VID_YYYFB	0x0000008cUL /* PCI base of YYY FB */
#define RAMDAC_VID_ZZZFB	0x00000090UL /* PCI base of ZZZ FB */

/* CLUT registers */
#define RAMDAC_INDEX		0x000000bcUL
#define RAMDAC_DATA		0x000000c0UL

static void e3d_clut_write(struct e3d_info *ep, int index, u32 val)
{
	void __iomem *ramdac = ep->ramdac;
	unsigned long flags;

	spin_lock_irqsave(&ep->lock, flags);

	writel(index, ramdac + RAMDAC_INDEX);
	writel(val, ramdac + RAMDAC_DATA);

	spin_unlock_irqrestore(&ep->lock, flags);
}

static int e3d_setcolreg(unsigned regno,
			 unsigned red, unsigned green, unsigned blue,
			 unsigned transp, struct fb_info *info)
{
	struct e3d_info *ep = info->par;
	u32 red_8, green_8, blue_8;
	u32 red_10, green_10, blue_10;
	u32 value;

	if (regno >= 256)
		return 1;

	red_8 = red >> 8;
	green_8 = green >> 8;
	blue_8 = blue >> 8;

	value = (blue_8 << 24) | (green_8 << 16) | (red_8 << 8);

	if (info->fix.visual == FB_VISUAL_TRUECOLOR && regno < 16)
		((u32 *)info->pseudo_palette)[regno] = value;


	red_10 = red >> 6;
	green_10 = green >> 6;
	blue_10 = blue >> 6;

	value = (blue_10 << 20) | (green_10 << 10) | (red_10 << 0);
	e3d_clut_write(ep, regno, value);

	return 0;
}

/* XXX This is a bit of a hack.  I can't figure out exactly how the
 * XXX two 8bpp areas of the framebuffer work.  I imagine there is
 * XXX a WID attribute somewhere else in the framebuffer which tells
 * XXX the ramdac which of the two 8bpp framebuffer regions to take
 * XXX the pixel from.  So, for now, render into both regions to make
 * XXX sure the pixel shows up.
 */
static void e3d_imageblit(struct fb_info *info, const struct fb_image *image)
{
	struct e3d_info *ep = info->par;
	unsigned long flags;

	spin_lock_irqsave(&ep->lock, flags);
	cfb_imageblit(info, image);
	info->screen_base += ep->fb8_buf_diff;
	cfb_imageblit(info, image);
	info->screen_base -= ep->fb8_buf_diff;
	spin_unlock_irqrestore(&ep->lock, flags);
}

static void e3d_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
	struct e3d_info *ep = info->par;
	unsigned long flags;

	spin_lock_irqsave(&ep->lock, flags);
	cfb_fillrect(info, rect);
	info->screen_base += ep->fb8_buf_diff;
	cfb_fillrect(info, rect);
	info->screen_base -= ep->fb8_buf_diff;
	spin_unlock_irqrestore(&ep->lock, flags);
}

static void e3d_copyarea(struct fb_info *info, const struct fb_copyarea *area)
{
	struct e3d_info *ep = info->par;
	unsigned long flags;

	spin_lock_irqsave(&ep->lock, flags);
	cfb_copyarea(info, area);
	info->screen_base += ep->fb8_buf_diff;
	cfb_copyarea(info, area);
	info->screen_base -= ep->fb8_buf_diff;
	spin_unlock_irqrestore(&ep->lock, flags);
}

static struct fb_ops e3d_ops = {
	.owner			= THIS_MODULE,
	.fb_setcolreg		= e3d_setcolreg,
	.fb_fillrect		= e3d_fillrect,
	.fb_copyarea		= e3d_copyarea,
	.fb_imageblit		= e3d_imageblit,
};

static int e3d_set_fbinfo(struct e3d_info *ep)
{
	struct fb_info *info = ep->info;
	struct fb_var_screeninfo *var = &info->var;

	info->flags = FBINFO_DEFAULT;
	info->fbops = &e3d_ops;
	info->screen_base = ep->fb_base;
	info->screen_size = ep->fb_size;

	info->pseudo_palette = ep->pseudo_palette;

	/* Fill fix common fields */
	strlcpy(info->fix.id, "e3d", sizeof(info->fix.id));
        info->fix.smem_start = ep->fb_base_phys;
        info->fix.smem_len = ep->fb_size;
        info->fix.type = FB_TYPE_PACKED_PIXELS;
	if (ep->depth == 32 || ep->depth == 24)
		info->fix.visual = FB_VISUAL_TRUECOLOR;
	else
		info->fix.visual = FB_VISUAL_PSEUDOCOLOR;

	var->xres = ep->width;
	var->yres = ep->height;
	var->xres_virtual = var->xres;
	var->yres_virtual = var->yres;
	var->bits_per_pixel = ep->depth;

	var->red.offset = 8;
	var->red.length = 8;
	var->green.offset = 16;
	var->green.length = 8;
	var->blue.offset = 24;
	var->blue.length = 8;
	var->transp.offset = 0;
	var->transp.length = 0;

	if (fb_alloc_cmap(&info->cmap, 256, 0)) {
		printk(KERN_ERR "e3d: Cannot allocate color map.\n");
		return -ENOMEM;
	}

        return 0;
}

static int e3d_pci_register(struct pci_dev *pdev,
			    const struct pci_device_id *ent)
{
	struct device_node *of_node;
	const char *device_type;
	struct fb_info *info;
	struct e3d_info *ep;
	unsigned int line_length;
	int err;

	of_node = pci_device_to_OF_node(pdev);
	if (!of_node) {
		printk(KERN_ERR "e3d: Cannot find OF node of %s\n",
		       pci_name(pdev));
		return -ENODEV;
	}

	device_type = of_get_property(of_node, "device_type", NULL);
	if (!device_type) {
		printk(KERN_INFO "e3d: Ignoring secondary output device "
		       "at %s\n", pci_name(pdev));
		return -ENODEV;
	}

	err = pci_enable_device(pdev);
	if (err < 0) {
		printk(KERN_ERR "e3d: Cannot enable PCI device %s\n",
		       pci_name(pdev));
		goto err_out;
	}

	info = framebuffer_alloc(sizeof(struct e3d_info), &pdev->dev);
	if (!info) {
		printk(KERN_ERR "e3d: Cannot allocate fb_info\n");
		err = -ENOMEM;
		goto err_disable;
	}

	ep = info->par;
	ep->info = info;
	ep->pdev = pdev;
	spin_lock_init(&ep->lock);
	ep->of_node = of_node;

	/* Read the PCI base register of the frame buffer, which we
	 * need in order to interpret the RAMDAC_VID_*FB* values in
	 * the ramdac correctly.
	 */
	pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0,
			      &ep->fb_base_reg);
	ep->fb_base_reg &= PCI_BASE_ADDRESS_MEM_MASK;

	ep->regs_base_phys = pci_resource_start (pdev, 1);
	err = pci_request_region(pdev, 1, "e3d regs");
	if (err < 0) {
		printk("e3d: Cannot request region 1 for %s\n",
		       pci_name(pdev));
		goto err_release_fb;
	}
	ep->ramdac = ioremap(ep->regs_base_phys + 0x8000, 0x1000);
	if (!ep->ramdac) {
		err = -ENOMEM;
		goto err_release_pci1;
	}

	ep->fb8_0_off = readl(ep->ramdac + RAMDAC_VID_8FB_0);
	ep->fb8_0_off -= ep->fb_base_reg;

	ep->fb8_1_off = readl(ep->ramdac + RAMDAC_VID_8FB_1);
	ep->fb8_1_off -= ep->fb_base_reg;

	ep->fb8_buf_diff = ep->fb8_1_off - ep->fb8_0_off;

	ep->fb_base_phys = pci_resource_start (pdev, 0);
	ep->fb_base_phys += ep->fb8_0_off;

	err = pci_request_region(pdev, 0, "e3d framebuffer");
	if (err < 0) {
		printk("e3d: Cannot request region 0 for %s\n",
		       pci_name(pdev));
		goto err_unmap_ramdac;
	}

	err = e3d_get_props(ep);
	if (err)
		goto err_release_pci0;

	line_length = (readl(ep->ramdac + RAMDAC_VID_CFG) >> 16) & 0xff;
	line_length = 1 << line_length;

	switch (ep->depth) {
	case 8:
		info->fix.line_length = line_length;
		break;
	case 16:
		info->fix.line_length = line_length * 2;
		break;
	case 24:
		info->fix.line_length = line_length * 3;
		break;
	case 32:
		info->fix.line_length = line_length * 4;
		break;
	}
	ep->fb_size = info->fix.line_length * ep->height;

	ep->fb_base = ioremap(ep->fb_base_phys, ep->fb_size);
	if (!ep->fb_base) {
		err = -ENOMEM;
		goto err_release_pci0;
	}

	err = e3d_set_fbinfo(ep);
	if (err)
		goto err_unmap_fb;

	pci_set_drvdata(pdev, info);

	printk("e3d: Found device at %s\n", pci_name(pdev));

	err = register_framebuffer(info);
	if (err < 0) {
		printk(KERN_ERR "e3d: Could not register framebuffer %s\n",
		       pci_name(pdev));
		goto err_free_cmap;
	}

	return 0;

err_free_cmap:
	fb_dealloc_cmap(&info->cmap);

err_unmap_fb:
	iounmap(ep->fb_base);

err_release_pci0:
	pci_release_region(pdev, 0);

err_unmap_ramdac:
	iounmap(ep->ramdac);

err_release_pci1:
	pci_release_region(pdev, 1);

err_release_fb:
        framebuffer_release(info);

err_disable:
	pci_disable_device(pdev);

err_out:
	return err;
}

static void e3d_pci_unregister(struct pci_dev *pdev)
{
	struct fb_info *info = pci_get_drvdata(pdev);
	struct e3d_info *ep = info->par;

	unregister_framebuffer(info);

	iounmap(ep->ramdac);
	iounmap(ep->fb_base);

	pci_release_region(pdev, 0);
	pci_release_region(pdev, 1);

	fb_dealloc_cmap(&info->cmap);
        framebuffer_release(info);

	pci_disable_device(pdev);
}

static struct pci_device_id e3d_pci_table[] = {
	{	PCI_DEVICE(PCI_VENDOR_ID_3DLABS, 0x7a0),	},
	{	PCI_DEVICE(0x1091, 0x7a0),			},
	{	PCI_DEVICE(PCI_VENDOR_ID_3DLABS, 0x7a2),	},
	{	.vendor = PCI_VENDOR_ID_3DLABS,
		.device = PCI_ANY_ID,
		.subvendor = PCI_VENDOR_ID_3DLABS,
		.subdevice = 0x0108,
	},
	{	.vendor = PCI_VENDOR_ID_3DLABS,
		.device = PCI_ANY_ID,
		.subvendor = PCI_VENDOR_ID_3DLABS,
		.subdevice = 0x0140,
	},
	{	.vendor = PCI_VENDOR_ID_3DLABS,
		.device = PCI_ANY_ID,
		.subvendor = PCI_VENDOR_ID_3DLABS,
		.subdevice = 0x1024,
	},
	{ 0, }
};

static struct pci_driver e3d_driver = {
	.name		= "e3d",
	.id_table	= e3d_pci_table,
	.probe		= e3d_pci_register,
	.remove		= e3d_pci_unregister,
};

static int __init e3d_init(void)
{
	if (fb_get_options("e3d", NULL))
		return -ENODEV;

	return pci_register_driver(&e3d_driver);
}

static void __exit e3d_exit(void)
{
	pci_unregister_driver(&e3d_driver);
}

module_init(e3d_init);
module_exit(e3d_exit);

MODULE_DESCRIPTION("framebuffer driver for Sun XVR-500 graphics");
MODULE_AUTHOR("David S. Miller <davem@davemloft.net>");
MODULE_VERSION("1.0");
MODULE_LICENSE("GPL");