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Commit 07a801def46f412a7ce6de9553dfd8895bf33356

Authored by Ralf Baechle
Committed by
1 parent f12555d24c
Exists in master and in 39 other branches 8mp-imx_5.4.70_2.3.0, 8qm-imx_5.4.70_2.3.0, emb_imx_lf-5.15.y, emb_lf-6.1.y, imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, imx_4.1.15_1.0.0_ga, pitx_8mp_lf-5.10.y, rt-smarc-imx_4.1.15_1.0.0_ga, rt_linux_5.15.71, smarc-8m-android-11.0.0_2.0.0, smarc-imx6_4.14.98_2.0.0_ga, smarc-imx6_4.9.88_2.0.0_ga, smarc-imx7_4.14.98_2.0.0_ga, smarc-imx7_4.9.11_1.0.0_ga, smarc-imx7_4.9.88_2.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-imx_4.1.15_1.0.0_ga, smarc-imx_4.9.11_1.0.0_ga, smarc-imx_4.9.51_imx8m_ga, smarc-imx_4.9.88_2.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_1.2.0_ga, smarc_8m_00d0_imx_4.14.98_2.0.0_ga, smarc_8m_imx_4.14.78_1.0.0_ga, smarc_8m_imx_4.14.98_2.0.0_ga, smarc_8m_imx_4.19.35_1.1.0, smarc_8mm_imx_4.14.78_1.0.0_ga, smarc_8mm_imx_4.14.98_2.0.0_ga, smarc_8mm_imx_4.19.35_1.1.0, smarc_8mm_imx_5.4.24_2.1.0, smarc_8mp_lf-5.10.y, smarc_8mq_imx_5.4.24_2.1.0, smarc_8mq_lf-5.10.y, smarc_imx_lf-5.15.y

MIPS: DSP: Set all register masks to 0x3ff. 

0x2ff was a typo and the value 0x1f of DSP_MASK was refering to an old
version of the documentation.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Showing 1 changed file with 3 additions and 3 deletions Side-by-side Diff

include/asm-mips/dsp.h
Diff comments   View file @ 07a801d
... ... @@ -16,7 +16,7 @@
16 16 #include <asm/mipsregs.h>
17 17  
18 18 #define DSP_DEFAULT 0x00000000
19   -#define DSP_MASK 0x1f
  19 +#define DSP_MASK 0x3ff
20 20  
21 21 #define __enable_dsp_hazard() \
22 22 do { \
... ... @@ -48,7 +48,7 @@
48 48 tsk->thread.dsp.dspr[3] = mflo2(); \
49 49 tsk->thread.dsp.dspr[4] = mfhi3(); \
50 50 tsk->thread.dsp.dspr[5] = mflo3(); \
51   - tsk->thread.dsp.dspcontrol = rddsp(0x2ff); \
  51 + tsk->thread.dsp.dspcontrol = rddsp(DSP_MASK); \
52 52 } while (0)
53 53  
54 54 #define save_dsp(tsk) \
... ... @@ -65,7 +65,7 @@
65 65 mtlo2(tsk->thread.dsp.dspr[3]); \
66 66 mthi3(tsk->thread.dsp.dspr[4]); \
67 67 mtlo3(tsk->thread.dsp.dspr[5]); \
68   - wrdsp(tsk->thread.dsp.dspcontrol, 0x2ff); \
  68 + wrdsp(tsk->thread.dsp.dspcontrol, DSP_MASK); \
69 69 } while (0)
70 70  
71 71 #define restore_dsp(tsk) \