Eric Lee / smarc-fsl-linux-kernel

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Commit 08cefa9fa7e5b3ddaefb8b7bfa408d148429c08d

Authored by David S. Miller
1 parent 1a8e0da593
Exists in master and in 38 other branches 8mp-imx_5.4.70_2.3.0, 8qm-imx_5.4.70_2.3.0, emb_imx_lf-5.15.y, emb_lf-6.1.y, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, imx_4.1.15_1.0.0_ga, pitx_8mp_lf-5.10.y, rt-smarc-imx_4.1.15_1.0.0_ga, rt_linux_5.15.71, smarc-8m-android-11.0.0_2.0.0, smarc-imx6_4.14.98_2.0.0_ga, smarc-imx6_4.9.88_2.0.0_ga, smarc-imx7_4.14.98_2.0.0_ga, smarc-imx7_4.9.11_1.0.0_ga, smarc-imx7_4.9.88_2.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-imx_4.1.15_1.0.0_ga, smarc-imx_4.9.11_1.0.0_ga, smarc-imx_4.9.51_imx8m_ga, smarc-imx_4.9.88_2.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_1.2.0_ga, smarc_8m_00d0_imx_4.14.98_2.0.0_ga, smarc_8m_imx_4.14.78_1.0.0_ga, smarc_8m_imx_4.14.98_2.0.0_ga, smarc_8m_imx_4.19.35_1.1.0, smarc_8mm_imx_4.14.78_1.0.0_ga, smarc_8mm_imx_4.14.98_2.0.0_ga, smarc_8mm_imx_4.19.35_1.1.0, smarc_8mm_imx_5.4.24_2.1.0, smarc_8mp_lf-5.10.y, smarc_8mq_imx_5.4.24_2.1.0, smarc_8mq_lf-5.10.y, smarc_imx_lf-5.15.y

sparc64: Future proof Niagara cpu detection. 

Recognize T4 and T5 chips.  Treating them both as "T2 plus other
stuff" should be extremely safe and make sure distributions will work
when those chips actually ship to customers.

Signed-off-by: David S. Miller <davem@davemloft.net>

Showing 6 changed files with 53 additions and 8 deletions Side-by-side Diff

arch/sparc/include/asm/spitfire.h
Diff comments   View file @ 08cefa9
... ... @@ -43,6 +43,8 @@
43 43 #define SUN4V_CHIP_NIAGARA1 0x01
44 44 #define SUN4V_CHIP_NIAGARA2 0x02
45 45 #define SUN4V_CHIP_NIAGARA3 0x03
  46 +#define SUN4V_CHIP_NIAGARA4 0x04
  47 +#define SUN4V_CHIP_NIAGARA5 0x05
46 48 #define SUN4V_CHIP_UNKNOWN 0xff
47 49  
48 50 #ifndef __ASSEMBLY__
arch/sparc/include/asm/xor_64.h
Diff comments   View file @ 08cefa9
... ... @@ -66,7 +66,9 @@
66 66 ((tlb_type == hypervisor && \
67 67 (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || \
68 68 sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || \
69   - sun4v_chip_type == SUN4V_CHIP_NIAGARA3)) ? \
  69 + sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || \
  70 + sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || \
  71 + sun4v_chip_type == SUN4V_CHIP_NIAGARA5)) ? \
70 72 &xor_block_niagara : \
71 73 &xor_block_VIS)
arch/sparc/kernel/cpu.c
Diff comments   View file @ 08cefa9
... ... @@ -481,6 +481,18 @@
481 481 sparc_pmu_type = "niagara3";
482 482 break;
483 483  
  484 + case SUN4V_CHIP_NIAGARA4:
  485 + sparc_cpu_type = "UltraSparc T4 (Niagara4)";
  486 + sparc_fpu_type = "UltraSparc T4 integrated FPU";
  487 + sparc_pmu_type = "niagara4";
  488 + break;
  489 +
  490 + case SUN4V_CHIP_NIAGARA5:
  491 + sparc_cpu_type = "UltraSparc T5 (Niagara5)";
  492 + sparc_fpu_type = "UltraSparc T5 integrated FPU";
  493 + sparc_pmu_type = "niagara5";
  494 + break;
  495 +
484 496 default:
485 497 printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n",
486 498 prom_cpu_compatible);
arch/sparc/kernel/cpumap.c
Diff comments   View file @ 08cefa9
... ... @@ -325,6 +325,8 @@
325 325 case SUN4V_CHIP_NIAGARA1:
326 326 case SUN4V_CHIP_NIAGARA2:
327 327 case SUN4V_CHIP_NIAGARA3:
  328 + case SUN4V_CHIP_NIAGARA4:
  329 + case SUN4V_CHIP_NIAGARA5:
328 330 rover_inc_table = niagara_iterate_method;
329 331 break;
330 332 default:
arch/sparc/kernel/head_64.S
Diff comments   View file @ 08cefa9
... ... @@ -133,7 +133,7 @@
133 133 prom_niagara_prefix:
134 134 .asciz "SUNW,UltraSPARC-T"
135 135 prom_sparc_prefix:
136   - .asciz "SPARC-T"
  136 + .asciz "SPARC-"
137 137 .align 4
138 138 prom_root_compatible:
139 139 .skip 64
... ... @@ -396,7 +396,7 @@
396 396 or %g1, %lo(prom_cpu_compatible), %g1
397 397 sethi %hi(prom_sparc_prefix), %g7
398 398 or %g7, %lo(prom_sparc_prefix), %g7
399   - mov 7, %g3
  399 + mov 6, %g3
400 400 90: ldub [%g7], %g2
401 401 ldub [%g1], %g4
402 402 cmp %g2, %g4
403 403  
... ... @@ -408,10 +408,23 @@
408 408  
409 409 sethi %hi(prom_cpu_compatible), %g1
410 410 or %g1, %lo(prom_cpu_compatible), %g1
411   - ldub [%g1 + 7], %g2
  411 + ldub [%g1 + 6], %g2
  412 + cmp %g2, 'T'
  413 + be,pt %xcc, 70f
  414 + cmp %g2, 'M'
  415 + bne,pn %xcc, 4f
  416 + nop
  417 +
  418 +70: ldub [%g1 + 7], %g2
412 419 cmp %g2, '3'
413 420 be,pt %xcc, 5f
414 421 mov SUN4V_CHIP_NIAGARA3, %g4
  422 + cmp %g2, '4'
  423 + be,pt %xcc, 5f
  424 + mov SUN4V_CHIP_NIAGARA4, %g4
  425 + cmp %g2, '5'
  426 + be,pt %xcc, 5f
  427 + mov SUN4V_CHIP_NIAGARA5, %g4
415 428 ba,pt %xcc, 4f
416 429 nop
417 430  
... ... @@ -543,6 +556,12 @@
543 556 be,pt %xcc, niagara2_patch
544 557 nop
545 558 cmp %g1, SUN4V_CHIP_NIAGARA3
  559 + be,pt %xcc, niagara2_patch
  560 + nop
  561 + cmp %g1, SUN4V_CHIP_NIAGARA4
  562 + be,pt %xcc, niagara2_patch
  563 + nop
  564 + cmp %g1, SUN4V_CHIP_NIAGARA5
546 565 be,pt %xcc, niagara2_patch
547 566 nop
548 567  
arch/sparc/kernel/setup_64.c
Diff comments   View file @ 08cefa9
... ... @@ -425,10 +425,14 @@
425 425 else if (tlb_type == hypervisor) {
426 426 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||
427 427 sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
428   - sun4v_chip_type == SUN4V_CHIP_NIAGARA3)
  428 + sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
  429 + sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
  430 + sun4v_chip_type == SUN4V_CHIP_NIAGARA5)
429 431 cap |= HWCAP_SPARC_BLKINIT;
430 432 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
431   - sun4v_chip_type == SUN4V_CHIP_NIAGARA3)
  433 + sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
  434 + sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
  435 + sun4v_chip_type == SUN4V_CHIP_NIAGARA5)
432 436 cap |= HWCAP_SPARC_N2;
433 437 }
434 438  
435 439  
... ... @@ -452,11 +456,15 @@
452 456 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1)
453 457 cap |= AV_SPARC_ASI_BLK_INIT;
454 458 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
455   - sun4v_chip_type == SUN4V_CHIP_NIAGARA3)
  459 + sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
  460 + sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
  461 + sun4v_chip_type == SUN4V_CHIP_NIAGARA5)
456 462 cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 |
457 463 AV_SPARC_ASI_BLK_INIT |
458 464 AV_SPARC_POPC);
459   - if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3)
  465 + if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
  466 + sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
  467 + sun4v_chip_type == SUN4V_CHIP_NIAGARA5)
460 468 cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC |
461 469 AV_SPARC_FMAF);
462 470 }