Merge tag 'ib-mfd-omap-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/le…

…e/mfd into omap-for-v3.16/pm Immutable branch between MFD and ARM OMAP due for v3.16 merge-window.

Merge tag 'ib-mfd-omap-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/le…
…e/mfd into omap-for-v3.16/pm Immutable branch between MFD and ARM OMAP due for v3.16 merge-window.
Tony Lindgren
2 parents 89ca3b8819 a613b739b8
Showing 2 changed files Side-by-side Diff
arch/arm/mach-omap2/omap_twl.c
drivers/mfd/twl-core.c
@@ -46,15 +46,8 @@
  
 static bool is_offset_valid;
 static u8 smps_offset;
-/*
- * Flag to ensure Smartreflex bit in TWL
- * being cleared in board file is not overwritten.
- */
-static bool __initdata twl_sr_enable_autoinit;
  
-#define TWL4030_DCDC_GLOBAL_CFG        0x06
 #define REG_SMPS_OFFSET         0xE0
-#define SMARTREFLEX_ENABLE     BIT(3)
  
 static unsigned long twl4030_vsel_to_uv(const u8 vsel)
 {
@@ -251,18 +244,6 @@
 	if (!cpu_is_omap34xx())
 		return -ENODEV;
  
-	/*
-	 * The smartreflex bit on twl4030 specifies if the setting of voltage
-	 * is done over the I2C_SR path. Since this setting is independent of
-	 * the actual usage of smartreflex AVS module, we enable TWL SR bit
-	 * by default irrespective of whether smartreflex AVS module is enabled
-	 * on the OMAP side or not. This is because without this bit enabled,
-	 * the voltage scaling through vp forceupdate/bypass mechanism of
-	 * voltage scaling will not function on TWL over I2C_SR.
-	 */
-	if (!twl_sr_enable_autoinit)
-		omap3_twl_set_sr_bit(true);
-
 	voltdm = voltdm_lookup("mpu_iva");
 	omap_voltage_register_pmic(voltdm, &omap3_mpu_pmic);
  
@@ -270,46 +251,5 @@
 	omap_voltage_register_pmic(voltdm, &omap3_core_pmic);
  
 	return 0;
-}
-
-/**
- * omap3_twl_set_sr_bit() - Set/Clear SR bit on TWL
- * @enable: enable SR mode in twl or not
- *
- * If 'enable' is true, enables Smartreflex bit on TWL 4030 to make sure
- * voltage scaling through OMAP SR works. Else, the smartreflex bit
- * on twl4030 is cleared as there are platforms which use OMAP3 and T2 but
- * use Synchronized Scaling Hardware Strategy (ENABLE_VMODE=1) and Direct
- * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages,
- * in those scenarios this bit is to be cleared (enable = false).
- *
- * Returns 0 on success, error is returned if I2C read/write fails.
- */
-int __init omap3_twl_set_sr_bit(bool enable)
-{
-	u8 temp;
-	int ret;
-	if (twl_sr_enable_autoinit)
-		pr_warning("%s: unexpected multiple calls\n", __func__);
-
-	ret = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &temp,
-			      TWL4030_DCDC_GLOBAL_CFG);
-	if (ret)
-		goto err;
-
-	if (enable)
-		temp |= SMARTREFLEX_ENABLE;
-	else
-		temp &= ~SMARTREFLEX_ENABLE;
-
-	ret = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, temp,
-			       TWL4030_DCDC_GLOBAL_CFG);
-	if (!ret) {
-		twl_sr_enable_autoinit = true;
-		return 0;
-	}
-err:
-	pr_err("%s: Error access to TWL4030 (%d)\n", __func__, ret);
-	return ret;
 }
@@ -98,7 +98,11 @@
 #define TWL4030_BASEADD_BACKUP		0x0014
 #define TWL4030_BASEADD_INT		0x002E
 #define TWL4030_BASEADD_PM_MASTER	0x0036
+
 #define TWL4030_BASEADD_PM_RECEIVER	0x005B
+#define TWL4030_DCDC_GLOBAL_CFG		0x06
+#define SMARTREFLEX_ENABLE		BIT(3)
+
 #define TWL4030_BASEADD_RTC		0x001C
 #define TWL4030_BASEADD_SECURED_REG	0x0000
  
@@ -1204,6 +1208,11 @@
 	 * Disable TWL4030/TWL5030 I2C Pull-up on I2C1 and I2C4(SR) interface.
 	 * Program I2C_SCL_CTRL_PU(bit 0)=0, I2C_SDA_CTRL_PU (bit 2)=0,
 	 * SR_I2C_SCL_CTRL_PU(bit 4)=0 and SR_I2C_SDA_CTRL_PU(bit 6)=0.
+	 *
+	 * Also, always enable SmartReflex bit as that's needed for omaps to
+	 * to do anything over I2C4 for voltage scaling even if SmartReflex
+	 * is disabled. Without the SmartReflex bit omap sys_clkreq idle
+	 * signal will never trigger for retention idle.
 	 */
 	if (twl_class_is_4030()) {
 		u8 temp;
@@ -1212,6 +1221,12 @@
 		temp &= ~(SR_I2C_SDA_CTRL_PU | SR_I2C_SCL_CTRL_PU | \
 			I2C_SDA_CTRL_PU | I2C_SCL_CTRL_PU);
 		twl_i2c_write_u8(TWL4030_MODULE_INTBR, temp, REG_GPPUPDCTR1);
+
+		twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &temp,
+				TWL4030_DCDC_GLOBAL_CFG);
+		temp |= SMARTREFLEX_ENABLE;
+		twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, temp,
+				 TWL4030_DCDC_GLOBAL_CFG);
 	}
  
 	if (node) {
...	...	@@ -46,15 +46,8 @@
46	46
47	47	static bool is_offset_valid;
48	48	static u8 smps_offset;
49		-/*
50		- * Flag to ensure Smartreflex bit in TWL
51		- * being cleared in board file is not overwritten.
52		- */
53		-static bool __initdata twl_sr_enable_autoinit;
54	49
55		-#define TWL4030_DCDC_GLOBAL_CFG 0x06
56	50	#define REG_SMPS_OFFSET 0xE0
57		-#define SMARTREFLEX_ENABLE BIT(3)
58	51
59	52	static unsigned long twl4030_vsel_to_uv(const u8 vsel)
60	53	{
...	...	@@ -251,18 +244,6 @@
251	244	if (!cpu_is_omap34xx())
252	245	return -ENODEV;
253	246
254		- /*
255		- * The smartreflex bit on twl4030 specifies if the setting of voltage
256		- * is done over the I2C_SR path. Since this setting is independent of
257		- * the actual usage of smartreflex AVS module, we enable TWL SR bit
258		- * by default irrespective of whether smartreflex AVS module is enabled
259		- * on the OMAP side or not. This is because without this bit enabled,
260		- * the voltage scaling through vp forceupdate/bypass mechanism of
261		- * voltage scaling will not function on TWL over I2C_SR.
262		- */
263		- if (!twl_sr_enable_autoinit)
264		- omap3_twl_set_sr_bit(true);
265		-
266	247	voltdm = voltdm_lookup("mpu_iva");
267	248	omap_voltage_register_pmic(voltdm, &omap3_mpu_pmic);
268	249
...	...	@@ -270,46 +251,5 @@
270	251	omap_voltage_register_pmic(voltdm, &omap3_core_pmic);
271	252
272	253	return 0;
273		-}
274		-
275		-/**
276		- * omap3_twl_set_sr_bit() - Set/Clear SR bit on TWL
277		- * @enable: enable SR mode in twl or not
278		- *
279		- * If 'enable' is true, enables Smartreflex bit on TWL 4030 to make sure
280		- * voltage scaling through OMAP SR works. Else, the smartreflex bit
281		- * on twl4030 is cleared as there are platforms which use OMAP3 and T2 but
282		- * use Synchronized Scaling Hardware Strategy (ENABLE_VMODE=1) and Direct
283		- * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages,
284		- * in those scenarios this bit is to be cleared (enable = false).
285		- *
286		- * Returns 0 on success, error is returned if I2C read/write fails.
287		- */
288		-int __init omap3_twl_set_sr_bit(bool enable)
289		-{
290		- u8 temp;
291		- int ret;
292		- if (twl_sr_enable_autoinit)
293		- pr_warning("%s: unexpected multiple calls\n", __func__);
294		-
295		- ret = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &temp,
296		- TWL4030_DCDC_GLOBAL_CFG);
297		- if (ret)
298		- goto err;
299		-
300		- if (enable)
301		- temp \|= SMARTREFLEX_ENABLE;
302		- else
303		- temp &= ~SMARTREFLEX_ENABLE;
304		-
305		- ret = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, temp,
306		- TWL4030_DCDC_GLOBAL_CFG);
307		- if (!ret) {
308		- twl_sr_enable_autoinit = true;
309		- return 0;
310		- }
311		-err:
312		- pr_err("%s: Error access to TWL4030 (%d)\n", __func__, ret);
313		- return ret;
314	254	}
...	...	@@ -98,7 +98,11 @@
98	98	#define TWL4030_BASEADD_BACKUP 0x0014
99	99	#define TWL4030_BASEADD_INT 0x002E
100	100	#define TWL4030_BASEADD_PM_MASTER 0x0036
	101	+
101	102	#define TWL4030_BASEADD_PM_RECEIVER 0x005B
	103	+#define TWL4030_DCDC_GLOBAL_CFG 0x06
	104	+#define SMARTREFLEX_ENABLE BIT(3)
	105	+
102	106	#define TWL4030_BASEADD_RTC 0x001C
103	107	#define TWL4030_BASEADD_SECURED_REG 0x0000
104	108
...	...	@@ -1204,6 +1208,11 @@
1204	1208	* Disable TWL4030/TWL5030 I2C Pull-up on I2C1 and I2C4(SR) interface.
1205	1209	* Program I2C_SCL_CTRL_PU(bit 0)=0, I2C_SDA_CTRL_PU (bit 2)=0,
1206	1210	* SR_I2C_SCL_CTRL_PU(bit 4)=0 and SR_I2C_SDA_CTRL_PU(bit 6)=0.
	1211	+ *
	1212	+ * Also, always enable SmartReflex bit as that's needed for omaps to
	1213	+ * to do anything over I2C4 for voltage scaling even if SmartReflex
	1214	+ * is disabled. Without the SmartReflex bit omap sys_clkreq idle
	1215	+ * signal will never trigger for retention idle.
1207	1216	*/
1208	1217	if (twl_class_is_4030()) {
1209	1218	u8 temp;
...	...	@@ -1212,6 +1221,12 @@
1212	1221	temp &= ~(SR_I2C_SDA_CTRL_PU \| SR_I2C_SCL_CTRL_PU \| \
1213	1222	I2C_SDA_CTRL_PU \| I2C_SCL_CTRL_PU);
1214	1223	twl_i2c_write_u8(TWL4030_MODULE_INTBR, temp, REG_GPPUPDCTR1);
	1224	+
	1225	+ twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &temp,
	1226	+ TWL4030_DCDC_GLOBAL_CFG);
	1227	+ temp \|= SMARTREFLEX_ENABLE;
	1228	+ twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, temp,
	1229	+ TWL4030_DCDC_GLOBAL_CFG);
1215	1230	}
1216	1231
1217	1232	if (node) {