Commit 0c30e0d31b57375b1decad4cc0e139e2f7758986

Authored by Sandeep Paulraj
Committed by Kevin Hilman
1 parent 1aebb50e06

DaVinci: DM365: Adding entries for DM365 IRQ's

This patch adds definitions for some DM365 IRQs that are used by
the codecs. Codecs will also use the IRQs.
Entries are being added to enable/disable IRQ's.
There is no use as such for these entires in the kernel itself.
Instead these will be used by the "linuxutils" package of the DVSDK.

For further information on IRQ muxing refer to
http://focus.ti.com/lit/ug/sprufg5a/sprufg5a.pdf

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sneha Narnakaje <nsnehaprabha@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>

Showing 3 changed files with 19 additions and 0 deletions Side-by-side Diff

arch/arm/mach-davinci/dm365.c
... ... @@ -595,6 +595,14 @@
595 595 INT_CFG(DM365, INT_EMAC_RXPULSE, 15, 1, 1, false)
596 596 INT_CFG(DM365, INT_EMAC_TXPULSE, 16, 1, 1, false)
597 597 INT_CFG(DM365, INT_EMAC_MISCPULSE, 17, 1, 1, false)
  598 +INT_CFG(DM365, INT_IMX0_ENABLE, 0, 1, 0, false)
  599 +INT_CFG(DM365, INT_IMX0_DISABLE, 0, 1, 1, false)
  600 +INT_CFG(DM365, INT_HDVICP_ENABLE, 0, 1, 1, false)
  601 +INT_CFG(DM365, INT_HDVICP_DISABLE, 0, 1, 0, false)
  602 +INT_CFG(DM365, INT_IMX1_ENABLE, 24, 1, 1, false)
  603 +INT_CFG(DM365, INT_IMX1_DISABLE, 24, 1, 0, false)
  604 +INT_CFG(DM365, INT_NSF_ENABLE, 25, 1, 1, false)
  605 +INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false)
598 606 #endif
599 607 };
600 608  
arch/arm/mach-davinci/include/mach/irqs.h
... ... @@ -205,6 +205,9 @@
205 205  
206 206 /* DaVinci DM365-specific Interrupts */
207 207 #define IRQ_DM365_INSFINT 7
  208 +#define IRQ_DM365_IMXINT1 8
  209 +#define IRQ_DM365_IMXINT0 10
  210 +#define IRQ_DM365_KLD_ARMINT 10
208 211 #define IRQ_DM365_IMCOPINT 11
209 212 #define IRQ_DM365_RTOINT 13
210 213 #define IRQ_DM365_TINT5 14
arch/arm/mach-davinci/include/mach/mux.h
... ... @@ -301,6 +301,14 @@
301 301 DM365_INT_EMAC_RXPULSE,
302 302 DM365_INT_EMAC_TXPULSE,
303 303 DM365_INT_EMAC_MISCPULSE,
  304 + DM365_INT_IMX0_ENABLE,
  305 + DM365_INT_IMX0_DISABLE,
  306 + DM365_INT_HDVICP_ENABLE,
  307 + DM365_INT_HDVICP_DISABLE,
  308 + DM365_INT_IMX1_ENABLE,
  309 + DM365_INT_IMX1_DISABLE,
  310 + DM365_INT_NSF_ENABLE,
  311 + DM365_INT_NSF_DISABLE,
304 312  
305 313 /* EDMA event muxing */
306 314 DM365_EVT2_ASP_TX,