Commit 0cbefeb28cebb3bc2a22912da7ff3d50c924aac9

Authored by Liu Ying
1 parent a7fcc0edd4

MLK-21269 drm/imx: dpu: crtc: Wait for FG moving after tcon mode switch for non-PC cases

Due to TKT320590, we are asked to turn TCON into operation mode later after
the first dumb frame is generated by DPU.  This makes DPR/PRG be able to
evade the frame.  However, it turns out we have to set the TCON into operation
mode first and then wait for Framegen frame counter moving, otherwise, the
display pipeline cannot be setup correctly sometimes(If pixel combiner is used,
one of the two display streams is likely broken).  This is a mysterious issue.
So, we've already taken a workaround for the cases where pixel combiner is used.

It appears that the similar issue is likely to happen for cases where pixel
combiner is unused.  That is to say, if pixel combiner is unused and prefetch
engine is used, the first atomic flush after the enablement is likely to fail -
content shadow load irq doesn't come.  The sequence which the patch takes is
the same to the one taken by the previous workaround.  Based on tests, it is
valid for cases with or without pixel combiner.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit b6126aa9697c77896d2085997eec2a6995509f4b)

Showing 1 changed file with 8 additions and 6 deletions Side-by-side Diff

drivers/gpu/drm/imx/dpu/dpu-crtc.c
... ... @@ -215,11 +215,13 @@
215 215 * TKT320590:
216 216 * Turn TCON into operation mode later after the first dumb frame is
217 217 * generated by DPU. This makes DPR/PRG be able to evade the frame.
218   - * However, if pixel combiner is used, it turns out we have to set
219   - * the TCON into operation mode first and then wait for Framegen
220   - * frame counter moving, otherwise, the display pipeline cannot be
221   - * setup correctly sometimes(one of the two display streams would
222   - * be broken). This is a mysterious issue.
  218 + * However, it turns out we have to set the TCON into operation mode
  219 + * first and then wait for Framegen frame counter moving, otherwise,
  220 + * the display pipeline is likely to broken(If pixel combiner is used,
  221 + * one of the two display streams cannot be setup correctly sometimes.
  222 + * If pixel combiner is unused and prefetch engine is used, the first
  223 + * atomic flush after the enablement is likely to fail - content shadow
  224 + * load irq doesn't come.). This is a mysterious issue.
223 225 */
224 226 if (dcstate->use_pc) {
225 227 tcon_set_operation_mode(dpu_crtc->m_tcon);
226 228  
... ... @@ -241,8 +243,8 @@
241 243 "enable - slave FrameGen requests to read empty FIFO\n");
242 244 }
243 245 } else {
244   - framegen_wait_for_frame_counter_moving(dpu_crtc->fg);
245 246 tcon_set_operation_mode(dpu_crtc->tcon);
  247 + framegen_wait_for_frame_counter_moving(dpu_crtc->fg);
246 248  
247 249 framegen_wait_for_secondary_syncup(dpu_crtc->fg);
248 250