Eric Lee / smarc-fsl-linux-kernel

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Commit 0dba4dc4d0bf2bd469b1ae7eae0a6ab26624bfe9

Authored by Jongpill Lee
Committed by Kukjin Kim
1 parent 0513218222

ARM: EXYNOS4: Modify PMU register setting function 

This patch modifies PMU register setting function
to support the other EXYNOS4 SoCs.

Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

Showing 3 changed files with 96 additions and 151 deletions Side-by-side Diff

arch/arm/mach-exynos4/include/mach/pmu.h
Diff comments   View file @ 0dba4dc
... ... @@ -13,11 +13,18 @@
13 13 #ifndef __ASM_ARCH_PMU_H
14 14 #define __ASM_ARCH_PMU_H __FILE__
15 15  
  16 +#define PMU_TABLE_END NULL
  17 +
16 18 enum sys_powerdown {
17 19 SYS_AFTR,
18 20 SYS_LPA,
19 21 SYS_SLEEP,
20 22 NUM_SYS_POWERDOWN,
  23 +};
  24 +
  25 +struct exynos4_pmu_conf {
  26 + void __iomem *reg;
  27 + unsigned int val[NUM_SYS_POWERDOWN];
21 28 };
22 29  
23 30 extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
arch/arm/mach-exynos4/include/mach/regs-pmu.h
Diff comments   View file @ 0dba4dc
... ... @@ -27,7 +27,6 @@
27 27 #define S5P_USE_STANDBY_WFI1 (1 << 17)
28 28 #define S5P_USE_STANDBY_WFE0 (1 << 24)
29 29 #define S5P_USE_STANDBY_WFE1 (1 << 25)
30   -#define S5P_USE_MASK ((0x3 << 16) | (0x3 << 24))
31 30  
32 31 #define S5P_SWRESET S5P_PMUREG(0x0400)
33 32  
arch/arm/mach-exynos4/pmu.c
Diff comments   View file @ 0dba4dc
... ... @@ -16,161 +16,100 @@
16 16 #include <mach/regs-clock.h>
17 17 #include <mach/pmu.h>
18 18  
19   -static void __iomem *sys_powerdown_reg[] = {
20   - S5P_ARM_CORE0_LOWPWR,
21   - S5P_DIS_IRQ_CORE0,
22   - S5P_DIS_IRQ_CENTRAL0,
23   - S5P_ARM_CORE1_LOWPWR,
24   - S5P_DIS_IRQ_CORE1,
25   - S5P_DIS_IRQ_CENTRAL1,
26   - S5P_ARM_COMMON_LOWPWR,
27   - S5P_L2_0_LOWPWR,
28   - S5P_L2_1_LOWPWR,
29   - S5P_CMU_ACLKSTOP_LOWPWR,
30   - S5P_CMU_SCLKSTOP_LOWPWR,
31   - S5P_CMU_RESET_LOWPWR,
32   - S5P_APLL_SYSCLK_LOWPWR,
33   - S5P_MPLL_SYSCLK_LOWPWR,
34   - S5P_VPLL_SYSCLK_LOWPWR,
35   - S5P_EPLL_SYSCLK_LOWPWR,
36   - S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR,
37   - S5P_CMU_RESET_GPSALIVE_LOWPWR,
38   - S5P_CMU_CLKSTOP_CAM_LOWPWR,
39   - S5P_CMU_CLKSTOP_TV_LOWPWR,
40   - S5P_CMU_CLKSTOP_MFC_LOWPWR,
41   - S5P_CMU_CLKSTOP_G3D_LOWPWR,
42   - S5P_CMU_CLKSTOP_LCD0_LOWPWR,
43   - S5P_CMU_CLKSTOP_LCD1_LOWPWR,
44   - S5P_CMU_CLKSTOP_MAUDIO_LOWPWR,
45   - S5P_CMU_CLKSTOP_GPS_LOWPWR,
46   - S5P_CMU_RESET_CAM_LOWPWR,
47   - S5P_CMU_RESET_TV_LOWPWR,
48   - S5P_CMU_RESET_MFC_LOWPWR,
49   - S5P_CMU_RESET_G3D_LOWPWR,
50   - S5P_CMU_RESET_LCD0_LOWPWR,
51   - S5P_CMU_RESET_LCD1_LOWPWR,
52   - S5P_CMU_RESET_MAUDIO_LOWPWR,
53   - S5P_CMU_RESET_GPS_LOWPWR,
54   - S5P_TOP_BUS_LOWPWR,
55   - S5P_TOP_RETENTION_LOWPWR,
56   - S5P_TOP_PWR_LOWPWR,
57   - S5P_LOGIC_RESET_LOWPWR,
58   - S5P_ONENAND_MEM_LOWPWR,
59   - S5P_MODIMIF_MEM_LOWPWR,
60   - S5P_G2D_ACP_MEM_LOWPWR,
61   - S5P_USBOTG_MEM_LOWPWR,
62   - S5P_HSMMC_MEM_LOWPWR,
63   - S5P_CSSYS_MEM_LOWPWR,
64   - S5P_SECSS_MEM_LOWPWR,
65   - S5P_PCIE_MEM_LOWPWR,
66   - S5P_SATA_MEM_LOWPWR,
67   - S5P_PAD_RETENTION_DRAM_LOWPWR,
68   - S5P_PAD_RETENTION_MAUDIO_LOWPWR,
69   - S5P_PAD_RETENTION_GPIO_LOWPWR,
70   - S5P_PAD_RETENTION_UART_LOWPWR,
71   - S5P_PAD_RETENTION_MMCA_LOWPWR,
72   - S5P_PAD_RETENTION_MMCB_LOWPWR,
73   - S5P_PAD_RETENTION_EBIA_LOWPWR,
74   - S5P_PAD_RETENTION_EBIB_LOWPWR,
75   - S5P_PAD_RETENTION_ISOLATION_LOWPWR,
76   - S5P_PAD_RETENTION_ALV_SEL_LOWPWR,
77   - S5P_XUSBXTI_LOWPWR,
78   - S5P_XXTI_LOWPWR,
79   - S5P_EXT_REGULATOR_LOWPWR,
80   - S5P_GPIO_MODE_LOWPWR,
81   - S5P_GPIO_MODE_MAUDIO_LOWPWR,
82   - S5P_CAM_LOWPWR,
83   - S5P_TV_LOWPWR,
84   - S5P_MFC_LOWPWR,
85   - S5P_G3D_LOWPWR,
86   - S5P_LCD0_LOWPWR,
87   - S5P_LCD1_LOWPWR,
88   - S5P_MAUDIO_LOWPWR,
89   - S5P_GPS_LOWPWR,
90   - S5P_GPS_ALIVE_LOWPWR,
91   -};
  19 +static struct exynos4_pmu_conf *exynos4_pmu_config;
92 20  
93   -static const unsigned int sys_powerdown_val[][NUM_SYS_POWERDOWN] = {
94   - /* { AFTR, LPA, SLEEP }*/
95   - { 0, 0, 2 }, /* ARM_CORE0 */
96   - { 0, 0, 0 }, /* ARM_DIS_IRQ_CORE0 */
97   - { 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL0 */
98   - { 0, 0, 2 }, /* ARM_CORE1 */
99   - { 0, 0, 0 }, /* ARM_DIS_IRQ_CORE1 */
100   - { 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL1 */
101   - { 0, 0, 2 }, /* ARM_COMMON */
102   - { 2, 2, 3 }, /* ARM_CPU_L2_0 */
103   - { 2, 2, 3 }, /* ARM_CPU_L2_1 */
104   - { 1, 0, 0 }, /* CMU_ACLKSTOP */
105   - { 1, 0, 0 }, /* CMU_SCLKSTOP */
106   - { 1, 1, 0 }, /* CMU_RESET */
107   - { 1, 0, 0 }, /* APLL_SYSCLK */
108   - { 1, 0, 0 }, /* MPLL_SYSCLK */
109   - { 1, 0, 0 }, /* VPLL_SYSCLK */
110   - { 1, 1, 0 }, /* EPLL_SYSCLK */
111   - { 1, 1, 0 }, /* CMU_CLKSTOP_GPS_ALIVE */
112   - { 1, 1, 0 }, /* CMU_RESET_GPS_ALIVE */
113   - { 1, 1, 0 }, /* CMU_CLKSTOP_CAM */
114   - { 1, 1, 0 }, /* CMU_CLKSTOP_TV */
115   - { 1, 1, 0 }, /* CMU_CLKSTOP_MFC */
116   - { 1, 1, 0 }, /* CMU_CLKSTOP_G3D */
117   - { 1, 1, 0 }, /* CMU_CLKSTOP_LCD0 */
118   - { 1, 1, 0 }, /* CMU_CLKSTOP_LCD1 */
119   - { 1, 1, 0 }, /* CMU_CLKSTOP_MAUDIO */
120   - { 1, 1, 0 }, /* CMU_CLKSTOP_GPS */
121   - { 1, 1, 0 }, /* CMU_RESET_CAM */
122   - { 1, 1, 0 }, /* CMU_RESET_TV */
123   - { 1, 1, 0 }, /* CMU_RESET_MFC */
124   - { 1, 1, 0 }, /* CMU_RESET_G3D */
125   - { 1, 1, 0 }, /* CMU_RESET_LCD0 */
126   - { 1, 1, 0 }, /* CMU_RESET_LCD1 */
127   - { 1, 1, 0 }, /* CMU_RESET_MAUDIO */
128   - { 1, 1, 0 }, /* CMU_RESET_GPS */
129   - { 3, 0, 0 }, /* TOP_BUS */
130   - { 1, 0, 1 }, /* TOP_RETENTION */
131   - { 3, 0, 3 }, /* TOP_PWR */
132   - { 1, 1, 0 }, /* LOGIC_RESET */
133   - { 3, 0, 0 }, /* ONENAND_MEM */
134   - { 3, 0, 0 }, /* MODIMIF_MEM */
135   - { 3, 0, 0 }, /* G2D_ACP_MEM */
136   - { 3, 0, 0 }, /* USBOTG_MEM */
137   - { 3, 0, 0 }, /* HSMMC_MEM */
138   - { 3, 0, 0 }, /* CSSYS_MEM */
139   - { 3, 0, 0 }, /* SECSS_MEM */
140   - { 3, 0, 0 }, /* PCIE_MEM */
141   - { 3, 0, 0 }, /* SATA_MEM */
142   - { 1, 0, 0 }, /* PAD_RETENTION_DRAM */
143   - { 1, 1, 0 }, /* PAD_RETENTION_MAUDIO */
144   - { 1, 0, 0 }, /* PAD_RETENTION_GPIO */
145   - { 1, 0, 0 }, /* PAD_RETENTION_UART */
146   - { 1, 0, 0 }, /* PAD_RETENTION_MMCA */
147   - { 1, 0, 0 }, /* PAD_RETENTION_MMCB */
148   - { 1, 0, 0 }, /* PAD_RETENTION_EBIA */
149   - { 1, 0, 0 }, /* PAD_RETENTION_EBIB */
150   - { 1, 0, 0 }, /* PAD_RETENTION_ISOLATION */
151   - { 1, 0, 0 }, /* PAD_RETENTION_ALV_SEL */
152   - { 1, 1, 0 }, /* XUSBXTI */
153   - { 1, 1, 0 }, /* XXTI */
154   - { 1, 1, 0 }, /* EXT_REGULATOR */
155   - { 1, 0, 0 }, /* GPIO_MODE */
156   - { 1, 1, 0 }, /* GPIO_MODE_MAUDIO */
157   - { 7, 0, 0 }, /* CAM */
158   - { 7, 0, 0 }, /* TV */
159   - { 7, 0, 0 }, /* MFC */
160   - { 7, 0, 0 }, /* G3D */
161   - { 7, 0, 0 }, /* LCD0 */
162   - { 7, 0, 0 }, /* LCD1 */
163   - { 7, 7, 0 }, /* MAUDIO */
164   - { 7, 0, 0 }, /* GPS */
165   - { 7, 0, 0 }, /* GPS_ALIVE */
  21 +static struct exynos4_pmu_conf exynos4210_pmu_config[] = {
  22 + /* { .reg = address, .val = { AFTR, LPA, SLEEP } */
  23 + { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
  24 + { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
  25 + { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
  26 + { S5P_ARM_CORE1_LOWPWR, { 0x0, 0x0, 0x2 } },
  27 + { S5P_DIS_IRQ_CORE1, { 0x0, 0x0, 0x0 } },
  28 + { S5P_DIS_IRQ_CENTRAL1, { 0x0, 0x0, 0x0 } },
  29 + { S5P_ARM_COMMON_LOWPWR, { 0x0, 0x0, 0x2 } },
  30 + { S5P_L2_0_LOWPWR, { 0x2, 0x2, 0x3 } },
  31 + { S5P_L2_1_LOWPWR, { 0x2, 0x2, 0x3 } },
  32 + { S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
  33 + { S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
  34 + { S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
  35 + { S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
  36 + { S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
  37 + { S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
  38 + { S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } },
  39 + { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x1, 0x0 } },
  40 + { S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x1, 0x0 } },
  41 + { S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x1, 0x0 } },
  42 + { S5P_CMU_CLKSTOP_TV_LOWPWR, { 0x1, 0x1, 0x0 } },
  43 + { S5P_CMU_CLKSTOP_MFC_LOWPWR, { 0x1, 0x1, 0x0 } },
  44 + { S5P_CMU_CLKSTOP_G3D_LOWPWR, { 0x1, 0x1, 0x0 } },
  45 + { S5P_CMU_CLKSTOP_LCD0_LOWPWR, { 0x1, 0x1, 0x0 } },
  46 + { S5P_CMU_CLKSTOP_LCD1_LOWPWR, { 0x1, 0x1, 0x0 } },
  47 + { S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
  48 + { S5P_CMU_CLKSTOP_GPS_LOWPWR, { 0x1, 0x1, 0x0 } },
  49 + { S5P_CMU_RESET_CAM_LOWPWR, { 0x1, 0x1, 0x0 } },
  50 + { S5P_CMU_RESET_TV_LOWPWR, { 0x1, 0x1, 0x0 } },
  51 + { S5P_CMU_RESET_MFC_LOWPWR, { 0x1, 0x1, 0x0 } },
  52 + { S5P_CMU_RESET_G3D_LOWPWR, { 0x1, 0x1, 0x0 } },
  53 + { S5P_CMU_RESET_LCD0_LOWPWR, { 0x1, 0x1, 0x0 } },
  54 + { S5P_CMU_RESET_LCD1_LOWPWR, { 0x1, 0x1, 0x0 } },
  55 + { S5P_CMU_RESET_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
  56 + { S5P_CMU_RESET_GPS_LOWPWR, { 0x1, 0x1, 0x0 } },
  57 + { S5P_TOP_BUS_LOWPWR, { 0x3, 0x0, 0x0 } },
  58 + { S5P_TOP_RETENTION_LOWPWR, { 0x1, 0x0, 0x1 } },
  59 + { S5P_TOP_PWR_LOWPWR, { 0x3, 0x0, 0x3 } },
  60 + { S5P_LOGIC_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
  61 + { S5P_ONENAND_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
  62 + { S5P_MODIMIF_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
  63 + { S5P_G2D_ACP_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
  64 + { S5P_USBOTG_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
  65 + { S5P_HSMMC_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
  66 + { S5P_CSSYS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
  67 + { S5P_SECSS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
  68 + { S5P_PCIE_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
  69 + { S5P_SATA_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
  70 + { S5P_PAD_RETENTION_DRAM_LOWPWR, { 0x1, 0x0, 0x0 } },
  71 + { S5P_PAD_RETENTION_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
  72 + { S5P_PAD_RETENTION_GPIO_LOWPWR, { 0x1, 0x0, 0x0 } },
  73 + { S5P_PAD_RETENTION_UART_LOWPWR, { 0x1, 0x0, 0x0 } },
  74 + { S5P_PAD_RETENTION_MMCA_LOWPWR, { 0x1, 0x0, 0x0 } },
  75 + { S5P_PAD_RETENTION_MMCB_LOWPWR, { 0x1, 0x0, 0x0 } },
  76 + { S5P_PAD_RETENTION_EBIA_LOWPWR, { 0x1, 0x0, 0x0 } },
  77 + { S5P_PAD_RETENTION_EBIB_LOWPWR, { 0x1, 0x0, 0x0 } },
  78 + { S5P_PAD_RETENTION_ISOLATION_LOWPWR, { 0x1, 0x0, 0x0 } },
  79 + { S5P_PAD_RETENTION_ALV_SEL_LOWPWR, { 0x1, 0x0, 0x0 } },
  80 + { S5P_XUSBXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
  81 + { S5P_XXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
  82 + { S5P_EXT_REGULATOR_LOWPWR, { 0x1, 0x1, 0x0 } },
  83 + { S5P_GPIO_MODE_LOWPWR, { 0x1, 0x0, 0x0 } },
  84 + { S5P_GPIO_MODE_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
  85 + { S5P_CAM_LOWPWR, { 0x7, 0x0, 0x0 } },
  86 + { S5P_TV_LOWPWR, { 0x7, 0x0, 0x0 } },
  87 + { S5P_MFC_LOWPWR, { 0x7, 0x0, 0x0 } },
  88 + { S5P_G3D_LOWPWR, { 0x7, 0x0, 0x0 } },
  89 + { S5P_LCD0_LOWPWR, { 0x7, 0x0, 0x0 } },
  90 + { S5P_LCD1_LOWPWR, { 0x7, 0x0, 0x0 } },
  91 + { S5P_MAUDIO_LOWPWR, { 0x7, 0x7, 0x0 } },
  92 + { S5P_GPS_LOWPWR, { 0x7, 0x0, 0x0 } },
  93 + { S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } },
  94 + { PMU_TABLE_END,},
166 95 };
167 96  
168 97 void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
169 98 {
170   - unsigned int count = ARRAY_SIZE(sys_powerdown_reg);
  99 + unsigned int i;
171 100  
172   - for (; count > 0; count--)
173   - __raw_writel(sys_powerdown_val[count - 1][mode],
174   - sys_powerdown_reg[count - 1]);
  101 + for (i = 0; (exynos4_pmu_config[i].reg != PMU_TABLE_END) ; i++)
  102 + __raw_writel(exynos4_pmu_config[i].val[mode],
  103 + exynos4_pmu_config[i].reg);
175 104 }
  105 +
  106 +static int __init exynos4_pmu_init(void)
  107 +{
  108 + exynos4_pmu_config = exynos4210_pmu_config;
  109 +
  110 + pr_info("EXYNOS4210 PMU Initialize\n");
  111 +
  112 + return 0;
  113 +}
  114 +arch_initcall(exynos4_pmu_init);