Eric Lee / smarc-fsl-linux-kernel

Commit 0f7b332f9777819a39a3b325690379a7efef89d1

Authored by Russell King 14 years ago

Exists in master and in 39 other branches

ARM: consolidate SMP cross call implementation

Rather than having each platform class provide a mach/smp.h header for
smp_cross_call(), arrange for them to register the function with the
core ARM SMP code instead.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Showing 19 changed files with 37 additions and 162 deletions Inline Diff

arch/arm/include/asm/smp.h
arch/arm/kernel/smp.c
arch/arm/mach-exynos4/include/mach/smp.h
arch/arm/mach-exynos4/platsmp.c
arch/arm/mach-msm/include/mach/smp.h
arch/arm/mach-msm/platsmp.c
arch/arm/mach-omap2/omap-smp.c
arch/arm/mach-realview/include/mach/smp.h
arch/arm/mach-realview/platsmp.c
arch/arm/mach-shmobile/include/mach/smp.h
arch/arm/mach-shmobile/platsmp.c
arch/arm/mach-tegra/include/mach/smp.h
arch/arm/mach-tegra/platsmp.c
arch/arm/mach-ux500/include/mach/smp.h
arch/arm/mach-ux500/platsmp.c
arch/arm/mach-vexpress/ct-ca9x4.c
arch/arm/mach-vexpress/include/mach/smp.h
arch/arm/plat-omap/include/plat/smp.h
arch/arm/plat-versatile/platsmp.c

arch/arm/include/asm/smp.h

Diff comments View file @ 0f7b332

 /*
  *  arch/arm/include/asm/smp.h
  *
  *  Copyright (C) 2004-2005 ARM Ltd.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 #ifndef __ASM_ARM_SMP_H
 #define __ASM_ARM_SMP_H
 #include <linux/threads.h>
 #include <linux/cpumask.h>
 #include <linux/thread_info.h>
-#include <mach/smp.h>
 #ifndef CONFIG_SMP
 # error "<asm/smp.h> included in non-SMP build"
 #endif
 #define raw_smp_processor_id() (current_thread_info()->cpu)
 /*
  * at the moment, there's not a big penalty for changing CPUs
  * (the >big< penalty is running SMP in the first place)
  */
 #define PROC_CHANGE_PENALTY		15
 struct seq_file;
 /*
  * generate IPI list text
  */
 extern void show_ipi_list(struct seq_file *, int);
 /*
  * Called from assembly code, this handles an IPI.
  */
 asmlinkage void do_IPI(int ipinr, struct pt_regs *regs);
 /*
  * Setup the set of possible CPUs (via set_cpu_possible)
  */
 extern void smp_init_cpus(void);
 /*
- * Raise an IPI cross call on CPUs in callmap.
+ * Provide a function to raise an IPI cross call on CPUs in callmap.
  */
-extern void smp_cross_call(const struct cpumask *mask, int ipi);
+extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned int));
 /*
  * Boot a secondary CPU, and assign it the specified idle task.
  * This also gives us the initial stack to use for this CPU.
  */
 extern int boot_secondary(unsigned int cpu, struct task_struct *);
 /*
  * Called from platform specific assembly code, this is the
  * secondary CPU entry point.
  */
 asmlinkage void secondary_start_kernel(void);
 /*
  * Perform platform specific initialisation of the specified CPU.
  */
 extern void platform_secondary_init(unsigned int cpu);
 /*
  * Initialize cpu_possible map, and enable coherency
  */
 extern void platform_smp_prepare_cpus(unsigned int);
 /*
  * Initial data for bringing up a secondary CPU.
  */
 struct secondary_data {
 	unsigned long pgdir;
 	void *stack;
 };
 extern struct secondary_data secondary_data;
 extern int __cpu_disable(void);
 extern int platform_cpu_disable(unsigned int cpu);
 extern void __cpu_die(unsigned int cpu);
 extern void cpu_die(void);
 extern void platform_cpu_die(unsigned int cpu);
 extern int platform_cpu_kill(unsigned int cpu);
 extern void platform_cpu_enable(unsigned int cpu);
 extern void arch_send_call_function_single_ipi(int cpu);
 extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
 /*
  * show local interrupt info
  */
 extern void show_local_irqs(struct seq_file *, int);
 #endif /* ifndef __ASM_ARM_SMP_H */

arch/arm/kernel/smp.c

Diff comments View file @ 0f7b332

 /*
  *  linux/arch/arm/kernel/smp.c
  *
  *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 #include <linux/module.h>
 #include <linux/delay.h>
 #include <linux/init.h>
 #include <linux/spinlock.h>
 #include <linux/sched.h>
 #include <linux/interrupt.h>
 #include <linux/cache.h>
 #include <linux/profile.h>
 #include <linux/errno.h>
 #include <linux/ftrace.h>
 #include <linux/mm.h>
 #include <linux/err.h>
 #include <linux/cpu.h>
 #include <linux/smp.h>
 #include <linux/seq_file.h>
 #include <linux/irq.h>
 #include <linux/percpu.h>
 #include <linux/clockchips.h>
 #include <linux/completion.h>
 #include <asm/atomic.h>
 #include <asm/cacheflush.h>
 #include <asm/cpu.h>
 #include <asm/cputype.h>
 #include <asm/mmu_context.h>
 #include <asm/pgtable.h>
 #include <asm/pgalloc.h>
 #include <asm/processor.h>
 #include <asm/sections.h>
 #include <asm/tlbflush.h>
 #include <asm/ptrace.h>
 #include <asm/localtimer.h>
 /*
  * as from 2.5, kernels no longer have an init_tasks structure
  * so we need some other way of telling a new secondary core
  * where to place its SVC stack
  */
 struct secondary_data secondary_data;
 enum ipi_msg_type {
 	IPI_TIMER = 2,
 	IPI_RESCHEDULE,
 	IPI_CALL_FUNC,
 	IPI_CALL_FUNC_SINGLE,
 	IPI_CPU_STOP,
 };
 int __cpuinit __cpu_up(unsigned int cpu)
 {
 	struct cpuinfo_arm *ci = &per_cpu(cpu_data, cpu);
 	struct task_struct *idle = ci->idle;
 	pgd_t *pgd;
 	int ret;
 	/*
 	 * Spawn a new process manually, if not already done.
 	 * Grab a pointer to its task struct so we can mess with it
 	 */
 	if (!idle) {
 		idle = fork_idle(cpu);
 		if (IS_ERR(idle)) {
 			printk(KERN_ERR "CPU%u: fork() failed\n", cpu);
 			return PTR_ERR(idle);
 		}
 		ci->idle = idle;
 	} else {
 		/*
 		 * Since this idle thread is being re-used, call
 		 * init_idle() to reinitialize the thread structure.
 		 */
 		init_idle(idle, cpu);
 	}
 	/*
 	 * Allocate initial page tables to allow the new CPU to
 	 * enable the MMU safely.  This essentially means a set
 	 * of our "standard" page tables, with the addition of
 	 * a 1:1 mapping for the physical address of the kernel.
 	 */
 	pgd = pgd_alloc(&init_mm);
 	if (!pgd)
 		return -ENOMEM;
 	if (PHYS_OFFSET != PAGE_OFFSET) {
 #ifndef CONFIG_HOTPLUG_CPU
 		identity_mapping_add(pgd, __pa(__init_begin), __pa(__init_end));
 #endif
 		identity_mapping_add(pgd, __pa(_stext), __pa(_etext));
 		identity_mapping_add(pgd, __pa(_sdata), __pa(_edata));
 	}
 	/*
 	 * We need to tell the secondary core where to find
 	 * its stack and the page tables.
 	 */
 	secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
 	secondary_data.pgdir = virt_to_phys(pgd);
 	__cpuc_flush_dcache_area(&secondary_data, sizeof(secondary_data));
 	outer_clean_range(__pa(&secondary_data), __pa(&secondary_data + 1));
 	/*
 	 * Now bring the CPU into our world.
 	 */
 	ret = boot_secondary(cpu, idle);
 	if (ret == 0) {
 		unsigned long timeout;
 		/*
 		 * CPU was successfully started, wait for it
 		 * to come online or time out.
 		 */
 		timeout = jiffies + HZ;
 		while (time_before(jiffies, timeout)) {
 			if (cpu_online(cpu))
 				break;
 			udelay(10);
 			barrier();
 		}
 		if (!cpu_online(cpu)) {
 			pr_crit("CPU%u: failed to come online\n", cpu);
 			ret = -EIO;
 		}
 	} else {
 		pr_err("CPU%u: failed to boot: %d\n", cpu, ret);
 	}
 	secondary_data.stack = NULL;
 	secondary_data.pgdir = 0;
 	if (PHYS_OFFSET != PAGE_OFFSET) {
 #ifndef CONFIG_HOTPLUG_CPU
 		identity_mapping_del(pgd, __pa(__init_begin), __pa(__init_end));
 #endif
 		identity_mapping_del(pgd, __pa(_stext), __pa(_etext));
 		identity_mapping_del(pgd, __pa(_sdata), __pa(_edata));
 	}
 	pgd_free(&init_mm, pgd);
 	return ret;
 }
 #ifdef CONFIG_HOTPLUG_CPU
 static void percpu_timer_stop(void);
 /*
  * __cpu_disable runs on the processor to be shutdown.
  */
 int __cpu_disable(void)
 {
 	unsigned int cpu = smp_processor_id();
 	struct task_struct *p;
 	int ret;
 	ret = platform_cpu_disable(cpu);
 	if (ret)
 		return ret;
 	/*
 	 * Take this CPU offline.  Once we clear this, we can't return,
 	 * and we must not schedule until we're ready to give up the cpu.
 	 */
 	set_cpu_online(cpu, false);
 	/*
 	 * OK - migrate IRQs away from this CPU
 	 */
 	migrate_irqs();
 	/*
 	 * Stop the local timer for this CPU.
 	 */
 	percpu_timer_stop();
 	/*
 	 * Flush user cache and TLB mappings, and then remove this CPU
 	 * from the vm mask set of all processes.
 	 */
 	flush_cache_all();
 	local_flush_tlb_all();
 	read_lock(&tasklist_lock);
 	for_each_process(p) {
 		if (p->mm)
 			cpumask_clear_cpu(cpu, mm_cpumask(p->mm));
 	}
 	read_unlock(&tasklist_lock);
 	return 0;
 }
 static DECLARE_COMPLETION(cpu_died);
 /*
  * called on the thread which is asking for a CPU to be shutdown -
  * waits until shutdown has completed, or it is timed out.
  */
 void __cpu_die(unsigned int cpu)
 {
 	if (!wait_for_completion_timeout(&cpu_died, msecs_to_jiffies(5000))) {
 		pr_err("CPU%u: cpu didn't die\n", cpu);
 		return;
 	}
 	printk(KERN_NOTICE "CPU%u: shutdown\n", cpu);
 	if (!platform_cpu_kill(cpu))
 		printk("CPU%u: unable to kill\n", cpu);
 }
 /*
  * Called from the idle thread for the CPU which has been shutdown.
  *
  * Note that we disable IRQs here, but do not re-enable them
  * before returning to the caller. This is also the behaviour
  * of the other hotplug-cpu capable cores, so presumably coming
  * out of idle fixes this.
  */
 void __ref cpu_die(void)
 {
 	unsigned int cpu = smp_processor_id();
 	idle_task_exit();
 	local_irq_disable();
 	mb();
 	/* Tell __cpu_die() that this CPU is now safe to dispose of */
 	complete(&cpu_died);
 	/*
 	 * actual CPU shutdown procedure is at least platform (if not
 	 * CPU) specific.
 	 */
 	platform_cpu_die(cpu);
 	/*
 	 * Do not return to the idle loop - jump back to the secondary
 	 * cpu initialisation.  There's some initialisation which needs
 	 * to be repeated to undo the effects of taking the CPU offline.
 	 */
 	__asm__("mov	sp, %0\n"
 	"	mov	fp, #0\n"
 	"	b	secondary_start_kernel"
 		:
 		: "r" (task_stack_page(current) + THREAD_SIZE - 8));
 }
 #endif /* CONFIG_HOTPLUG_CPU */
 /*
  * Called by both boot and secondaries to move global data into
  * per-processor storage.
  */
 static void __cpuinit smp_store_cpu_info(unsigned int cpuid)
 {
 	struct cpuinfo_arm *cpu_info = &per_cpu(cpu_data, cpuid);
 	cpu_info->loops_per_jiffy = loops_per_jiffy;
 }
 /*
  * This is the secondary CPU boot entry.  We're using this CPUs
  * idle thread stack, but a set of temporary page tables.
  */
 asmlinkage void __cpuinit secondary_start_kernel(void)
 {
 	struct mm_struct *mm = &init_mm;
 	unsigned int cpu = smp_processor_id();
 	printk("CPU%u: Booted secondary processor\n", cpu);
 	/*
 	 * All kernel threads share the same mm context; grab a
 	 * reference and switch to it.
 	 */
 	atomic_inc(&mm->mm_count);
 	current->active_mm = mm;
 	cpumask_set_cpu(cpu, mm_cpumask(mm));
 	cpu_switch_mm(mm->pgd, mm);
 	enter_lazy_tlb(mm, current);
 	local_flush_tlb_all();
 	cpu_init();
 	preempt_disable();
 	trace_hardirqs_off();
 	/*
 	 * Give the platform a chance to do its own initialisation.
 	 */
 	platform_secondary_init(cpu);
 	/*
 	 * Enable local interrupts.
 	 */
 	notify_cpu_starting(cpu);
 	local_irq_enable();
 	local_fiq_enable();
 	/*
 	 * Setup the percpu timer for this CPU.
 	 */
 	percpu_timer_setup();
 	calibrate_delay();
 	smp_store_cpu_info(cpu);
 	/*
 	 * OK, now it's safe to let the boot CPU continue
 	 */
 	set_cpu_online(cpu, true);
 	/*
 	 * OK, it's off to the idle thread for us
 	 */
 	cpu_idle();
 }
 void __init smp_cpus_done(unsigned int max_cpus)
 {
 	int cpu;
 	unsigned long bogosum = 0;
 	for_each_online_cpu(cpu)
 		bogosum += per_cpu(cpu_data, cpu).loops_per_jiffy;
 	printk(KERN_INFO "SMP: Total of %d processors activated "
 	       "(%lu.%02lu BogoMIPS).\n",
 	       num_online_cpus(),
 	       bogosum / (500000/HZ),
 	       (bogosum / (5000/HZ)) % 100);
 }
 void __init smp_prepare_boot_cpu(void)
 {
 	unsigned int cpu = smp_processor_id();
 	per_cpu(cpu_data, cpu).idle = current;
 }
 void __init smp_prepare_cpus(unsigned int max_cpus)
 {
 	unsigned int ncores = num_possible_cpus();
 	smp_store_cpu_info(smp_processor_id());
 	/*
 	 * are we trying to boot more cores than exist?
 	 */
 	if (max_cpus > ncores)
 		max_cpus = ncores;
 	if (max_cpus > 1) {
 		/*
 		 * Enable the local timer or broadcast device for the
 		 * boot CPU, but only if we have more than one CPU.
 		 */
 		percpu_timer_setup();
 		/*
 		 * Initialise the SCU if there are more than one CPU
 		 * and let them know where to start.
 		 */
 		platform_smp_prepare_cpus(max_cpus);
 	}
 }
+static void (*smp_cross_call)(const struct cpumask *, unsigned int);
+void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
+{
+	smp_cross_call = fn;
+}
 void arch_send_call_function_ipi_mask(const struct cpumask *mask)
 {
 	smp_cross_call(mask, IPI_CALL_FUNC);
 }
 void arch_send_call_function_single_ipi(int cpu)
 {
 	smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE);
 }
 static const char *ipi_types[NR_IPI] = {
 #define S(x,s)	[x - IPI_TIMER] = s
 	S(IPI_TIMER, "Timer broadcast interrupts"),
 	S(IPI_RESCHEDULE, "Rescheduling interrupts"),
 	S(IPI_CALL_FUNC, "Function call interrupts"),
 	S(IPI_CALL_FUNC_SINGLE, "Single function call interrupts"),
 	S(IPI_CPU_STOP, "CPU stop interrupts"),
 };
 void show_ipi_list(struct seq_file *p, int prec)
 {
 	unsigned int cpu, i;
 	for (i = 0; i < NR_IPI; i++) {
 		seq_printf(p, "%*s%u: ", prec - 1, "IPI", i);
 		for_each_present_cpu(cpu)
 			seq_printf(p, "%10u ",
 				   __get_irq_stat(cpu, ipi_irqs[i]));
 		seq_printf(p, " %s\n", ipi_types[i]);
 	}
 }
 u64 smp_irq_stat_cpu(unsigned int cpu)
 {
 	u64 sum = 0;
 	int i;
 	for (i = 0; i < NR_IPI; i++)
 		sum += __get_irq_stat(cpu, ipi_irqs[i]);
 #ifdef CONFIG_LOCAL_TIMERS
 	sum += __get_irq_stat(cpu, local_timer_irqs);
 #endif
 	return sum;
 }
 /*
  * Timer (local or broadcast) support
  */
 static DEFINE_PER_CPU(struct clock_event_device, percpu_clockevent);
 static void ipi_timer(void)
 {
 	struct clock_event_device *evt = &__get_cpu_var(percpu_clockevent);
 	irq_enter();
 	evt->event_handler(evt);
 	irq_exit();
 }
 #ifdef CONFIG_LOCAL_TIMERS
 asmlinkage void __exception_irq_entry do_local_timer(struct pt_regs *regs)
 {
 	struct pt_regs *old_regs = set_irq_regs(regs);
 	int cpu = smp_processor_id();
 	if (local_timer_ack()) {
 		__inc_irq_stat(cpu, local_timer_irqs);
 		ipi_timer();
 	}
 	set_irq_regs(old_regs);
 }
 void show_local_irqs(struct seq_file *p, int prec)
 {
 	unsigned int cpu;
 	seq_printf(p, "%*s: ", prec, "LOC");
 	for_each_present_cpu(cpu)
 		seq_printf(p, "%10u ", __get_irq_stat(cpu, local_timer_irqs));
 	seq_printf(p, " Local timer interrupts\n");
 }
 #endif
 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
 static void smp_timer_broadcast(const struct cpumask *mask)
 {
 	smp_cross_call(mask, IPI_TIMER);
 }
 #else
 #define smp_timer_broadcast	NULL
 #endif
 static void broadcast_timer_set_mode(enum clock_event_mode mode,
 	struct clock_event_device *evt)
 {
 }
 static void broadcast_timer_setup(struct clock_event_device *evt)
 {
 	evt->name	= "dummy_timer";
 	evt->features	= CLOCK_EVT_FEAT_ONESHOT |
 			  CLOCK_EVT_FEAT_PERIODIC |
 			  CLOCK_EVT_FEAT_DUMMY;
 	evt->rating	= 400;
 	evt->mult	= 1;
 	evt->set_mode	= broadcast_timer_set_mode;
 	clockevents_register_device(evt);
 }
 void __cpuinit percpu_timer_setup(void)
 {
 	unsigned int cpu = smp_processor_id();
 	struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu);
 	evt->cpumask = cpumask_of(cpu);
 	evt->broadcast = smp_timer_broadcast;
 	if (local_timer_setup(evt))
 		broadcast_timer_setup(evt);
 }
 #ifdef CONFIG_HOTPLUG_CPU
 /*
  * The generic clock events code purposely does not stop the local timer
  * on CPU_DEAD/CPU_DEAD_FROZEN hotplug events, so we have to do it
  * manually here.
  */
 static void percpu_timer_stop(void)
 {
 	unsigned int cpu = smp_processor_id();
 	struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu);
 	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
 }
 #endif
 static DEFINE_SPINLOCK(stop_lock);
 /*
  * ipi_cpu_stop - handle IPI from smp_send_stop()
  */
 static void ipi_cpu_stop(unsigned int cpu)
 {
 	if (system_state == SYSTEM_BOOTING ||
 	    system_state == SYSTEM_RUNNING) {
 		spin_lock(&stop_lock);
 		printk(KERN_CRIT "CPU%u: stopping\n", cpu);
 		dump_stack();
 		spin_unlock(&stop_lock);
 	}
 	set_cpu_online(cpu, false);
 	local_fiq_disable();
 	local_irq_disable();
 	while (1)
 		cpu_relax();
 }
 /*
  * Main handler for inter-processor interrupts
  */
 asmlinkage void __exception_irq_entry do_IPI(int ipinr, struct pt_regs *regs)
 {
 	unsigned int cpu = smp_processor_id();
 	struct pt_regs *old_regs = set_irq_regs(regs);
 	if (ipinr >= IPI_TIMER && ipinr < IPI_TIMER + NR_IPI)
 		__inc_irq_stat(cpu, ipi_irqs[ipinr - IPI_TIMER]);
 	switch (ipinr) {
 	case IPI_TIMER:
 		ipi_timer();
 		break;
 	case IPI_RESCHEDULE:
 		/*
 		 * nothing more to do - eveything is
 		 * done on the interrupt return path
 		 */
 		break;
 	case IPI_CALL_FUNC:
 		generic_smp_call_function_interrupt();
 		break;
 	case IPI_CALL_FUNC_SINGLE:
 		generic_smp_call_function_single_interrupt();
 		break;
 	case IPI_CPU_STOP:
 		ipi_cpu_stop(cpu);
 		break;
 	default:
 		printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%x\n",
 		       cpu, ipinr);
 		break;
 	}
 	set_irq_regs(old_regs);
 }
 void smp_send_reschedule(int cpu)
 {
 	smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
 }
 void smp_send_stop(void)
 {
 	unsigned long timeout;
 	if (num_online_cpus() > 1) {
 		cpumask_t mask = cpu_online_map;
 		cpu_clear(smp_processor_id(), mask);
 		smp_cross_call(&mask, IPI_CPU_STOP);
 	}
 	/* Wait up to one second for other CPUs to stop */
 	timeout = USEC_PER_SEC;
 	while (num_online_cpus() > 1 && timeout--)
 		udelay(1);
 	if (num_online_cpus() > 1)
 		pr_warning("SMP: failed to stop secondary CPUs\n");
 }
 /*
  * not supported here
  */
 int setup_profiling_timer(unsigned int multiplier)
 {
 	return -EINVAL;
 }

arch/arm/mach-exynos4/include/mach/smp.h

View file @ 0f7b332

1	/* linux/arch/arm/mach-exynos4/include/mach/smp.h		File was deleted
2	*
3	* Cloned from arch/arm/mach-realview/include/mach/smp.h
4	*/
5
6	#ifndef ASM_ARCH_SMP_H
7	#define ASM_ARCH_SMP_H __FILE__
8
9	#include <asm/hardware/gic.h>
10
11	/*
12	* We use IRQ1 as the IPI
13	*/
14	static inline void smp_cross_call(const struct cpumask *mask, int ipi)
15	{
16	gic_raise_softirq(mask, ipi);
17	}
18
19	#endif
20		1	/* linux/arch/arm/mach-exynos4/include/mach/smp.h

arch/arm/mach-exynos4/platsmp.c

Diff comments View file @ 0f7b332

 /* linux/arch/arm/mach-exynos4/platsmp.c
  *
  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  *		http://www.samsung.com
  *
  * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
  *
  *  Copyright (C) 2002 ARM Ltd.
  *  All Rights Reserved
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
 */
 #include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/jiffies.h>
 #include <linux/smp.h>
 #include <linux/io.h>
 #include <asm/cacheflush.h>
+#include <asm/hardware/gic.h>
 #include <asm/smp_scu.h>
 #include <asm/unified.h>
 #include <mach/hardware.h>
 #include <mach/regs-clock.h>
 extern void exynos4_secondary_startup(void);
 /*
  * control for which core is the next to come out of the secondary
  * boot "holding pen"
  */
 volatile int __cpuinitdata pen_release = -1;
 /*
  * Write pen_release in a way that is guaranteed to be visible to all
  * observers, irrespective of whether they're taking part in coherency
  * or not.  This is necessary for the hotplug code to work reliably.
  */
 static void write_pen_release(int val)
 {
 	pen_release = val;
 	smp_wmb();
 	__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
 	outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
 }
 static void __iomem *scu_base_addr(void)
 {
 	return (void __iomem *)(S5P_VA_SCU);
 }
 static DEFINE_SPINLOCK(boot_lock);
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
 	/*
 	 * if any interrupts are already enabled for the primary
 	 * core (e.g. timer irq), then they will not have been enabled
 	 * for us: do so
 	 */
 	gic_secondary_init(0);
 	/*
 	 * let the primary processor know we're out of the
 	 * pen, then head off into the C entry point
 	 */
 	write_pen_release(-1);
 	/*
 	 * Synchronise with the boot thread.
 	 */
 	spin_lock(&boot_lock);
 	spin_unlock(&boot_lock);
 }
 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
 	unsigned long timeout;
 	/*
 	 * Set synchronisation state between this boot processor
 	 * and the secondary one
 	 */
 	spin_lock(&boot_lock);
 	/*
 	 * The secondary processor is waiting to be released from
 	 * the holding pen - release it, then wait for it to flag
 	 * that it has been released by resetting pen_release.
 	 *
 	 * Note that "pen_release" is the hardware CPU ID, whereas
 	 * "cpu" is Linux's internal ID.
 	 */
 	write_pen_release(cpu);
 	/*
 	 * Send the secondary CPU a soft interrupt, thereby causing
 	 * the boot monitor to read the system wide flags register,
 	 * and branch to the address found there.
 	 */
-	smp_cross_call(cpumask_of(cpu), 1);
+	gic_raise_softirq(cpumask_of(cpu), 1);
 	timeout = jiffies + (1 * HZ);
 	while (time_before(jiffies, timeout)) {
 		smp_rmb();
 		if (pen_release == -1)
 			break;
 		udelay(10);
 	}
 	/*
 	 * now the secondary core is starting up let it run its
 	 * calibrations, then wait for it to finish
 	 */
 	spin_unlock(&boot_lock);
 	return pen_release != -1 ? -ENOSYS : 0;
 }
 /*
  * Initialise the CPU possible map early - this describes the CPUs
  * which may be present or become present in the system.
  */
 void __init smp_init_cpus(void)
 {
 	void __iomem *scu_base = scu_base_addr();
 	unsigned int i, ncores;
 	ncores = scu_base ? scu_get_core_count(scu_base) : 1;
 	/* sanity check */
 	if (ncores > NR_CPUS) {
 		printk(KERN_WARNING
 		       "EXYNOS4: no. of cores (%d) greater than configured "
 		       "maximum of %d - clipping\n",
 		       ncores, NR_CPUS);
 		ncores = NR_CPUS;
 	}
 	for (i = 0; i < ncores; i++)
 		set_cpu_possible(i, true);
+	set_smp_cross_call(gic_raise_softirq);
 }
 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 {
 	int i;
 	/*
 	 * Initialise the present map, which describes the set of CPUs
 	 * actually populated at the present time.
 	 */
 	for (i = 0; i < max_cpus; i++)
 		set_cpu_present(i, true);
 	scu_enable(scu_base_addr());
 	/*
 	 * Write the address of secondary startup into the
 	 * system-wide flags register. The boot monitor waits
 	 * until it receives a soft interrupt, and then the
 	 * secondary CPU branches to this address.
 	 */
 	__raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), S5P_VA_SYSRAM);
 }

arch/arm/mach-msm/include/mach/smp.h

View file @ 0f7b332

1	/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.		File was deleted
2	*
3	* This program is free software; you can redistribute it and/or modify
4	* it under the terms of the GNU General Public License version 2 and
5	* only version 2 as published by the Free Software Foundation.
6	*
7	* This program is distributed in the hope that it will be useful,
8	* but WITHOUT ANY WARRANTY; without even the implied warranty of
9	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10	* GNU General Public License for more details.
11	*/
12
13	#ifndef __ASM_ARCH_MSM_SMP_H
14	#define __ASM_ARCH_MSM_SMP_H
15
16	#include <asm/hardware/gic.h>
17
18	static inline void smp_cross_call(const struct cpumask *mask, int ipi)
19	{
20	gic_raise_softirq(mask, ipi);
21	}
22
23	#endif
24		1	/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.

arch/arm/mach-msm/platsmp.c

Diff comments View file @ 0f7b332

 /*
  *  Copyright (C) 2002 ARM Ltd.
  *  All Rights Reserved
  *  Copyright (c) 2010, Code Aurora Forum. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 #include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/jiffies.h>
 #include <linux/smp.h>
 #include <linux/io.h>
 #include <asm/hardware/gic.h>
 #include <asm/cacheflush.h>
 #include <asm/mach-types.h>
 #include <mach/msm_iomap.h>
 #include "scm-boot.h"
 #define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0
 #define SCSS_CPU1CORE_RESET 0xD80
 #define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64
 /* Mask for edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
 #define GIC_PPI_EDGE_MASK 0xFFFFD7FF
 extern void msm_secondary_startup(void);
 /*
  * control for which core is the next to come out of the secondary
  * boot "holding pen".
  */
 volatile int pen_release = -1;
 static DEFINE_SPINLOCK(boot_lock);
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
 	/* Configure edge-triggered PPIs */
 	writel(GIC_PPI_EDGE_MASK, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
 	/*
 	 * if any interrupts are already enabled for the primary
 	 * core (e.g. timer irq), then they will not have been enabled
 	 * for us: do so
 	 */
 	gic_secondary_init(0);
 	/*
 	 * let the primary processor know we're out of the
 	 * pen, then head off into the C entry point
 	 */
 	pen_release = -1;
 	smp_wmb();
 	/*
 	 * Synchronise with the boot thread.
 	 */
 	spin_lock(&boot_lock);
 	spin_unlock(&boot_lock);
 }
 static __cpuinit void prepare_cold_cpu(unsigned int cpu)
 {
 	int ret;
 	ret = scm_set_boot_addr(virt_to_phys(msm_secondary_startup),
 				SCM_FLAG_COLDBOOT_CPU1);
 	if (ret == 0) {
 		void *sc1_base_ptr;
 		sc1_base_ptr = ioremap_nocache(0x00902000, SZ_4K*2);
 		if (sc1_base_ptr) {
 			writel(0, sc1_base_ptr + VDD_SC1_ARRAY_CLAMP_GFS_CTL);
 			writel(0, sc1_base_ptr + SCSS_CPU1CORE_RESET);
 			writel(3, sc1_base_ptr + SCSS_DBG_STATUS_CORE_PWRDUP);
 			iounmap(sc1_base_ptr);
 		}
 	} else
 		printk(KERN_DEBUG "Failed to set secondary core boot "
 				  "address\n");
 }
 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
 	unsigned long timeout;
 	static int cold_boot_done;
 	/* Only need to bring cpu out of reset this way once */
 	if (cold_boot_done == false) {
 		prepare_cold_cpu(cpu);
 		cold_boot_done = true;
 	}
 	/*
 	 * set synchronisation state between this boot processor
 	 * and the secondary one
 	 */
 	spin_lock(&boot_lock);
 	/*
 	 * The secondary processor is waiting to be released from
 	 * the holding pen - release it, then wait for it to flag
 	 * that it has been released by resetting pen_release.
 	 *
 	 * Note that "pen_release" is the hardware CPU ID, whereas
 	 * "cpu" is Linux's internal ID.
 	 */
 	pen_release = cpu;
 	__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
 	outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
 	/*
 	 * Send the secondary CPU a soft interrupt, thereby causing
 	 * the boot monitor to read the system wide flags register,
 	 * and branch to the address found there.
 	 */
-	smp_cross_call(cpumask_of(cpu), 1);
+	gic_raise_softirq(cpumask_of(cpu), 1);
 	timeout = jiffies + (1 * HZ);
 	while (time_before(jiffies, timeout)) {
 		smp_rmb();
 		if (pen_release == -1)
 			break;
 		udelay(10);
 	}
 	/*
 	 * now the secondary core is starting up let it run its
 	 * calibrations, then wait for it to finish
 	 */
 	spin_unlock(&boot_lock);
 	return pen_release != -1 ? -ENOSYS : 0;
 }
 /*
  * Initialise the CPU possible map early - this describes the CPUs
  * which may be present or become present in the system. The msm8x60
  * does not support the ARM SCU, so just set the possible cpu mask to
  * NR_CPUS.
  */
 void __init smp_init_cpus(void)
 {
 	unsigned int i;
 	for (i = 0; i < NR_CPUS; i++)
 		set_cpu_possible(i, true);
+        set_smp_cross_call(gic_raise_softirq);
 }
 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 {
 	int i;
 	/*
 	 * Initialise the present map, which describes the set of CPUs
 	 * actually populated at the present time.
 	 */
 	for (i = 0; i < max_cpus; i++)
 		set_cpu_present(i, true);
 }

arch/arm/mach-omap2/omap-smp.c

Diff comments View file @ 0f7b332

 /*
  * OMAP4 SMP source file. It contains platform specific fucntions
  * needed for the linux smp kernel.
  *
  * Copyright (C) 2009 Texas Instruments, Inc.
  *
  * Author:
  *      Santosh Shilimkar <santosh.shilimkar@ti.com>
  *
  * Platform file needed for the OMAP4 SMP. This file is based on arm
  * realview smp platform.
  * * Copyright (c) 2002 ARM Limited.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 #include <linux/init.h>
 #include <linux/device.h>
 #include <linux/smp.h>
 #include <linux/io.h>
 #include <asm/cacheflush.h>
+#include <asm/hardware/gic.h>
 #include <asm/smp_scu.h>
 #include <mach/hardware.h>
 #include <mach/omap4-common.h>
 /* SCU base address */
 static void __iomem *scu_base;
 static DEFINE_SPINLOCK(boot_lock);
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
 	/*
 	 * If any interrupts are already enabled for the primary
 	 * core (e.g. timer irq), then they will not have been enabled
 	 * for us: do so
 	 */
 	gic_secondary_init(0);
 	/*
 	 * Synchronise with the boot thread.
 	 */
 	spin_lock(&boot_lock);
 	spin_unlock(&boot_lock);
 }
 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
 	/*
 	 * Set synchronisation state between this boot processor
 	 * and the secondary one
 	 */
 	spin_lock(&boot_lock);
 	/*
 	 * Update the AuxCoreBoot0 with boot state for secondary core.
 	 * omap_secondary_startup() routine will hold the secondary core till
 	 * the AuxCoreBoot1 register is updated with cpu state
 	 * A barrier is added to ensure that write buffer is drained
 	 */
 	omap_modify_auxcoreboot0(0x200, 0xfffffdff);
 	flush_cache_all();
 	smp_wmb();
-	smp_cross_call(cpumask_of(cpu), 1);
+	gic_raise_softirq(cpumask_of(cpu), 1);
 	/*
 	 * Now the secondary core is starting up let it run its
 	 * calibrations, then wait for it to finish
 	 */
 	spin_unlock(&boot_lock);
 	return 0;
 }
 static void __init wakeup_secondary(void)
 {
 	/*
 	 * Write the address of secondary startup routine into the
 	 * AuxCoreBoot1 where ROM code will jump and start executing
 	 * on secondary core once out of WFE
 	 * A barrier is added to ensure that write buffer is drained
 	 */
 	omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
 	smp_wmb();
 	/*
 	 * Send a 'sev' to wake the secondary core from WFE.
 	 * Drain the outstanding writes to memory
 	 */
 	dsb_sev();
 	mb();
 }
 /*
  * Initialise the CPU possible map early - this describes the CPUs
  * which may be present or become present in the system.
  */
 void __init smp_init_cpus(void)
 {
 	unsigned int i, ncores;
 	/* Never released */
 	scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256);
 	BUG_ON(!scu_base);
 	ncores = scu_get_core_count(scu_base);
 	/* sanity check */
 	if (ncores > NR_CPUS) {
 		printk(KERN_WARNING
 		       "OMAP4: no. of cores (%d) greater than configured "
 		       "maximum of %d - clipping\n",
 		       ncores, NR_CPUS);
 		ncores = NR_CPUS;
 	}
 	for (i = 0; i < ncores; i++)
 		set_cpu_possible(i, true);
+	set_smp_cross_call(gic_raise_softirq);
 }
 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 {
 	int i;
 	/*
 	 * Initialise the present map, which describes the set of CPUs
 	 * actually populated at the present time.
 	 */
 	for (i = 0; i < max_cpus; i++)
 		set_cpu_present(i, true);
 	/*
 	 * Initialise the SCU and wake up the secondary core using
 	 * wakeup_secondary().
 	 */
 	scu_enable(scu_base);
 	wakeup_secondary();
 }

arch/arm/mach-realview/include/mach/smp.h

View file @ 0f7b332

1	#ifndef ASMARM_ARCH_SMP_H		File was deleted
2	#define ASMARM_ARCH_SMP_H
3
4	#include <asm/hardware/gic.h>
5
6	/*
7	* We use IRQ1 as the IPI
8	*/
9	static inline void smp_cross_call(const struct cpumask *mask, int ipi)
10	{
11	gic_raise_softirq(mask, ipi);
12	}
13
14	#endif
15		1	#ifndef ASMARM_ARCH_SMP_H

arch/arm/mach-realview/platsmp.c

Diff comments View file @ 0f7b332

 /*
  *  linux/arch/arm/mach-realview/platsmp.c
  *
  *  Copyright (C) 2002 ARM Ltd.
  *  All Rights Reserved
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 #include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/smp.h>
 #include <linux/io.h>
 #include <mach/hardware.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/smp_scu.h>
 #include <asm/unified.h>
 #include <mach/board-eb.h>
 #include <mach/board-pb11mp.h>
 #include <mach/board-pbx.h>
 #include "core.h"
 extern void versatile_secondary_startup(void);
 static void __iomem *scu_base_addr(void)
 {
 	if (machine_is_realview_eb_mp())
 		return __io_address(REALVIEW_EB11MP_SCU_BASE);
 	else if (machine_is_realview_pb11mp())
 		return __io_address(REALVIEW_TC11MP_SCU_BASE);
 	else if (machine_is_realview_pbx() &&
 		 (core_tile_pbx11mp() || core_tile_pbxa9mp()))
 		return __io_address(REALVIEW_PBX_TILE_SCU_BASE);
 	else
 		return (void __iomem *)0;
 }
 /*
  * Initialise the CPU possible map early - this describes the CPUs
  * which may be present or become present in the system.
  */
 void __init smp_init_cpus(void)
 {
 	void __iomem *scu_base = scu_base_addr();
 	unsigned int i, ncores;
 	ncores = scu_base ? scu_get_core_count(scu_base) : 1;
 	/* sanity check */
 	if (ncores > NR_CPUS) {
 		printk(KERN_WARNING
 		       "Realview: no. of cores (%d) greater than configured "
 		       "maximum of %d - clipping\n",
 		       ncores, NR_CPUS);
 		ncores = NR_CPUS;
 	}
 	for (i = 0; i < ncores; i++)
 		set_cpu_possible(i, true);
+	set_smp_cross_call(gic_raise_softirq);
 }
 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 {
 	int i;
 	/*
 	 * Initialise the present map, which describes the set of CPUs
 	 * actually populated at the present time.
 	 */
 	for (i = 0; i < max_cpus; i++)
 		set_cpu_present(i, true);
 	scu_enable(scu_base_addr());
 	/*
 	 * Write the address of secondary startup into the
 	 * system-wide flags register. The BootMonitor waits
 	 * until it receives a soft interrupt, and then the
 	 * secondary CPU branches to this address.
 	 */
 	__raw_writel(BSYM(virt_to_phys(versatile_secondary_startup)),
 		     __io_address(REALVIEW_SYS_FLAGSSET));
 }

arch/arm/mach-shmobile/include/mach/smp.h

View file @ 0f7b332

1	#ifndef __MACH_SMP_H		File was deleted
2	#define __MACH_SMP_H
3
4	#include <asm/hardware/gic.h>
5
6	/*
7	* We use IRQ1 as the IPI
8	*/
9	static inline void smp_cross_call(const struct cpumask *mask, int ipi)
10	{
11	#if defined(CONFIG_ARM_GIC)
12	gic_raise_softirq(mask, ipi);
13	#endif
14	}
15
16	#endif
17		1	#ifndef __MACH_SMP_H

arch/arm/mach-shmobile/platsmp.c

Diff comments View file @ 0f7b332

 /*
  * SMP support for R-Mobile / SH-Mobile
  *
  * Copyright (C) 2010  Magnus Damm
  * Copyright (C) 2011  Paul Mundt
  *
  * Based on vexpress, Copyright (C) 2002 ARM Ltd, All Rights Reserved
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 #include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/smp.h>
 #include <linux/io.h>
+#include <asm/hardware/gic.h>
 #include <asm/localtimer.h>
 #include <asm/mach-types.h>
 #include <mach/common.h>
 static unsigned int __init shmobile_smp_get_core_count(void)
 {
 	if (machine_is_ag5evm())
 		return sh73a0_get_core_count();
 	return 1;
 }
 static void __init shmobile_smp_prepare_cpus(void)
 {
 	if (machine_is_ag5evm())
 		sh73a0_smp_prepare_cpus();
 }
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
 	trace_hardirqs_off();
 	if (machine_is_ag5evm())
 		sh73a0_secondary_init(cpu);
 }
 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
 	if (machine_is_ag5evm())
 		return sh73a0_boot_secondary(cpu);
 	return -ENOSYS;
 }
 void __init smp_init_cpus(void)
 {
 	unsigned int ncores = shmobile_smp_get_core_count();
 	unsigned int i;
 	for (i = 0; i < ncores; i++)
 		set_cpu_possible(i, true);
+	set_smp_cross_call(gic_raise_softirq);
 }
 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 {
 	int i;
 	for (i = 0; i < max_cpus; i++)
 		set_cpu_present(i, true);
 	shmobile_smp_prepare_cpus();
 }

arch/arm/mach-tegra/include/mach/smp.h

View file @ 0f7b332

1	#ifndef ASMARM_ARCH_SMP_H		File was deleted
2	#define ASMARM_ARCH_SMP_H
3
4	#include <asm/hardware/gic.h>
5
6	/*
7	* We use IRQ1 as the IPI
8	*/
9	static inline void smp_cross_call(const struct cpumask *mask, int ipi)
10	{
11	gic_raise_softirq(mask, ipi);
12	}
13
14	#endif
15		1	#ifndef ASMARM_ARCH_SMP_H

arch/arm/mach-tegra/platsmp.c

Diff comments View file @ 0f7b332

 /*
  *  linux/arch/arm/mach-tegra/platsmp.c
  *
  *  Copyright (C) 2002 ARM Ltd.
  *  All Rights Reserved
  *
  *  Copyright (C) 2009 Palm
  *  All Rights Reserved
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 #include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/jiffies.h>
 #include <linux/smp.h>
 #include <linux/io.h>
 #include <asm/cacheflush.h>
+#include <asm/hardware/gic.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/smp_scu.h>
 #include <mach/iomap.h>
 extern void tegra_secondary_startup(void);
 static DEFINE_SPINLOCK(boot_lock);
 static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
 #define EVP_CPU_RESET_VECTOR \
 	(IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
 #define CLK_RST_CONTROLLER_CLK_CPU_CMPLX \
 	(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x4c)
 #define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \
 	(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344)
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
 	/*
 	 * if any interrupts are already enabled for the primary
 	 * core (e.g. timer irq), then they will not have been enabled
 	 * for us: do so
 	 */
 	gic_secondary_init(0);
 	/*
 	 * Synchronise with the boot thread.
 	 */
 	spin_lock(&boot_lock);
 	spin_unlock(&boot_lock);
 }
 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
 	unsigned long old_boot_vector;
 	unsigned long boot_vector;
 	unsigned long timeout;
 	u32 reg;
 	/*
 	 * set synchronisation state between this boot processor
 	 * and the secondary one
 	 */
 	spin_lock(&boot_lock);
 	/* set the reset vector to point to the secondary_startup routine */
 	boot_vector = virt_to_phys(tegra_secondary_startup);
 	old_boot_vector = readl(EVP_CPU_RESET_VECTOR);
 	writel(boot_vector, EVP_CPU_RESET_VECTOR);
 	/* enable cpu clock on cpu1 */
 	reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
 	writel(reg & ~(1<<9), CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
 	reg = (1<<13) | (1<<9) | (1<<5) | (1<<1);
 	writel(reg, CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
 	smp_wmb();
 	flush_cache_all();
 	/* unhalt the cpu */
 	writel(0, IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x14);
 	timeout = jiffies + (1 * HZ);
 	while (time_before(jiffies, timeout)) {
 		if (readl(EVP_CPU_RESET_VECTOR) != boot_vector)
 			break;
 		udelay(10);
 	}
 	/* put the old boot vector back */
 	writel(old_boot_vector, EVP_CPU_RESET_VECTOR);
 	/*
 	 * now the secondary core is starting up let it run its
 	 * calibrations, then wait for it to finish
 	 */
 	spin_unlock(&boot_lock);
 	return 0;
 }
 /*
  * Initialise the CPU possible map early - this describes the CPUs
  * which may be present or become present in the system.
  */
 void __init smp_init_cpus(void)
 {
 	unsigned int i, ncores = scu_get_core_count(scu_base);
 	if (ncores > NR_CPUS) {
 		printk(KERN_ERR "Tegra: no. of cores (%u) greater than configured (%u), clipping\n",
 			ncores, NR_CPUS);
 		ncores = NR_CPUS;
 	}
 	for (i = 0; i < ncores; i++)
 		cpu_set(i, cpu_possible_map);
+	set_smp_cross_call(gic_raise_softirq);
 }
 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 {
 	int i;
 	/*
 	 * Initialise the present map, which describes the set of CPUs
 	 * actually populated at the present time.
 	 */
 	for (i = 0; i < max_cpus; i++)
 		set_cpu_present(i, true);
 	scu_enable(scu_base);
 }

arch/arm/mach-ux500/include/mach/smp.h

View file @ 0f7b332

1	/*		File was deleted
2	* This file is based ARM realview platform.
3	* Copyright (C) ARM Limited.
4	*
5	* This file is licensed under the terms of the GNU General Public
6	* License version 2. This program is licensed "as is" without any
7	* warranty of any kind, whether express or implied.
8	*/
9	#ifndef ASMARM_ARCH_SMP_H
10	#define ASMARM_ARCH_SMP_H
11
12	#include <asm/hardware/gic.h>
13
14	/* This is required to wakeup the secondary core */
15	extern void u8500_secondary_startup(void);
16
17	/*
18	* We use IRQ1 as the IPI
19	*/
20	static inline void smp_cross_call(const struct cpumask *mask, int ipi)
21	{
22	gic_raise_softirq(mask, ipi);
23	}
24	#endif
25		1	/*

arch/arm/mach-ux500/platsmp.c

Diff comments View file @ 0f7b332

 /*
  * Copyright (C) 2002 ARM Ltd.
  * Copyright (C) 2008 STMicroelctronics.
  * Copyright (C) 2009 ST-Ericsson.
  * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
  *
  * This file is based on arm realview platform
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 #include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/smp.h>
 #include <linux/io.h>
 #include <asm/cacheflush.h>
+#include <asm/hardware/gic.h>
 #include <asm/smp_scu.h>
 #include <mach/hardware.h>
 #include <mach/setup.h>
 /*
  * control for which core is the next to come out of the secondary
  * boot "holding pen"
  */
 volatile int pen_release = -1;
 /*
  * Write pen_release in a way that is guaranteed to be visible to all
  * observers, irrespective of whether they're taking part in coherency
  * or not.  This is necessary for the hotplug code to work reliably.
  */
 static void write_pen_release(int val)
 {
 	pen_release = val;
 	smp_wmb();
 	__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
 	outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
 }
 static void __iomem *scu_base_addr(void)
 {
 	if (cpu_is_u5500())
 		return __io_address(U5500_SCU_BASE);
 	else if (cpu_is_u8500())
 		return __io_address(U8500_SCU_BASE);
 	else
 		ux500_unknown_soc();
 	return NULL;
 }
 static DEFINE_SPINLOCK(boot_lock);
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
 	/*
 	 * if any interrupts are already enabled for the primary
 	 * core (e.g. timer irq), then they will not have been enabled
 	 * for us: do so
 	 */
 	gic_secondary_init(0);
 	/*
 	 * let the primary processor know we're out of the
 	 * pen, then head off into the C entry point
 	 */
 	write_pen_release(-1);
 	/*
 	 * Synchronise with the boot thread.
 	 */
 	spin_lock(&boot_lock);
 	spin_unlock(&boot_lock);
 }
 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
 	unsigned long timeout;
 	/*
 	 * set synchronisation state between this boot processor
 	 * and the secondary one
 	 */
 	spin_lock(&boot_lock);
 	/*
 	 * The secondary processor is waiting to be released from
 	 * the holding pen - release it, then wait for it to flag
 	 * that it has been released by resetting pen_release.
 	 */
 	write_pen_release(cpu);
-	smp_cross_call(cpumask_of(cpu), 1);
+	gic_raise_softirq(cpumask_of(cpu), 1);
 	timeout = jiffies + (1 * HZ);
 	while (time_before(jiffies, timeout)) {
 		if (pen_release == -1)
 			break;
 	}
 	/*
 	 * now the secondary core is starting up let it run its
 	 * calibrations, then wait for it to finish
 	 */
 	spin_unlock(&boot_lock);
 	return pen_release != -1 ? -ENOSYS : 0;
 }
 static void __init wakeup_secondary(void)
 {
 	void __iomem *backupram;
 	if (cpu_is_u5500())
 		backupram = __io_address(U5500_BACKUPRAM0_BASE);
 	else if (cpu_is_u8500())
 		backupram = __io_address(U8500_BACKUPRAM0_BASE);
 	else
 		ux500_unknown_soc();
 	/*
 	 * write the address of secondary startup into the backup ram register
 	 * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
 	 * backup ram register at offset 0x1FF0, which is what boot rom code
 	 * is waiting for. This would wake up the secondary core from WFE
 	 */
 #define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4
 	__raw_writel(virt_to_phys(u8500_secondary_startup),
 		     backupram + UX500_CPU1_JUMPADDR_OFFSET);
 #define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0
 	__raw_writel(0xA1FEED01,
 		     backupram + UX500_CPU1_WAKEMAGIC_OFFSET);
 	/* make sure write buffer is drained */
 	mb();
 }
 /*
  * Initialise the CPU possible map early - this describes the CPUs
  * which may be present or become present in the system.
  */
 void __init smp_init_cpus(void)
 {
 	void __iomem *scu_base = scu_base_addr();
 	unsigned int i, ncores;
 	ncores = scu_base ? scu_get_core_count(scu_base) : 1;
 	/* sanity check */
 	if (ncores > NR_CPUS) {
 		printk(KERN_WARNING
 		       "U8500: no. of cores (%d) greater than configured "
 		       "maximum of %d - clipping\n",
 		       ncores, NR_CPUS);
 		ncores = NR_CPUS;
 	}
 	for (i = 0; i < ncores; i++)
 		set_cpu_possible(i, true);
+	set_smp_cross_call(gic_raise_softirq);
 }
 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 {
 	int i;
 	/*
 	 * Initialise the present map, which describes the set of CPUs
 	 * actually populated at the present time.
 	 */
 	for (i = 0; i < max_cpus; i++)
 		set_cpu_present(i, true);
 	scu_enable(scu_base_addr());
 	wakeup_secondary();
 }

arch/arm/mach-vexpress/ct-ca9x4.c

Diff comments View file @ 0f7b332

 /*
  * Versatile Express Core Tile Cortex A9x4 Support
  */
 #include <linux/init.h>
 #include <linux/gfp.h>
 #include <linux/device.h>
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
 #include <linux/clkdev.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/hardware/gic.h>
 #include <asm/pmu.h>
 #include <asm/smp_scu.h>
 #include <asm/smp_twd.h>
 #include <mach/ct-ca9x4.h>
 #include <asm/hardware/timer-sp.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include "core.h"
 #include <mach/motherboard.h>
 #include <plat/clcd.h>
 #define V2M_PA_CS7	0x10000000
 static struct map_desc ct_ca9x4_io_desc[] __initdata = {
 	{
 		.virtual	= __MMIO_P2V(CT_CA9X4_MPIC),
 		.pfn		= __phys_to_pfn(CT_CA9X4_MPIC),
 		.length		= SZ_16K,
 		.type		= MT_DEVICE,
 	}, {
 		.virtual	= __MMIO_P2V(CT_CA9X4_SP804_TIMER),
 		.pfn		= __phys_to_pfn(CT_CA9X4_SP804_TIMER),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE,
 	}, {
 		.virtual	= __MMIO_P2V(CT_CA9X4_L2CC),
 		.pfn		= __phys_to_pfn(CT_CA9X4_L2CC),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE,
 	},
 };
 static void __init ct_ca9x4_map_io(void)
 {
 #ifdef CONFIG_LOCAL_TIMERS
 	twd_base = MMIO_P2V(A9_MPCORE_TWD);
 #endif
 	iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
 }
 static void __init ct_ca9x4_init_irq(void)
 {
 	gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST),
 		 MMIO_P2V(A9_MPCORE_GIC_CPU));
 }
 #if 0
 static void __init ct_ca9x4_timer_init(void)
 {
 	writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
 	writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
 	sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1));
 	sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0);
 }
 static struct sys_timer ct_ca9x4_timer = {
 	.init	= ct_ca9x4_timer_init,
 };
 #endif
 static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
 {
 	v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
 	v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE_DB1, 2);
 }
 static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
 {
 	unsigned long framesize = 1024 * 768 * 2;
 	fb->panel = versatile_clcd_get_panel("XVGA");
 	if (!fb->panel)
 		return -EINVAL;
 	return versatile_clcd_setup_dma(fb, framesize);
 }
 static struct clcd_board ct_ca9x4_clcd_data = {
 	.name		= "CT-CA9X4",
 	.caps		= CLCD_CAP_5551 | CLCD_CAP_565,
 	.check		= clcdfb_check,
 	.decode		= clcdfb_decode,
 	.enable		= ct_ca9x4_clcd_enable,
 	.setup		= ct_ca9x4_clcd_setup,
 	.mmap		= versatile_clcd_mmap_dma,
 	.remove		= versatile_clcd_remove_dma,
 };
 static AMBA_DEVICE(clcd, "ct:clcd", CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);
 static AMBA_DEVICE(dmc, "ct:dmc", CT_CA9X4_DMC, NULL);
 static AMBA_DEVICE(smc, "ct:smc", CT_CA9X4_SMC, NULL);
 static AMBA_DEVICE(gpio, "ct:gpio", CT_CA9X4_GPIO, NULL);
 static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
 	&clcd_device,
 	&dmc_device,
 	&smc_device,
 	&gpio_device,
 };
 static long ct_round(struct clk *clk, unsigned long rate)
 {
 	return rate;
 }
 static int ct_set(struct clk *clk, unsigned long rate)
 {
 	return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_DB1 | 1, rate);
 }
 static const struct clk_ops osc1_clk_ops = {
 	.round	= ct_round,
 	.set	= ct_set,
 };
 static struct clk osc1_clk = {
 	.ops	= &osc1_clk_ops,
 	.rate	= 24000000,
 };
 static struct clk_lookup lookups[] = {
 	{	/* CLCD */
 		.dev_id		= "ct:clcd",
 		.clk		= &osc1_clk,
 	},
 };
 static struct resource pmu_resources[] = {
 	[0] = {
 		.start	= IRQ_CT_CA9X4_PMU_CPU0,
 		.end	= IRQ_CT_CA9X4_PMU_CPU0,
 		.flags	= IORESOURCE_IRQ,
 	},
 	[1] = {
 		.start	= IRQ_CT_CA9X4_PMU_CPU1,
 		.end	= IRQ_CT_CA9X4_PMU_CPU1,
 		.flags	= IORESOURCE_IRQ,
 	},
 	[2] = {
 		.start	= IRQ_CT_CA9X4_PMU_CPU2,
 		.end	= IRQ_CT_CA9X4_PMU_CPU2,
 		.flags	= IORESOURCE_IRQ,
 	},
 	[3] = {
 		.start	= IRQ_CT_CA9X4_PMU_CPU3,
 		.end	= IRQ_CT_CA9X4_PMU_CPU3,
 		.flags	= IORESOURCE_IRQ,
 	},
 };
 static struct platform_device pmu_device = {
 	.name		= "arm-pmu",
 	.id		= ARM_PMU_DEVICE_CPU,
 	.num_resources	= ARRAY_SIZE(pmu_resources),
 	.resource	= pmu_resources,
 };
 static void __init ct_ca9x4_init_early(void)
 {
 	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 }
 static void __init ct_ca9x4_init(void)
 {
 	int i;
 #ifdef CONFIG_CACHE_L2X0
 	void __iomem *l2x0_base = MMIO_P2V(CT_CA9X4_L2CC);
 	/* set RAM latencies to 1 cycle for this core tile. */
 	writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
 	writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);
 	l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
 #endif
 	for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
 		amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
 	platform_device_register(&pmu_device);
 }
 #ifdef CONFIG_SMP
 static void ct_ca9x4_init_cpu_map(void)
 {
 	int i, ncores = scu_get_core_count(MMIO_P2V(A9_MPCORE_SCU));
 	for (i = 0; i < ncores; ++i)
 		set_cpu_possible(i, true);
+	set_smp_cross_call(gic_raise_softirq);
 }
 static void ct_ca9x4_smp_enable(unsigned int max_cpus)
 {
 	int i;
 	for (i = 0; i < max_cpus; i++)
 		set_cpu_present(i, true);
 	scu_enable(MMIO_P2V(A9_MPCORE_SCU));
 }
 #endif
 struct ct_desc ct_ca9x4_desc __initdata = {
 	.id		= V2M_CT_ID_CA9,
 	.name		= "CA9x4",
 	.map_io		= ct_ca9x4_map_io,
 	.init_early	= ct_ca9x4_init_early,
 	.init_irq	= ct_ca9x4_init_irq,
 	.init_tile	= ct_ca9x4_init,
 #ifdef CONFIG_SMP
 	.init_cpu_map	= ct_ca9x4_init_cpu_map,
 	.smp_enable	= ct_ca9x4_smp_enable,
 #endif
 };

arch/arm/mach-vexpress/include/mach/smp.h

View file @ 0f7b332

1	#ifndef __MACH_SMP_H		File was deleted
2	#define __MACH_SMP_H
3
4	#include <asm/hardware/gic.h>
5
6	/*
7	* We use IRQ1 as the IPI
8	*/
9	static inline void smp_cross_call(const struct cpumask *mask, int ipi)
10	{
11	gic_raise_softirq(mask, ipi);
12	}
13	#endif
14		1	#ifndef __MACH_SMP_H

arch/arm/plat-omap/include/plat/smp.h

View file @ 0f7b332

1	/*		File was deleted
2	* OMAP4 machine specific smp.h
3	*
4	* Copyright (C) 2009 Texas Instruments, Inc.
5	*
6	* Author:
7	* Santosh Shilimkar <santosh.shilimkar@ti.com>
8	*
9	* Interface functions needed for the SMP. This file is based on arm
10	* realview smp platform.
11	* Copyright (c) 2003 ARM Limited.
12	*
13	* This program is free software; you can redistribute it and/or modify
14	* it under the terms of the GNU General Public License version 2 as
15	* published by the Free Software Foundation.
16	*/
17	#ifndef OMAP_ARCH_SMP_H
18	#define OMAP_ARCH_SMP_H
19
20	#include <asm/hardware/gic.h>
21
22	/*
23	* We use Soft IRQ1 as the IPI
24	*/
25	static inline void smp_cross_call(const struct cpumask *mask, int ipi)
26	{
27	gic_raise_softirq(mask, ipi);
28	}
29
30	#endif
31		1	/*

arch/arm/plat-versatile/platsmp.c

Diff comments View file @ 0f7b332

 /*
  *  linux/arch/arm/plat-versatile/platsmp.c
  *
  *  Copyright (C) 2002 ARM Ltd.
  *  All Rights Reserved
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 #include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/jiffies.h>
 #include <linux/smp.h>
 #include <asm/cacheflush.h>
+#include <asm/hardware/gic.h>
 /*
  * control for which core is the next to come out of the secondary
  * boot "holding pen"
  */
 volatile int __cpuinitdata pen_release = -1;
 /*
  * Write pen_release in a way that is guaranteed to be visible to all
  * observers, irrespective of whether they're taking part in coherency
  * or not.  This is necessary for the hotplug code to work reliably.
  */
 static void __cpuinit write_pen_release(int val)
 {
 	pen_release = val;
 	smp_wmb();
 	__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
 	outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
 }
 static DEFINE_SPINLOCK(boot_lock);
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
 	/*
 	 * if any interrupts are already enabled for the primary
 	 * core (e.g. timer irq), then they will not have been enabled
 	 * for us: do so
 	 */
 	gic_secondary_init(0);
 	/*
 	 * let the primary processor know we're out of the
 	 * pen, then head off into the C entry point
 	 */
 	write_pen_release(-1);
 	/*
 	 * Synchronise with the boot thread.
 	 */
 	spin_lock(&boot_lock);
 	spin_unlock(&boot_lock);
 }
 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
 	unsigned long timeout;
 	/*
 	 * Set synchronisation state between this boot processor
 	 * and the secondary one
 	 */
 	spin_lock(&boot_lock);
 	/*
 	 * This is really belt and braces; we hold unintended secondary
 	 * CPUs in the holding pen until we're ready for them.  However,
 	 * since we haven't sent them a soft interrupt, they shouldn't
 	 * be there.
 	 */
 	write_pen_release(cpu);
 	/*
 	 * Send the secondary CPU a soft interrupt, thereby causing
 	 * the boot monitor to read the system wide flags register,
 	 * and branch to the address found there.
 	 */
-	smp_cross_call(cpumask_of(cpu), 1);
+	gic_raise_softirq(cpumask_of(cpu), 1);
 	timeout = jiffies + (1 * HZ);
 	while (time_before(jiffies, timeout)) {
 		smp_rmb();
 		if (pen_release == -1)
 			break;
 		udelay(10);
 	}
 	/*
 	 * now the secondary core is starting up let it run its
 	 * calibrations, then wait for it to finish
 	 */
 	spin_unlock(&boot_lock);
 	return pen_release != -1 ? -ENOSYS : 0;
 }