netdev: Merge UCC and gianfar MDIO bus drivers

The MDIO bus drivers for the UCC and gianfar ethernet controllers are essentially the same. There's no reason to duplicate that much code. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>

netdev: Merge UCC and gianfar MDIO bus drivers
The MDIO bus drivers for the UCC and gianfar ethernet controllers are essentially the same. There's no reason to duplicate that much code. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Andy Fleming · David S. Miller
1 parent 9c46f6d42f
Showing 12 changed files with 549 additions and 490 deletions Side-by-side Diff
drivers/net/Kconfig
drivers/net/Makefile
drivers/net/fsl_pq_mdio.c
drivers/net/fsl_pq_mdio.h
drivers/net/gianfar.c
drivers/net/gianfar.h
drivers/net/gianfar_mii.h
drivers/net/ucc_geth.c
drivers/net/ucc_geth.h
drivers/net/ucc_geth_ethtool.c
drivers/net/ucc_geth_mii.c
drivers/net/ucc_geth_mii.h
@@ -2272,9 +2272,17 @@
  
           If unsure, say N.
  
+config FSL_PQ_MDIO
+	tristate "Freescale PQ MDIO"
+	depends on FSL_SOC
+	select PHYLIB
+	help
+	  This driver supports the MDIO bus used by the gianfar and UCC drivers.
+
 config GIANFAR
 	tristate "Gianfar Ethernet"
 	depends on FSL_SOC
+	select FSL_PQ_MDIO
 	select PHYLIB
 	select CRC32
 	help
@@ -2284,6 +2292,7 @@
 config UCC_GETH
 	tristate "Freescale QE Gigabit Ethernet"
 	depends on QUICC_ENGINE
+	select FSL_PQ_MDIO
 	select PHYLIB
 	help
 	  This driver supports the Gigabit Ethernet mode of the QUICC Engine,
@@ -24,11 +24,12 @@
  
 gianfar_driver-objs := gianfar.o \
 		gianfar_ethtool.o \
-		gianfar_mii.o \
 		gianfar_sysfs.o
  
 obj-$(CONFIG_UCC_GETH) += ucc_geth_driver.o
-ucc_geth_driver-objs := ucc_geth.o ucc_geth_mii.o ucc_geth_ethtool.o
+ucc_geth_driver-objs := ucc_geth.o ucc_geth_ethtool.o
+
+obj-$(CONFIG_FSL_PQ_MDIO) += fsl_pq_mdio.o
  
 #
 # link order important here
+/*
+ * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation
+ * Provides Bus interface for MIIM regs
+ *
+ * Author: Andy Fleming <afleming@freescale.com>
+ *
+ * Copyright (c) 2002-2004,2008 Freescale Semiconductor, Inc.
+ *
+ * Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips)
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/errno.h>
+#include <linux/unistd.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/spinlock.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/crc32.h>
+#include <linux/mii.h>
+#include <linux/phy.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+#include <asm/ucc.h>
+
+#include "gianfar.h"
+#include "fsl_pq_mdio.h"
+
+/*
+ * Write value to the PHY at mii_id at register regnum,
+ * on the bus attached to the local interface, which may be different from the
+ * generic mdio bus (tied to a single interface), waiting until the write is
+ * done before returning. This is helpful in programming interfaces like
+ * the TBI which control interfaces like onchip SERDES and are always tied to
+ * the local mdio pins, which may not be the same as system mdio bus, used for
+ * controlling the external PHYs, for example.
+ */
+int fsl_pq_local_mdio_write(struct fsl_pq_mdio __iomem *regs, int mii_id,
+		int regnum, u16 value)
+{
+	/* Set the PHY address and the register address we want to write */
+	out_be32(&regs->miimadd, (mii_id << 8) | regnum);
+
+	/* Write out the value we want */
+	out_be32(&regs->miimcon, value);
+
+	/* Wait for the transaction to finish */
+	while (in_be32(&regs->miimind) & MIIMIND_BUSY)
+		cpu_relax();
+
+	return 0;
+}
+
+/*
+ * Read the bus for PHY at addr mii_id, register regnum, and
+ * return the value.  Clears miimcom first.  All PHY operation
+ * done on the bus attached to the local interface,
+ * which may be different from the generic mdio bus
+ * This is helpful in programming interfaces like
+ * the TBI which, in turn, control interfaces like onchip SERDES
+ * and are always tied to the local mdio pins, which may not be the
+ * same as system mdio bus, used for controlling the external PHYs, for eg.
+ */
+int fsl_pq_local_mdio_read(struct fsl_pq_mdio __iomem *regs,
+		int mii_id, int regnum)
+{
+	u16 value;
+
+	/* Set the PHY address and the register address we want to read */
+	out_be32(&regs->miimadd, (mii_id << 8) | regnum);
+
+	/* Clear miimcom, and then initiate a read */
+	out_be32(&regs->miimcom, 0);
+	out_be32(&regs->miimcom, MII_READ_COMMAND);
+
+	/* Wait for the transaction to finish */
+	while (in_be32(&regs->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY))
+		cpu_relax();
+
+	/* Grab the value of the register from miimstat */
+	value = in_be32(&regs->miimstat);
+
+	return value;
+}
+
+/*
+ * Write value to the PHY at mii_id at register regnum,
+ * on the bus, waiting until the write is done before returning.
+ */
+int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value)
+{
+	struct fsl_pq_mdio __iomem *regs = (void __iomem *)bus->priv;
+
+	/* Write to the local MII regs */
+	return(fsl_pq_local_mdio_write(regs, mii_id, regnum, value));
+}
+
+/*
+ * Read the bus for PHY at addr mii_id, register regnum, and
+ * return the value.  Clears miimcom first.
+ */
+int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
+{
+	struct fsl_pq_mdio __iomem *regs = (void __iomem *)bus->priv;
+
+	/* Read the local MII regs */
+	return(fsl_pq_local_mdio_read(regs, mii_id, regnum));
+}
+
+/* Reset the MIIM registers, and wait for the bus to free */
+static int fsl_pq_mdio_reset(struct mii_bus *bus)
+{
+	struct fsl_pq_mdio __iomem *regs = (void __iomem *)bus->priv;
+	unsigned int timeout = PHY_INIT_TIMEOUT;
+
+	mutex_lock(&bus->mdio_lock);
+
+	/* Reset the management interface */
+	out_be32(&regs->miimcfg, MIIMCFG_RESET);
+
+	/* Setup the MII Mgmt clock speed */
+	out_be32(&regs->miimcfg, MIIMCFG_INIT_VALUE);
+
+	/* Wait until the bus is free */
+	while ((in_be32(&regs->miimind) & MIIMIND_BUSY) && timeout--)
+		cpu_relax();
+
+	mutex_unlock(&bus->mdio_lock);
+
+	if(timeout == 0) {
+		printk(KERN_ERR "%s: The MII Bus is stuck!\n",
+				bus->name);
+		return -EBUSY;
+	}
+
+	return 0;
+}
+
+/* Allocate an array which provides irq #s for each PHY on the given bus */
+static int *create_irq_map(struct device_node *np)
+{
+	int *irqs;
+	int i;
+	struct device_node *child = NULL;
+
+	irqs = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
+
+	if (!irqs)
+		return NULL;
+
+	for (i = 0; i < PHY_MAX_ADDR; i++)
+		irqs[i] = PHY_POLL;
+
+	while ((child = of_get_next_child(np, child)) != NULL) {
+		int irq = irq_of_parse_and_map(child, 0);
+		const u32 *id;
+
+		if (irq == NO_IRQ)
+			continue;
+
+		id = of_get_property(child, "reg", NULL);
+
+		if (!id)
+			continue;
+
+		if (*id < PHY_MAX_ADDR && *id >= 0)
+			irqs[*id] = irq;
+		else
+			printk(KERN_WARNING "%s: "
+					"%d is not a valid PHY address\n",
+					np->full_name, *id);
+	}
+
+	return irqs;
+}
+
+void fsl_pq_mdio_bus_name(char *name, struct device_node *np)
+{
+	const u32 *reg;
+
+	reg = of_get_property(np, "reg", NULL);
+
+	snprintf(name, MII_BUS_ID_SIZE, "%s@%x", np->name, reg ? *reg : 0);
+}
+
+/* Scan the bus in reverse, looking for an empty spot */
+static int fsl_pq_mdio_find_free(struct mii_bus *new_bus)
+{
+	int i;
+
+	for (i = PHY_MAX_ADDR; i > 0; i--) {
+		u32 phy_id;
+
+		if (get_phy_id(new_bus, i, &phy_id))
+			return -1;
+
+		if (phy_id == 0xffffffff)
+			break;
+	}
+
+	return i;
+}
+
+
+#ifdef CONFIG_GIANFAR
+static u32 __iomem *get_gfar_tbipa(struct fsl_pq_mdio __iomem *regs)
+{
+	struct gfar __iomem *enet_regs;
+
+	/*
+	 * This is mildly evil, but so is our hardware for doing this.
+	 * Also, we have to cast back to struct gfar because of
+	 * definition weirdness done in gianfar.h.
+	 */
+	enet_regs = (struct gfar __iomem *)
+		((char __iomem *)regs - offsetof(struct gfar, gfar_mii_regs));
+
+	return &enet_regs->tbipa;
+}
+#endif
+
+
+#ifdef CONFIG_UCC_GETH
+static int get_ucc_id_for_range(u64 start, u64 end, u32 *ucc_id)
+{
+	struct device_node *np = NULL;
+	int err = 0;
+
+	for_each_compatible_node(np, NULL, "ucc_geth") {
+		struct resource tempres;
+
+		err = of_address_to_resource(np, 0, &tempres);
+		if (err)
+			continue;
+
+		/* if our mdio regs fall within this UCC regs range */
+		if ((start >= tempres.start) && (end <= tempres.end)) {
+			/* Find the id of the UCC */
+			const u32 *id;
+
+			id = of_get_property(np, "cell-index", NULL);
+			if (!id) {
+				id = of_get_property(np, "device-id", NULL);
+				if (!id)
+					continue;
+			}
+
+			*ucc_id = *id;
+
+			return 0;
+		}
+	}
+
+	if (err)
+		return err;
+	else
+		return -EINVAL;
+}
+#endif
+
+
+static int fsl_pq_mdio_probe(struct of_device *ofdev,
+		const struct of_device_id *match)
+{
+	struct device_node *np = ofdev->node;
+	struct device_node *tbi;
+	struct fsl_pq_mdio __iomem *regs;
+	u32 __iomem *tbipa;
+	struct mii_bus *new_bus;
+	int tbiaddr = -1;
+	u64 addr, size;
+	int err = 0;
+
+	new_bus = mdiobus_alloc();
+	if (NULL == new_bus)
+		return -ENOMEM;
+
+	new_bus->name = "Freescale PowerQUICC MII Bus",
+	new_bus->read = &fsl_pq_mdio_read,
+	new_bus->write = &fsl_pq_mdio_write,
+	new_bus->reset = &fsl_pq_mdio_reset,
+	fsl_pq_mdio_bus_name(new_bus->id, np);
+
+	/* Set the PHY base address */
+	addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
+	regs = ioremap(addr, size);
+
+	if (NULL == regs) {
+		err = -ENOMEM;
+		goto err_free_bus;
+	}
+
+	new_bus->priv = (void __force *)regs;
+
+	new_bus->irq = create_irq_map(np);
+
+	if (NULL == new_bus->irq) {
+		err = -ENOMEM;
+		goto err_unmap_regs;
+	}
+
+	new_bus->parent = &ofdev->dev;
+	dev_set_drvdata(&ofdev->dev, new_bus);
+
+	if (of_device_is_compatible(np, "fsl,gianfar-mdio") ||
+			of_device_is_compatible(np, "gianfar")) {
+#ifdef CONFIG_GIANFAR
+		tbipa = get_gfar_tbipa(regs);
+#else
+		err = -ENODEV;
+		goto err_free_irqs;
+#endif
+	} else if (of_device_is_compatible(np, "fsl,ucc-mdio") ||
+			of_device_is_compatible(np, "ucc_geth_phy")) {
+#ifdef CONFIG_UCC_GETH
+		u32 id;
+
+		tbipa = &regs->utbipar;
+
+		if ((err = get_ucc_id_for_range(addr, addr + size, &id)))
+			goto err_free_irqs;
+
+		ucc_set_qe_mux_mii_mng(id - 1);
+#else
+		err = -ENODEV;
+		goto err_free_irqs;
+#endif
+	} else {
+		err = -ENODEV;
+		goto err_free_irqs;
+	}
+
+	for_each_child_of_node(np, tbi) {
+		if (!strncmp(tbi->type, "tbi-phy", 8))
+			break;
+	}
+
+	if (tbi) {
+		const u32 *prop = of_get_property(tbi, "reg", NULL);
+
+		if (prop)
+			tbiaddr = *prop;
+	}
+
+	if (tbiaddr == -1) {
+		out_be32(tbipa, 0);
+
+		tbiaddr = fsl_pq_mdio_find_free(new_bus);
+	}
+
+	/*
+	 * We define TBIPA at 0 to be illegal, opting to fail for boards that
+	 * have PHYs at 1-31, rather than change tbipa and rescan.
+	 */
+	if (tbiaddr == 0) {
+		err = -EBUSY;
+
+		goto err_free_irqs;
+	}
+
+	out_be32(tbipa, tbiaddr);
+
+	/*
+	 * The TBIPHY-only buses will find PHYs at every address,
+	 * so we mask them all but the TBI
+	 */
+	if (!of_device_is_compatible(np, "fsl,gianfar-mdio"))
+		new_bus->phy_mask = ~(1 << tbiaddr);
+
+	err = mdiobus_register(new_bus);
+
+	if (err) {
+		printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
+				new_bus->name);
+		goto err_free_irqs;
+	}
+
+	return 0;
+
+err_free_irqs:
+	kfree(new_bus->irq);
+err_unmap_regs:
+	iounmap(regs);
+err_free_bus:
+	kfree(new_bus);
+
+	return err;
+}
+
+
+static int fsl_pq_mdio_remove(struct of_device *ofdev)
+{
+	struct device *device = &ofdev->dev;
+	struct mii_bus *bus = dev_get_drvdata(device);
+
+	mdiobus_unregister(bus);
+
+	dev_set_drvdata(device, NULL);
+
+	iounmap((void __iomem *)bus->priv);
+	bus->priv = NULL;
+	mdiobus_free(bus);
+
+	return 0;
+}
+
+static struct of_device_id fsl_pq_mdio_match[] = {
+	{
+		.type = "mdio",
+		.compatible = "ucc_geth_phy",
+	},
+	{
+		.type = "mdio",
+		.compatible = "gianfar",
+	},
+	{
+		.compatible = "fsl,ucc-mdio",
+	},
+	{
+		.compatible = "fsl,gianfar-tbi",
+	},
+	{
+		.compatible = "fsl,gianfar-mdio",
+	},
+	{},
+};
+
+static struct of_platform_driver fsl_pq_mdio_driver = {
+	.name = "fsl-pq_mdio",
+	.probe = fsl_pq_mdio_probe,
+	.remove = fsl_pq_mdio_remove,
+	.match_table = fsl_pq_mdio_match,
+};
+
+int __init fsl_pq_mdio_init(void)
+{
+	return of_register_platform_driver(&fsl_pq_mdio_driver);
+}
+
+void fsl_pq_mdio_exit(void)
+{
+	of_unregister_platform_driver(&fsl_pq_mdio_driver);
+}
+subsys_initcall_sync(fsl_pq_mdio_init);
+module_exit(fsl_pq_mdio_exit);
+/*
+ * Freescale PowerQUICC MDIO Driver -- MII Management Bus Implementation
+ * Driver for the MDIO bus controller on Freescale PowerQUICC processors
+ *
+ * Author: Andy Fleming
+ *
+ * Copyright (c) 2002-2004,2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+#ifndef __FSL_PQ_MDIO_H
+#define __FSL_PQ_MDIO_H
+
+#define MIIMIND_BUSY            0x00000001
+#define MIIMIND_NOTVALID        0x00000004
+#define MIIMCFG_INIT_VALUE	0x00000007
+#define MIIMCFG_RESET           0x80000000
+
+#define MII_READ_COMMAND       0x00000001
+
+struct fsl_pq_mdio {
+	u32 miimcfg;		/* MII management configuration reg */
+	u32 miimcom;		/* MII management command reg */
+	u32 miimadd;		/* MII management address reg */
+	u32 miimcon;		/* MII management control reg */
+	u32 miimstat;		/* MII management status reg */
+	u32 miimind;		/* MII management indication reg */
+	u8 reserved[28];	/* Space holder */
+	u32 utbipar;		/* TBI phy address reg (only on UCC) */
+} __attribute__ ((packed));
+
+
+int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum);
+int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value);
+int fsl_pq_local_mdio_write(struct fsl_pq_mdio __iomem *regs, int mii_id,
+			  int regnum, u16 value);
+int fsl_pq_local_mdio_read(struct fsl_pq_mdio __iomem *regs, int mii_id, int regnum);
+int __init fsl_pq_mdio_init(void);
+void fsl_pq_mdio_exit(void);
+void fsl_pq_mdio_bus_name(char *name, struct device_node *np);
+#endif /* FSL_PQ_MDIO_H */
@@ -93,7 +93,7 @@
 #include <linux/of.h>
  
 #include "gianfar.h"
-#include "gianfar_mii.h"
+#include "fsl_pq_mdio.h"
  
 #define TX_TIMEOUT      (1*HZ)
 #undef BRIEF_GFAR_ERRORS
@@ -253,7 +253,7 @@
 		of_node_put(phy);
 		of_node_put(mdio);
  
-		gfar_mdio_bus_name(bus_name, mdio);
+		fsl_pq_mdio_bus_name(bus_name, mdio);
 		snprintf(priv->phy_bus_id, sizeof(priv->phy_bus_id), "%s:%02x",
 				bus_name, *id);
 	}
@@ -420,7 +420,7 @@
 		priv->hash_width = 8;
  
 		priv->hash_regs[0] = &priv->regs->gaddr0;
-                priv->hash_regs[1] = &priv->regs->gaddr1;
+		priv->hash_regs[1] = &priv->regs->gaddr1;
 		priv->hash_regs[2] = &priv->regs->gaddr2;
 		priv->hash_regs[3] = &priv->regs->gaddr3;
 		priv->hash_regs[4] = &priv->regs->gaddr4;
@@ -836,7 +836,7 @@
 		free_irq(priv->interruptTransmit, dev);
 		free_irq(priv->interruptReceive, dev);
 	} else {
- 		free_irq(priv->interruptTransmit, dev);
+		free_irq(priv->interruptTransmit, dev);
 	}
  
 	free_skb_resources(priv);
@@ -1829,6 +1829,8 @@
 				skb_put(skb, pkt_len);
 				dev->stats.rx_bytes += pkt_len;
  
+				if (in_irq() || irqs_disabled())
+					printk("Interrupt problem!\n");
 				gfar_process_frame(dev, skb, amount_pull);
  
 			} else {
  
@@ -2302,23 +2304,12 @@
  
 static int __init gfar_init(void)
 {
-	int err = gfar_mdio_init();
-
-	if (err)
-		return err;
-
-	err = of_register_platform_driver(&gfar_driver);
-
-	if (err)
-		gfar_mdio_exit();
-
-	return err;
+	return of_register_platform_driver(&gfar_driver);
 }
  
 static void __exit gfar_exit(void)
 {
 	of_unregister_platform_driver(&gfar_driver);
-	gfar_mdio_exit();
 }
  
 module_init(gfar_init);
@@ -46,7 +46,6 @@
 #include <linux/workqueue.h>
 #include <linux/ethtool.h>
 #include <linux/fsl_devices.h>
-#include "gianfar_mii.h"
  
 /* The maximum number of packets to be handled in one call of gfar_poll */
 #define GFAR_DEV_WEIGHT 64
@@ -126,9 +125,12 @@
 #define DEFAULT_RX_COALESCE 0
 #define DEFAULT_RXCOUNT	0
  
-#define MIIMCFG_INIT_VALUE	0x00000007
-#define MIIMCFG_RESET           0x80000000
-#define MIIMIND_BUSY            0x00000001
+#define GFAR_SUPPORTED (SUPPORTED_10baseT_Half \
+		| SUPPORTED_10baseT_Full \
+		| SUPPORTED_100baseT_Half \
+		| SUPPORTED_100baseT_Full \
+		| SUPPORTED_Autoneg \
+		| SUPPORTED_MII)
  
 /* TBI register addresses */
 #define MII_TBICON		0x11
@@ -826,9 +828,6 @@
 extern void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev,
 		int enable, u32 regnum, u32 read);
 void gfar_init_sysfs(struct net_device *dev);
-int gfar_local_mdio_write(struct gfar_mii __iomem *regs, int mii_id,
-			  int regnum, u16 value);
-int gfar_local_mdio_read(struct gfar_mii __iomem *regs, int mii_id, int regnum);
  
 extern const struct ethtool_ops gfar_ethtool_ops;
  
-/*
- * drivers/net/gianfar_mii.h
- *
- * Gianfar Ethernet Driver -- MII Management Bus Implementation
- * Driver for the MDIO bus controller in the Gianfar register space
- *
- * Author: Andy Fleming
- * Maintainer: Kumar Gala
- *
- * Copyright (c) 2002-2004 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-#ifndef __GIANFAR_MII_H
-#define __GIANFAR_MII_H
-
-struct gfar_private; /* forward ref */
-
-#define MIIMIND_BUSY            0x00000001
-#define MIIMIND_NOTVALID        0x00000004
-
-#define MII_READ_COMMAND       0x00000001
-
-#define GFAR_SUPPORTED (SUPPORTED_10baseT_Half \
-		| SUPPORTED_10baseT_Full \
-		| SUPPORTED_100baseT_Half \
-		| SUPPORTED_100baseT_Full \
-		| SUPPORTED_Autoneg \
-		| SUPPORTED_MII)
-
-struct gfar_mii {
-	u32	miimcfg;	/* 0x.520 - MII Management Config Register */
-	u32	miimcom;	/* 0x.524 - MII Management Command Register */
-	u32	miimadd;	/* 0x.528 - MII Management Address Register */
-	u32	miimcon;	/* 0x.52c - MII Management Control Register */
-	u32	miimstat;	/* 0x.530 - MII Management Status Register */
-	u32	miimind;	/* 0x.534 - MII Management Indicator Register */
-};
-
-int gfar_mdio_read(struct mii_bus *bus, int mii_id, int regnum);
-int gfar_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value);
-int gfar_local_mdio_write(struct gfar_mii __iomem *regs, int mii_id,
-			  int regnum, u16 value);
-int gfar_local_mdio_read(struct gfar_mii __iomem *regs, int mii_id, int regnum);
-struct mii_bus *gfar_get_miibus(const struct gfar_private *priv);
-int __init gfar_mdio_init(void);
-void gfar_mdio_exit(void);
-
-void gfar_mdio_bus_name(char *name, struct device_node *np);
-#endif /* GIANFAR_PHY_H */
@@ -39,7 +39,7 @@
 #include <asm/ucc_fast.h>
  
 #include "ucc_geth.h"
-#include "ucc_geth_mii.h"
+#include "fsl_pq_mdio.h"
  
 #undef DEBUG
  
@@ -1557,7 +1557,7 @@
 	of_node_put(phy);
 	of_node_put(mdio);
  
-	uec_mdio_bus_name(bus_name, mdio);
+	fsl_pq_mdio_bus_name(bus_name, mdio);
 	snprintf(phy_id, sizeof(phy_id), "%s:%02x",
                                 bus_name, *id);
  
@@ -3657,7 +3657,8 @@
 		if (err)
 			return -1;
  
-		snprintf(ug_info->mdio_bus, MII_BUS_ID_SIZE, "%x", res.start);
+		snprintf(ug_info->mdio_bus, MII_BUS_ID_SIZE, "%x",
+				res.start&0xfffff);
 	}
  
 	/* get the phy interface type, or default to MII */
@@ -3803,11 +3804,6 @@
 {
 	int i, ret;
  
-	ret = uec_mdio_init();
-
-	if (ret)
-		return ret;
-
 	if (netif_msg_drv(&debug))
 		printk(KERN_INFO "ucc_geth: " DRV_DESC "\n");
 	for (i = 0; i < 8; i++)
  
@@ -3816,16 +3812,12 @@
  
 	ret = of_register_platform_driver(&ucc_geth_driver);
  
-	if (ret)
-		uec_mdio_exit();
-
 	return ret;
 }
  
 static void __exit ucc_geth_exit(void)
 {
 	of_unregister_platform_driver(&ucc_geth_driver);
-	uec_mdio_exit();
 }
  
 module_init(ucc_geth_init);
@@ -28,8 +28,6 @@
 #include <asm/ucc.h>
 #include <asm/ucc_fast.h>
  
-#include "ucc_geth_mii.h"
-
 #define DRV_DESC "QE UCC Gigabit Ethernet Controller"
 #define DRV_NAME "ucc_geth"
 #define DRV_VERSION "1.1"
@@ -183,6 +181,18 @@
  
 #define UCCE_RX_EVENTS  (UCCE_RXF | UCC_GETH_UCCE_BSY)
 #define UCCE_TX_EVENTS	(UCCE_TXB | UCC_GETH_UCCE_TXE)
+
+/* TBI defines */
+#define	ENET_TBI_MII_CR		0x00	/* Control */
+#define	ENET_TBI_MII_SR		0x01	/* Status */
+#define	ENET_TBI_MII_ANA	0x04	/* AN advertisement */
+#define	ENET_TBI_MII_ANLPBPA	0x05	/* AN link partner base page ability */
+#define	ENET_TBI_MII_ANEX	0x06	/* AN expansion */
+#define	ENET_TBI_MII_ANNPT	0x07	/* AN next page transmit */
+#define	ENET_TBI_MII_ANLPANP	0x08	/* AN link partner ability next page */
+#define	ENET_TBI_MII_EXST	0x0F	/* Extended status */
+#define	ENET_TBI_MII_JD		0x10	/* Jitter diagnostics */
+#define	ENET_TBI_MII_TBICON	0x11	/* TBI control */
  
 /* UCC GETH MACCFG1 (MAC Configuration 1 Register) */
 #define MACCFG1_FLOW_RX                         0x00000020	/* Flow Control
@@ -39,7 +39,6 @@
 #include <asm/types.h>
  
 #include "ucc_geth.h"
-#include "ucc_geth_mii.h"
  
 static char hw_stat_gstrings[][ETH_GSTRING_LEN] = {
 	"tx-64-frames",
-/*
- * drivers/net/ucc_geth_mii.c
- *
- * QE UCC Gigabit Ethernet Driver -- MII Management Bus Implementation
- * Provides Bus interface for MII Management regs in the UCC register space
- *
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- *
- * Authors: Li Yang <leoli@freescale.com>
- *	    Kim Phillips <kim.phillips@freescale.com>
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/string.h>
-#include <linux/errno.h>
-#include <linux/unistd.h>
-#include <linux/slab.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/netdevice.h>
-#include <linux/etherdevice.h>
-#include <linux/skbuff.h>
-#include <linux/spinlock.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/crc32.h>
-#include <linux/mii.h>
-#include <linux/phy.h>
-#include <linux/fsl_devices.h>
-#include <linux/of_platform.h>
-
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/uaccess.h>
-#include <asm/ucc.h>
-
-#include "ucc_geth_mii.h"
-#include "ucc_geth.h"
-
-#define DEBUG
-#ifdef DEBUG
-#define vdbg(format, arg...) printk(KERN_DEBUG , format "\n" , ## arg)
-#else
-#define vdbg(format, arg...) do {} while(0)
-#endif
-
-#define MII_DRV_DESC "QE UCC Ethernet Controller MII Bus"
-#define MII_DRV_NAME "fsl-uec_mdio"
-
-/* Write value to the PHY for this device to the register at regnum, */
-/* waiting until the write is done before it returns.  All PHY */
-/* configuration has to be done through the master UEC MIIM regs */
-int uec_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value)
-{
-	struct ucc_mii_mng __iomem *regs = (void __iomem *)bus->priv;
-
-	/* Setting up the MII Mangement Address Register */
-	out_be32(&regs->miimadd,
-		 (mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | regnum);
-
-	/* Setting up the MII Mangement Control Register with the value */
-	out_be32(&regs->miimcon, value);
-
-	/* Wait till MII management write is complete */
-	while ((in_be32(&regs->miimind)) & MIIMIND_BUSY)
-		cpu_relax();
-
-	return 0;
-}
-
-/* Reads from register regnum in the PHY for device dev, */
-/* returning the value.  Clears miimcom first.  All PHY */
-/* configuration has to be done through the TSEC1 MIIM regs */
-int uec_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
-{
-	struct ucc_mii_mng __iomem *regs = (void __iomem *)bus->priv;
-	u16 value;
-
-	/* Setting up the MII Mangement Address Register */
-	out_be32(&regs->miimadd,
-		 (mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | regnum);
-
-	/* Clear miimcom, perform an MII management read cycle */
-	out_be32(&regs->miimcom, 0);
-	out_be32(&regs->miimcom, MIIMCOM_READ_CYCLE);
-
-	/* Wait till MII management write is complete */
-	while ((in_be32(&regs->miimind)) & (MIIMIND_BUSY | MIIMIND_NOT_VALID))
-		cpu_relax();
-
-	/* Read MII management status  */
-	value = in_be32(&regs->miimstat);
-
-	return value;
-}
-
-/* Reset the MIIM registers, and wait for the bus to free */
-static int uec_mdio_reset(struct mii_bus *bus)
-{
-	struct ucc_mii_mng __iomem *regs = (void __iomem *)bus->priv;
-	unsigned int timeout = PHY_INIT_TIMEOUT;
-
-	mutex_lock(&bus->mdio_lock);
-
-	/* Reset the management interface */
-	out_be32(&regs->miimcfg, MIIMCFG_RESET_MANAGEMENT);
-
-	/* Setup the MII Mgmt clock speed */
-	out_be32(&regs->miimcfg, MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_112);
-
-	/* Wait until the bus is free */
-	while ((in_be32(&regs->miimind) & MIIMIND_BUSY) && timeout--)
-		cpu_relax();
-
-	mutex_unlock(&bus->mdio_lock);
-
-	if (timeout <= 0) {
-		printk(KERN_ERR "%s: The MII Bus is stuck!\n", bus->name);
-		return -EBUSY;
-	}
-
-	return 0;
-}
-
-static int uec_mdio_probe(struct of_device *ofdev, const struct of_device_id *match)
-{
-	struct device *device = &ofdev->dev;
-	struct device_node *np = ofdev->node, *tempnp = NULL;
-	struct device_node *child = NULL;
-	struct ucc_mii_mng __iomem *regs;
-	struct mii_bus *new_bus;
-	struct resource res;
-	int k, err = 0;
-
-	new_bus = mdiobus_alloc();
-	if (NULL == new_bus)
-		return -ENOMEM;
-
-	new_bus->name = "UCC Ethernet Controller MII Bus";
-	new_bus->read = &uec_mdio_read;
-	new_bus->write = &uec_mdio_write;
-	new_bus->reset = &uec_mdio_reset;
-
-	memset(&res, 0, sizeof(res));
-
-	err = of_address_to_resource(np, 0, &res);
-	if (err)
-		goto reg_map_fail;
-
-	uec_mdio_bus_name(new_bus->id, np);
-
-	new_bus->irq = kmalloc(32 * sizeof(int), GFP_KERNEL);
-
-	if (NULL == new_bus->irq) {
-		err = -ENOMEM;
-		goto reg_map_fail;
-	}
-
-	for (k = 0; k < 32; k++)
-		new_bus->irq[k] = PHY_POLL;
-
-	while ((child = of_get_next_child(np, child)) != NULL) {
-		int irq = irq_of_parse_and_map(child, 0);
-		if (irq != NO_IRQ) {
-			const u32 *id = of_get_property(child, "reg", NULL);
-			new_bus->irq[*id] = irq;
-		}
-	}
-
-	/* Set the base address */
-	regs = ioremap(res.start, sizeof(struct ucc_mii_mng));
-
-	if (NULL == regs) {
-		err = -ENOMEM;
-		goto ioremap_fail;
-	}
-
-	new_bus->priv = (void __force *)regs;
-
-	new_bus->parent = device;
-	dev_set_drvdata(device, new_bus);
-
-	/* Read MII management master from device tree */
-	while ((tempnp = of_find_compatible_node(tempnp, "network", "ucc_geth"))
-	       != NULL) {
-		struct resource tempres;
-
-		err = of_address_to_resource(tempnp, 0, &tempres);
-		if (err)
-			goto bus_register_fail;
-
-		/* if our mdio regs fall within this UCC regs range */
-		if ((res.start >= tempres.start) &&
-		    (res.end <= tempres.end)) {
-			/* set this UCC to be the MII master */
-			const u32 *id;
-
-			id = of_get_property(tempnp, "cell-index", NULL);
-			if (!id) {
-				id = of_get_property(tempnp, "device-id", NULL);
-				if (!id)
-					goto bus_register_fail;
-			}
-
-			ucc_set_qe_mux_mii_mng(*id - 1);
-
-			/* assign the TBI an address which won't
-			 * conflict with the PHYs */
-			out_be32(&regs->utbipar, UTBIPAR_INIT_TBIPA);
-			break;
-		}
-	}
-
-	err = mdiobus_register(new_bus);
-	if (0 != err) {
-		printk(KERN_ERR "%s: Cannot register as MDIO bus\n",
-		       new_bus->name);
-		goto bus_register_fail;
-	}
-
-	return 0;
-
-bus_register_fail:
-	iounmap(regs);
-ioremap_fail:
-	kfree(new_bus->irq);
-reg_map_fail:
-	mdiobus_free(new_bus);
-
-	return err;
-}
-
-static int uec_mdio_remove(struct of_device *ofdev)
-{
-	struct device *device = &ofdev->dev;
-	struct mii_bus *bus = dev_get_drvdata(device);
-
-	mdiobus_unregister(bus);
-
-	dev_set_drvdata(device, NULL);
-
-	iounmap((void __iomem *)bus->priv);
-	bus->priv = NULL;
-	mdiobus_free(bus);
-
-	return 0;
-}
-
-static struct of_device_id uec_mdio_match[] = {
-	{
-		.type = "mdio",
-		.compatible = "ucc_geth_phy",
-	},
-	{
-		.compatible = "fsl,ucc-mdio",
-	},
-	{},
-};
-
-static struct of_platform_driver uec_mdio_driver = {
-	.name	= MII_DRV_NAME,
-	.probe	= uec_mdio_probe,
-	.remove	= uec_mdio_remove,
-	.match_table	= uec_mdio_match,
-};
-
-int __init uec_mdio_init(void)
-{
-	return of_register_platform_driver(&uec_mdio_driver);
-}
-
-/* called from __init ucc_geth_init, therefore can not be __exit */
-void uec_mdio_exit(void)
-{
-	of_unregister_platform_driver(&uec_mdio_driver);
-}
-
-void uec_mdio_bus_name(char *name, struct device_node *np)
-{
-        const u32 *reg;
-
-        reg = of_get_property(np, "reg", NULL);
-
-        snprintf(name, MII_BUS_ID_SIZE, "%s@%x", np->name, reg ? *reg : 0);
-}
-/*
- * drivers/net/ucc_geth_mii.h
- *
- * QE UCC Gigabit Ethernet Driver -- MII Management Bus Implementation
- * Provides Bus interface for MII Management regs in the UCC register space
- *
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- *
- * Authors: Li Yang <leoli@freescale.com>
- *	    Kim Phillips <kim.phillips@freescale.com>
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-#ifndef __UEC_MII_H
-#define __UEC_MII_H
-
-/* UCC GETH MIIMCFG (MII Management Configuration Register) */
-#define MIIMCFG_RESET_MANAGEMENT                0x80000000	/* Reset
-								   management */
-#define MIIMCFG_NO_PREAMBLE                     0x00000010	/* Preamble
-								   suppress */
-#define MIIMCFG_CLOCK_DIVIDE_SHIFT              (31 - 31)	/* clock divide
-								   << shift */
-#define MIIMCFG_CLOCK_DIVIDE_MAX                0xf	/* max clock divide */
-#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_2    0x00000000
-#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_4    0x00000001
-#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_6    0x00000002
-#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_8    0x00000003
-#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10   0x00000004
-#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_14   0x00000005
-#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_16   0x00000008
-#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_20   0x00000006
-#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_28   0x00000007
-#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_32   0x00000009
-#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_48   0x0000000a
-#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_64   0x0000000b
-#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_80   0x0000000c
-#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_112  0x0000000d
-#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_160  0x0000000e
-#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_224  0x0000000f
-
-/* UCC GETH MIIMCOM (MII Management Command Register) */
-#define MIIMCOM_SCAN_CYCLE                      0x00000002	/* Scan cycle */
-#define MIIMCOM_READ_CYCLE                      0x00000001	/* Read cycle */
-
-/* UCC GETH MIIMADD (MII Management Address Register) */
-#define MIIMADD_PHY_ADDRESS_SHIFT               (31 - 23)	/* PHY Address
-								   << shift */
-#define MIIMADD_PHY_REGISTER_SHIFT              (31 - 31)	/* PHY Register
-								   << shift */
-
-/* UCC GETH MIIMCON (MII Management Control Register) */
-#define MIIMCON_PHY_CONTROL_SHIFT               (31 - 31)	/* PHY Control
-								   << shift */
-#define MIIMCON_PHY_STATUS_SHIFT                (31 - 31)	/* PHY Status
-								   << shift */
-
-/* UCC GETH MIIMIND (MII Management Indicator Register) */
-#define MIIMIND_NOT_VALID                       0x00000004	/* Not valid */
-#define MIIMIND_SCAN                            0x00000002	/* Scan in
-								   progress */
-#define MIIMIND_BUSY                            0x00000001
-
-/* Initial TBI Physical Address */
-#define UTBIPAR_INIT_TBIPA			0x1f
-
-struct ucc_mii_mng {
-	u32 miimcfg;		/* MII management configuration reg */
-	u32 miimcom;		/* MII management command reg */
-	u32 miimadd;		/* MII management address reg */
-	u32 miimcon;		/* MII management control reg */
-	u32 miimstat;		/* MII management status reg */
-	u32 miimind;		/* MII management indication reg */
-	u8 notcare[28];		/* Space holder */
-	u32 utbipar;		/* TBI phy address reg */
-} __attribute__ ((packed));
-
-/* TBI / MII Set Register */
-enum enet_tbi_mii_reg {
-	ENET_TBI_MII_CR = 0x00,	/* Control */
-	ENET_TBI_MII_SR = 0x01,	/* Status */
-	ENET_TBI_MII_ANA = 0x04,	/* AN advertisement */
-	ENET_TBI_MII_ANLPBPA = 0x05,	/* AN link partner base page ability */
-	ENET_TBI_MII_ANEX = 0x06,	/* AN expansion */
-	ENET_TBI_MII_ANNPT = 0x07,	/* AN next page transmit */
-	ENET_TBI_MII_ANLPANP = 0x08,	/* AN link partner ability next page */
-	ENET_TBI_MII_EXST = 0x0F,	/* Extended status */
-	ENET_TBI_MII_JD = 0x10,	/* Jitter diagnostics */
-	ENET_TBI_MII_TBICON = 0x11	/* TBI control */
-};
-
-int uec_mdio_read(struct mii_bus *bus, int mii_id, int regnum);
-int uec_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value);
-int __init uec_mdio_init(void);
-void uec_mdio_exit(void);
-void uec_mdio_bus_name(char *name, struct device_node *np);
-#endif				/* __UEC_MII_H */
...	...	@@ -2272,9 +2272,17 @@
2272	2272
2273	2273	If unsure, say N.
2274	2274
	2275	+config FSL_PQ_MDIO
	2276	+ tristate "Freescale PQ MDIO"
	2277	+ depends on FSL_SOC
	2278	+ select PHYLIB
	2279	+ help
	2280	+ This driver supports the MDIO bus used by the gianfar and UCC drivers.
	2281	+
2275	2282	config GIANFAR
2276	2283	tristate "Gianfar Ethernet"
2277	2284	depends on FSL_SOC
	2285	+ select FSL_PQ_MDIO
2278	2286	select PHYLIB
2279	2287	select CRC32
2280	2288	help
...	...	@@ -2284,6 +2292,7 @@
2284	2292	config UCC_GETH
2285	2293	tristate "Freescale QE Gigabit Ethernet"
2286	2294	depends on QUICC_ENGINE
	2295	+ select FSL_PQ_MDIO
2287	2296	select PHYLIB
2288	2297	help
2289	2298	This driver supports the Gigabit Ethernet mode of the QUICC Engine,
...	...	@@ -24,11 +24,12 @@
24	24
25	25	gianfar_driver-objs := gianfar.o \
26	26	gianfar_ethtool.o \
27		- gianfar_mii.o \
28	27	gianfar_sysfs.o
29	28
30	29	obj-$(CONFIG_UCC_GETH) += ucc_geth_driver.o
31		-ucc_geth_driver-objs := ucc_geth.o ucc_geth_mii.o ucc_geth_ethtool.o
	30	+ucc_geth_driver-objs := ucc_geth.o ucc_geth_ethtool.o
	31	+
	32	+obj-$(CONFIG_FSL_PQ_MDIO) += fsl_pq_mdio.o
32	33
33	34	#
34	35	# link order important here
	1	+/*
	2	+ * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation
	3	+ * Provides Bus interface for MIIM regs
	4	+ *
	5	+ * Author: Andy Fleming <afleming@freescale.com>
	6	+ *
	7	+ * Copyright (c) 2002-2004,2008 Freescale Semiconductor, Inc.
	8	+ *
	9	+ * Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips)
	10	+ *
	11	+ * This program is free software; you can redistribute it and/or modify it
	12	+ * under the terms of the GNU General Public License as published by the
	13	+ * Free Software Foundation; either version 2 of the License, or (at your
	14	+ * option) any later version.
	15	+ *
	16	+ */
	17	+
	18	+#include <linux/kernel.h>
	19	+#include <linux/string.h>
	20	+#include <linux/errno.h>
	21	+#include <linux/unistd.h>
	22	+#include <linux/slab.h>
	23	+#include <linux/interrupt.h>
	24	+#include <linux/init.h>
	25	+#include <linux/delay.h>
	26	+#include <linux/netdevice.h>
	27	+#include <linux/etherdevice.h>
	28	+#include <linux/skbuff.h>
	29	+#include <linux/spinlock.h>
	30	+#include <linux/mm.h>
	31	+#include <linux/module.h>
	32	+#include <linux/platform_device.h>
	33	+#include <linux/crc32.h>
	34	+#include <linux/mii.h>
	35	+#include <linux/phy.h>
	36	+#include <linux/of.h>
	37	+#include <linux/of_platform.h>
	38	+
	39	+#include <asm/io.h>
	40	+#include <asm/irq.h>
	41	+#include <asm/uaccess.h>
	42	+#include <asm/ucc.h>
	43	+
	44	+#include "gianfar.h"
	45	+#include "fsl_pq_mdio.h"
	46	+
	47	+/*
	48	+ * Write value to the PHY at mii_id at register regnum,
	49	+ * on the bus attached to the local interface, which may be different from the
	50	+ * generic mdio bus (tied to a single interface), waiting until the write is
	51	+ * done before returning. This is helpful in programming interfaces like
	52	+ * the TBI which control interfaces like onchip SERDES and are always tied to
	53	+ * the local mdio pins, which may not be the same as system mdio bus, used for
	54	+ * controlling the external PHYs, for example.
	55	+ */
	56	+int fsl_pq_local_mdio_write(struct fsl_pq_mdio __iomem *regs, int mii_id,
	57	+ int regnum, u16 value)
	58	+{
	59	+ /* Set the PHY address and the register address we want to write */
	60	+ out_be32(&regs->miimadd, (mii_id << 8) \| regnum);
	61	+
	62	+ /* Write out the value we want */
	63	+ out_be32(&regs->miimcon, value);
	64	+
	65	+ /* Wait for the transaction to finish */
	66	+ while (in_be32(&regs->miimind) & MIIMIND_BUSY)
	67	+ cpu_relax();
	68	+
	69	+ return 0;
	70	+}
	71	+
	72	+/*
	73	+ * Read the bus for PHY at addr mii_id, register regnum, and
	74	+ * return the value. Clears miimcom first. All PHY operation
	75	+ * done on the bus attached to the local interface,
	76	+ * which may be different from the generic mdio bus
	77	+ * This is helpful in programming interfaces like
	78	+ * the TBI which, in turn, control interfaces like onchip SERDES
	79	+ * and are always tied to the local mdio pins, which may not be the
	80	+ * same as system mdio bus, used for controlling the external PHYs, for eg.
	81	+ */
	82	+int fsl_pq_local_mdio_read(struct fsl_pq_mdio __iomem *regs,
	83	+ int mii_id, int regnum)
	84	+{
	85	+ u16 value;
	86	+
	87	+ /* Set the PHY address and the register address we want to read */
	88	+ out_be32(&regs->miimadd, (mii_id << 8) \| regnum);
	89	+
	90	+ /* Clear miimcom, and then initiate a read */
	91	+ out_be32(&regs->miimcom, 0);
	92	+ out_be32(&regs->miimcom, MII_READ_COMMAND);
	93	+
	94	+ /* Wait for the transaction to finish */
	95	+ while (in_be32(&regs->miimind) & (MIIMIND_NOTVALID \| MIIMIND_BUSY))
	96	+ cpu_relax();
	97	+
	98	+ /* Grab the value of the register from miimstat */
	99	+ value = in_be32(&regs->miimstat);
	100	+
	101	+ return value;
	102	+}
	103	+
	104	+/*
	105	+ * Write value to the PHY at mii_id at register regnum,
	106	+ * on the bus, waiting until the write is done before returning.
	107	+ */
	108	+int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value)
	109	+{
	110	+ struct fsl_pq_mdio __iomem regs = (void __iomem )bus->priv;
	111	+
	112	+ /* Write to the local MII regs */
	113	+ return(fsl_pq_local_mdio_write(regs, mii_id, regnum, value));
	114	+}
	115	+
	116	+/*
	117	+ * Read the bus for PHY at addr mii_id, register regnum, and
	118	+ * return the value. Clears miimcom first.
	119	+ */
	120	+int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
	121	+{
	122	+ struct fsl_pq_mdio __iomem regs = (void __iomem )bus->priv;
	123	+
	124	+ /* Read the local MII regs */
	125	+ return(fsl_pq_local_mdio_read(regs, mii_id, regnum));
	126	+}
	127	+
	128	+/* Reset the MIIM registers, and wait for the bus to free */
	129	+static int fsl_pq_mdio_reset(struct mii_bus *bus)
	130	+{
	131	+ struct fsl_pq_mdio __iomem regs = (void __iomem )bus->priv;
	132	+ unsigned int timeout = PHY_INIT_TIMEOUT;
	133	+
	134	+ mutex_lock(&bus->mdio_lock);
	135	+
	136	+ /* Reset the management interface */
	137	+ out_be32(&regs->miimcfg, MIIMCFG_RESET);
	138	+
	139	+ /* Setup the MII Mgmt clock speed */
	140	+ out_be32(&regs->miimcfg, MIIMCFG_INIT_VALUE);
	141	+
	142	+ /* Wait until the bus is free */
	143	+ while ((in_be32(&regs->miimind) & MIIMIND_BUSY) && timeout--)
	144	+ cpu_relax();
	145	+
	146	+ mutex_unlock(&bus->mdio_lock);
	147	+
	148	+ if(timeout == 0) {
	149	+ printk(KERN_ERR "%s: The MII Bus is stuck!\n",
	150	+ bus->name);
	151	+ return -EBUSY;
	152	+ }
	153	+
	154	+ return 0;
	155	+}
	156	+
	157	+/* Allocate an array which provides irq #s for each PHY on the given bus */
	158	+static int create_irq_map(struct device_node np)
	159	+{
	160	+ int *irqs;
	161	+ int i;
	162	+ struct device_node *child = NULL;
	163	+
	164	+ irqs = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
	165	+
	166	+ if (!irqs)
	167	+ return NULL;
	168	+
	169	+ for (i = 0; i < PHY_MAX_ADDR; i++)
	170	+ irqs[i] = PHY_POLL;
	171	+
	172	+ while ((child = of_get_next_child(np, child)) != NULL) {
	173	+ int irq = irq_of_parse_and_map(child, 0);
	174	+ const u32 *id;
	175	+
	176	+ if (irq == NO_IRQ)
	177	+ continue;
	178	+
	179	+ id = of_get_property(child, "reg", NULL);
	180	+
	181	+ if (!id)
	182	+ continue;
	183	+
	184	+ if (id < PHY_MAX_ADDR && id >= 0)
	185	+ irqs[*id] = irq;
	186	+ else
	187	+ printk(KERN_WARNING "%s: "
	188	+ "%d is not a valid PHY address\n",
	189	+ np->full_name, *id);
	190	+ }
	191	+
	192	+ return irqs;
	193	+}
	194	+
	195	+void fsl_pq_mdio_bus_name(char name, struct device_node np)
	196	+{
	197	+ const u32 *reg;
	198	+
	199	+ reg = of_get_property(np, "reg", NULL);
	200	+
	201	+ snprintf(name, MII_BUS_ID_SIZE, "%s@%x", np->name, reg ? *reg : 0);
	202	+}
	203	+
	204	+/* Scan the bus in reverse, looking for an empty spot */
	205	+static int fsl_pq_mdio_find_free(struct mii_bus *new_bus)
	206	+{
	207	+ int i;
	208	+
	209	+ for (i = PHY_MAX_ADDR; i > 0; i--) {
	210	+ u32 phy_id;
	211	+
	212	+ if (get_phy_id(new_bus, i, &phy_id))
	213	+ return -1;
	214	+
	215	+ if (phy_id == 0xffffffff)
	216	+ break;
	217	+ }
	218	+
	219	+ return i;
	220	+}
	221	+
	222	+
	223	+#ifdef CONFIG_GIANFAR
	224	+static u32 __iomem get_gfar_tbipa(struct fsl_pq_mdio __iomem regs)
	225	+{
	226	+ struct gfar __iomem *enet_regs;
	227	+
	228	+ /*
	229	+ * This is mildly evil, but so is our hardware for doing this.
	230	+ * Also, we have to cast back to struct gfar because of
	231	+ * definition weirdness done in gianfar.h.
	232	+ */
	233	+ enet_regs = (struct gfar __iomem *)
	234	+ ((char __iomem *)regs - offsetof(struct gfar, gfar_mii_regs));
	235	+
	236	+ return &enet_regs->tbipa;
	237	+}
	238	+#endif
	239	+
	240	+
	241	+#ifdef CONFIG_UCC_GETH
	242	+static int get_ucc_id_for_range(u64 start, u64 end, u32 *ucc_id)
	243	+{
	244	+ struct device_node *np = NULL;
	245	+ int err = 0;
	246	+
	247	+ for_each_compatible_node(np, NULL, "ucc_geth") {
	248	+ struct resource tempres;
	249	+
	250	+ err = of_address_to_resource(np, 0, &tempres);
	251	+ if (err)
	252	+ continue;
	253	+
	254	+ /* if our mdio regs fall within this UCC regs range */
	255	+ if ((start >= tempres.start) && (end <= tempres.end)) {
	256	+ /* Find the id of the UCC */
	257	+ const u32 *id;
	258	+
	259	+ id = of_get_property(np, "cell-index", NULL);
	260	+ if (!id) {
	261	+ id = of_get_property(np, "device-id", NULL);
	262	+ if (!id)
	263	+ continue;
	264	+ }
	265	+
	266	+ ucc_id = id;
	267	+
	268	+ return 0;
	269	+ }
	270	+ }
	271	+
	272	+ if (err)
	273	+ return err;
	274	+ else
	275	+ return -EINVAL;
	276	+}
	277	+#endif
	278	+
	279	+
	280	+static int fsl_pq_mdio_probe(struct of_device *ofdev,
	281	+ const struct of_device_id *match)
	282	+{
	283	+ struct device_node *np = ofdev->node;
	284	+ struct device_node *tbi;
	285	+ struct fsl_pq_mdio __iomem *regs;
	286	+ u32 __iomem *tbipa;
	287	+ struct mii_bus *new_bus;
	288	+ int tbiaddr = -1;
	289	+ u64 addr, size;
	290	+ int err = 0;
	291	+
	292	+ new_bus = mdiobus_alloc();
	293	+ if (NULL == new_bus)
	294	+ return -ENOMEM;
	295	+
	296	+ new_bus->name = "Freescale PowerQUICC MII Bus",
	297	+ new_bus->read = &fsl_pq_mdio_read,
	298	+ new_bus->write = &fsl_pq_mdio_write,
	299	+ new_bus->reset = &fsl_pq_mdio_reset,
	300	+ fsl_pq_mdio_bus_name(new_bus->id, np);
	301	+
	302	+ /* Set the PHY base address */
	303	+ addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
	304	+ regs = ioremap(addr, size);
	305	+
	306	+ if (NULL == regs) {
	307	+ err = -ENOMEM;
	308	+ goto err_free_bus;
	309	+ }
	310	+
	311	+ new_bus->priv = (void __force *)regs;
	312	+
	313	+ new_bus->irq = create_irq_map(np);
	314	+
	315	+ if (NULL == new_bus->irq) {
	316	+ err = -ENOMEM;
	317	+ goto err_unmap_regs;
	318	+ }
	319	+
	320	+ new_bus->parent = &ofdev->dev;
	321	+ dev_set_drvdata(&ofdev->dev, new_bus);
	322	+
	323	+ if (of_device_is_compatible(np, "fsl,gianfar-mdio") \|\|
	324	+ of_device_is_compatible(np, "gianfar")) {
	325	+#ifdef CONFIG_GIANFAR
	326	+ tbipa = get_gfar_tbipa(regs);
	327	+#else
	328	+ err = -ENODEV;
	329	+ goto err_free_irqs;
	330	+#endif
	331	+ } else if (of_device_is_compatible(np, "fsl,ucc-mdio") \|\|
	332	+ of_device_is_compatible(np, "ucc_geth_phy")) {
	333	+#ifdef CONFIG_UCC_GETH
	334	+ u32 id;
	335	+
	336	+ tbipa = &regs->utbipar;
	337	+
	338	+ if ((err = get_ucc_id_for_range(addr, addr + size, &id)))
	339	+ goto err_free_irqs;
	340	+
	341	+ ucc_set_qe_mux_mii_mng(id - 1);
	342	+#else
	343	+ err = -ENODEV;
	344	+ goto err_free_irqs;
	345	+#endif
	346	+ } else {
	347	+ err = -ENODEV;
	348	+ goto err_free_irqs;
	349	+ }
	350	+
	351	+ for_each_child_of_node(np, tbi) {
	352	+ if (!strncmp(tbi->type, "tbi-phy", 8))
	353	+ break;
	354	+ }
	355	+
	356	+ if (tbi) {
	357	+ const u32 *prop = of_get_property(tbi, "reg", NULL);
	358	+
	359	+ if (prop)
	360	+ tbiaddr = *prop;
	361	+ }
	362	+
	363	+ if (tbiaddr == -1) {
	364	+ out_be32(tbipa, 0);
	365	+
	366	+ tbiaddr = fsl_pq_mdio_find_free(new_bus);
	367	+ }
	368	+
	369	+ /*
	370	+ * We define TBIPA at 0 to be illegal, opting to fail for boards that
	371	+ * have PHYs at 1-31, rather than change tbipa and rescan.
	372	+ */
	373	+ if (tbiaddr == 0) {
	374	+ err = -EBUSY;
	375	+
	376	+ goto err_free_irqs;
	377	+ }
	378	+
	379	+ out_be32(tbipa, tbiaddr);
	380	+
	381	+ /*
	382	+ * The TBIPHY-only buses will find PHYs at every address,
	383	+ * so we mask them all but the TBI
	384	+ */
	385	+ if (!of_device_is_compatible(np, "fsl,gianfar-mdio"))
	386	+ new_bus->phy_mask = ~(1 << tbiaddr);
	387	+
	388	+ err = mdiobus_register(new_bus);
	389	+
	390	+ if (err) {
	391	+ printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
	392	+ new_bus->name);
	393	+ goto err_free_irqs;
	394	+ }
	395	+
	396	+ return 0;
	397	+
	398	+err_free_irqs:
	399	+ kfree(new_bus->irq);
	400	+err_unmap_regs:
	401	+ iounmap(regs);
	402	+err_free_bus:
	403	+ kfree(new_bus);
	404	+
	405	+ return err;
	406	+}
	407	+
	408	+
	409	+static int fsl_pq_mdio_remove(struct of_device *ofdev)
	410	+{
	411	+ struct device *device = &ofdev->dev;
	412	+ struct mii_bus *bus = dev_get_drvdata(device);
	413	+
	414	+ mdiobus_unregister(bus);
	415	+
	416	+ dev_set_drvdata(device, NULL);
	417	+
	418	+ iounmap((void __iomem *)bus->priv);
	419	+ bus->priv = NULL;
	420	+ mdiobus_free(bus);
	421	+
	422	+ return 0;
	423	+}
	424	+
	425	+static struct of_device_id fsl_pq_mdio_match[] = {
	426	+ {
	427	+ .type = "mdio",
	428	+ .compatible = "ucc_geth_phy",
	429	+ },
	430	+ {
	431	+ .type = "mdio",
	432	+ .compatible = "gianfar",
	433	+ },
	434	+ {
	435	+ .compatible = "fsl,ucc-mdio",
	436	+ },
	437	+ {
	438	+ .compatible = "fsl,gianfar-tbi",
	439	+ },
	440	+ {
	441	+ .compatible = "fsl,gianfar-mdio",
	442	+ },
	443	+ {},
	444	+};
	445	+
	446	+static struct of_platform_driver fsl_pq_mdio_driver = {
	447	+ .name = "fsl-pq_mdio",
	448	+ .probe = fsl_pq_mdio_probe,
	449	+ .remove = fsl_pq_mdio_remove,
	450	+ .match_table = fsl_pq_mdio_match,
	451	+};
	452	+
	453	+int __init fsl_pq_mdio_init(void)
	454	+{
	455	+ return of_register_platform_driver(&fsl_pq_mdio_driver);
	456	+}
	457	+
	458	+void fsl_pq_mdio_exit(void)
	459	+{
	460	+ of_unregister_platform_driver(&fsl_pq_mdio_driver);
	461	+}
	462	+subsys_initcall_sync(fsl_pq_mdio_init);
	463	+module_exit(fsl_pq_mdio_exit);
	1	+/*
	2	+ * Freescale PowerQUICC MDIO Driver -- MII Management Bus Implementation
	3	+ * Driver for the MDIO bus controller on Freescale PowerQUICC processors
	4	+ *
	5	+ * Author: Andy Fleming
	6	+ *
	7	+ * Copyright (c) 2002-2004,2008 Freescale Semiconductor, Inc.
	8	+ *
	9	+ * This program is free software; you can redistribute it and/or modify it
	10	+ * under the terms of the GNU General Public License as published by the
	11	+ * Free Software Foundation; either version 2 of the License, or (at your
	12	+ * option) any later version.
	13	+ *
	14	+ */
	15	+#ifndef __FSL_PQ_MDIO_H
	16	+#define __FSL_PQ_MDIO_H
	17	+
	18	+#define MIIMIND_BUSY 0x00000001
	19	+#define MIIMIND_NOTVALID 0x00000004
	20	+#define MIIMCFG_INIT_VALUE 0x00000007
	21	+#define MIIMCFG_RESET 0x80000000
	22	+
	23	+#define MII_READ_COMMAND 0x00000001
	24	+
	25	+struct fsl_pq_mdio {
	26	+ u32 miimcfg; /* MII management configuration reg */
	27	+ u32 miimcom; /* MII management command reg */
	28	+ u32 miimadd; /* MII management address reg */
	29	+ u32 miimcon; /* MII management control reg */
	30	+ u32 miimstat; /* MII management status reg */
	31	+ u32 miimind; /* MII management indication reg */
	32	+ u8 reserved[28]; /* Space holder */
	33	+ u32 utbipar; /* TBI phy address reg (only on UCC) */
	34	+} __attribute__ ((packed));
	35	+
	36	+
	37	+int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum);
	38	+int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value);
	39	+int fsl_pq_local_mdio_write(struct fsl_pq_mdio __iomem *regs, int mii_id,
	40	+ int regnum, u16 value);
	41	+int fsl_pq_local_mdio_read(struct fsl_pq_mdio __iomem *regs, int mii_id, int regnum);
	42	+int __init fsl_pq_mdio_init(void);
	43	+void fsl_pq_mdio_exit(void);
	44	+void fsl_pq_mdio_bus_name(char name, struct device_node np);
	45	+#endif /* FSL_PQ_MDIO_H */
...	...	@@ -93,7 +93,7 @@
93	93	#include <linux/of.h>
94	94
95	95	#include "gianfar.h"
96		-#include "gianfar_mii.h"
	96	+#include "fsl_pq_mdio.h"
97	97
98	98	#define TX_TIMEOUT (1*HZ)
99	99	#undef BRIEF_GFAR_ERRORS
...	...	@@ -253,7 +253,7 @@
253	253	of_node_put(phy);
254	254	of_node_put(mdio);
255	255
256		- gfar_mdio_bus_name(bus_name, mdio);
	256	+ fsl_pq_mdio_bus_name(bus_name, mdio);
257	257	snprintf(priv->phy_bus_id, sizeof(priv->phy_bus_id), "%s:%02x",
258	258	bus_name, *id);
259	259	}
...	...	@@ -420,7 +420,7 @@
420	420	priv->hash_width = 8;
421	421
422	422	priv->hash_regs[0] = &priv->regs->gaddr0;
423		- priv->hash_regs[1] = &priv->regs->gaddr1;
	423	+ priv->hash_regs[1] = &priv->regs->gaddr1;
424	424	priv->hash_regs[2] = &priv->regs->gaddr2;
425	425	priv->hash_regs[3] = &priv->regs->gaddr3;
426	426	priv->hash_regs[4] = &priv->regs->gaddr4;
...	...	@@ -836,7 +836,7 @@
836	836	free_irq(priv->interruptTransmit, dev);
837	837	free_irq(priv->interruptReceive, dev);
838	838	} else {
839		- free_irq(priv->interruptTransmit, dev);
	839	+ free_irq(priv->interruptTransmit, dev);
840	840	}
841	841
842	842	free_skb_resources(priv);
...	...	@@ -1829,6 +1829,8 @@
1829	1829	skb_put(skb, pkt_len);
1830	1830	dev->stats.rx_bytes += pkt_len;
1831	1831
	1832	+ if (in_irq() \|\| irqs_disabled())
	1833	+ printk("Interrupt problem!\n");
1832	1834	gfar_process_frame(dev, skb, amount_pull);
1833	1835
1834	1836	} else {
1835	1837
...	...	@@ -2302,23 +2304,12 @@
2302	2304
2303	2305	static int __init gfar_init(void)
2304	2306	{
2305		- int err = gfar_mdio_init();
2306		-
2307		- if (err)
2308		- return err;
2309		-
2310		- err = of_register_platform_driver(&gfar_driver);
2311		-
2312		- if (err)
2313		- gfar_mdio_exit();
2314		-
2315		- return err;
	2307	+ return of_register_platform_driver(&gfar_driver);
2316	2308	}
2317	2309
2318	2310	static void __exit gfar_exit(void)
2319	2311	{
2320	2312	of_unregister_platform_driver(&gfar_driver);
2321		- gfar_mdio_exit();
2322	2313	}
2323	2314
2324	2315	module_init(gfar_init);
...	...	@@ -46,7 +46,6 @@
46	46	#include <linux/workqueue.h>
47	47	#include <linux/ethtool.h>
48	48	#include <linux/fsl_devices.h>
49		-#include "gianfar_mii.h"
50	49
51	50	/* The maximum number of packets to be handled in one call of gfar_poll */
52	51	#define GFAR_DEV_WEIGHT 64
...	...	@@ -126,9 +125,12 @@
126	125	#define DEFAULT_RX_COALESCE 0
127	126	#define DEFAULT_RXCOUNT 0
128	127
129		-#define MIIMCFG_INIT_VALUE 0x00000007
130		-#define MIIMCFG_RESET 0x80000000
131		-#define MIIMIND_BUSY 0x00000001
	128	+#define GFAR_SUPPORTED (SUPPORTED_10baseT_Half \
	129	+ \| SUPPORTED_10baseT_Full \
	130	+ \| SUPPORTED_100baseT_Half \
	131	+ \| SUPPORTED_100baseT_Full \
	132	+ \| SUPPORTED_Autoneg \
	133	+ \| SUPPORTED_MII)
132	134
133	135	/* TBI register addresses */
134	136	#define MII_TBICON 0x11
...	...	@@ -826,9 +828,6 @@
826	828	extern void gfar_phy_test(struct mii_bus bus, struct phy_device phydev,
827	829	int enable, u32 regnum, u32 read);
828	830	void gfar_init_sysfs(struct net_device *dev);
829		-int gfar_local_mdio_write(struct gfar_mii __iomem *regs, int mii_id,
830		- int regnum, u16 value);
831		-int gfar_local_mdio_read(struct gfar_mii __iomem *regs, int mii_id, int regnum);
832	831
833	832	extern const struct ethtool_ops gfar_ethtool_ops;
834	833
1		-/*
2		- * drivers/net/gianfar_mii.h
3		- *
4		- * Gianfar Ethernet Driver -- MII Management Bus Implementation
5		- * Driver for the MDIO bus controller in the Gianfar register space
6		- *
7		- * Author: Andy Fleming
8		- * Maintainer: Kumar Gala
9		- *
10		- * Copyright (c) 2002-2004 Freescale Semiconductor, Inc.
11		- *
12		- * This program is free software; you can redistribute it and/or modify it
13		- * under the terms of the GNU General Public License as published by the
14		- * Free Software Foundation; either version 2 of the License, or (at your
15		- * option) any later version.
16		- *
17		- */
18		-#ifndef __GIANFAR_MII_H
19		-#define __GIANFAR_MII_H
20		-
21		-struct gfar_private; /* forward ref */
22		-
23		-#define MIIMIND_BUSY 0x00000001
24		-#define MIIMIND_NOTVALID 0x00000004
25		-
26		-#define MII_READ_COMMAND 0x00000001
27		-
28		-#define GFAR_SUPPORTED (SUPPORTED_10baseT_Half \
29		- \| SUPPORTED_10baseT_Full \
30		- \| SUPPORTED_100baseT_Half \
31		- \| SUPPORTED_100baseT_Full \
32		- \| SUPPORTED_Autoneg \
33		- \| SUPPORTED_MII)
34		-
35		-struct gfar_mii {
36		- u32 miimcfg; /* 0x.520 - MII Management Config Register */
37		- u32 miimcom; /* 0x.524 - MII Management Command Register */
38		- u32 miimadd; /* 0x.528 - MII Management Address Register */
39		- u32 miimcon; /* 0x.52c - MII Management Control Register */
40		- u32 miimstat; /* 0x.530 - MII Management Status Register */
41		- u32 miimind; /* 0x.534 - MII Management Indicator Register */
42		-};
43		-
44		-int gfar_mdio_read(struct mii_bus *bus, int mii_id, int regnum);
45		-int gfar_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value);
46		-int gfar_local_mdio_write(struct gfar_mii __iomem *regs, int mii_id,
47		- int regnum, u16 value);
48		-int gfar_local_mdio_read(struct gfar_mii __iomem *regs, int mii_id, int regnum);
49		-struct mii_bus gfar_get_miibus(const struct gfar_private priv);
50		-int __init gfar_mdio_init(void);
51		-void gfar_mdio_exit(void);
52		-
53		-void gfar_mdio_bus_name(char name, struct device_node np);
54		-#endif /* GIANFAR_PHY_H */
...	...	@@ -39,7 +39,7 @@
39	39	#include <asm/ucc_fast.h>
40	40
41	41	#include "ucc_geth.h"
42		-#include "ucc_geth_mii.h"
	42	+#include "fsl_pq_mdio.h"
43	43
44	44	#undef DEBUG
45	45
...	...	@@ -1557,7 +1557,7 @@
1557	1557	of_node_put(phy);
1558	1558	of_node_put(mdio);
1559	1559
1560		- uec_mdio_bus_name(bus_name, mdio);
	1560	+ fsl_pq_mdio_bus_name(bus_name, mdio);
1561	1561	snprintf(phy_id, sizeof(phy_id), "%s:%02x",
1562	1562	bus_name, *id);
1563	1563
...	...	@@ -3657,7 +3657,8 @@
3657	3657	if (err)
3658	3658	return -1;
3659	3659
3660		- snprintf(ug_info->mdio_bus, MII_BUS_ID_SIZE, "%x", res.start);
	3660	+ snprintf(ug_info->mdio_bus, MII_BUS_ID_SIZE, "%x",
	3661	+ res.start&0xfffff);
3661	3662	}
3662	3663
3663	3664	/* get the phy interface type, or default to MII */
...	...	@@ -3803,11 +3804,6 @@
3803	3804	{
3804	3805	int i, ret;
3805	3806
3806		- ret = uec_mdio_init();
3807		-
3808		- if (ret)
3809		- return ret;
3810		-
3811	3807	if (netif_msg_drv(&debug))
3812	3808	printk(KERN_INFO "ucc_geth: " DRV_DESC "\n");
3813	3809	for (i = 0; i < 8; i++)
3814	3810
...	...	@@ -3816,16 +3812,12 @@
3816	3812
3817	3813	ret = of_register_platform_driver(&ucc_geth_driver);
3818	3814
3819		- if (ret)
3820		- uec_mdio_exit();
3821		-
3822	3815	return ret;
3823	3816	}
3824	3817
3825	3818	static void __exit ucc_geth_exit(void)
3826	3819	{
3827	3820	of_unregister_platform_driver(&ucc_geth_driver);
3828		- uec_mdio_exit();
3829	3821	}
3830	3822
3831	3823	module_init(ucc_geth_init);
...	...	@@ -28,8 +28,6 @@
28	28	#include <asm/ucc.h>
29	29	#include <asm/ucc_fast.h>
30	30
31		-#include "ucc_geth_mii.h"
32		-
33	31	#define DRV_DESC "QE UCC Gigabit Ethernet Controller"
34	32	#define DRV_NAME "ucc_geth"
35	33	#define DRV_VERSION "1.1"
...	...	@@ -183,6 +181,18 @@
183	181
184	182	#define UCCE_RX_EVENTS (UCCE_RXF \| UCC_GETH_UCCE_BSY)
185	183	#define UCCE_TX_EVENTS (UCCE_TXB \| UCC_GETH_UCCE_TXE)
	184	+
	185	+/* TBI defines */
	186	+#define ENET_TBI_MII_CR 0x00 /* Control */
	187	+#define ENET_TBI_MII_SR 0x01 /* Status */
	188	+#define ENET_TBI_MII_ANA 0x04 /* AN advertisement */
	189	+#define ENET_TBI_MII_ANLPBPA 0x05 /* AN link partner base page ability */
	190	+#define ENET_TBI_MII_ANEX 0x06 /* AN expansion */
	191	+#define ENET_TBI_MII_ANNPT 0x07 /* AN next page transmit */
	192	+#define ENET_TBI_MII_ANLPANP 0x08 /* AN link partner ability next page */
	193	+#define ENET_TBI_MII_EXST 0x0F /* Extended status */
	194	+#define ENET_TBI_MII_JD 0x10 /* Jitter diagnostics */
	195	+#define ENET_TBI_MII_TBICON 0x11 /* TBI control */
186	196
187	197	/* UCC GETH MACCFG1 (MAC Configuration 1 Register) */
188	198	#define MACCFG1_FLOW_RX 0x00000020 /* Flow Control
...	...	@@ -39,7 +39,6 @@
39	39	#include <asm/types.h>
40	40
41	41	#include "ucc_geth.h"
42		-#include "ucc_geth_mii.h"
43	42
44	43	static char hw_stat_gstrings[][ETH_GSTRING_LEN] = {
45	44	"tx-64-frames",