Commit 193c3cc12583344be01206078d9ad3fec5dbc397
Committed by
Russell King
1 parent
6232be32af
[ARM] Fix timer damage from d3d74453c34f8fd87674a8cf5b8a327c68f22e99
Move the xtime write mode seqlock into timer_tick(), so it only surrounds the call to do_timer(). This avoids a deadlock in update_process_times() ... hrtimer_get_softirq_time() which tries to get a read mode seqlock on xtime, thereby preventing booting. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Showing 21 changed files with 2 additions and 71 deletions Side-by-side Diff
- arch/arm/kernel/time.c
- arch/arm/mach-aaec2000/core.c
- arch/arm/mach-clps711x/time.c
- arch/arm/mach-clps7500/core.c
- arch/arm/mach-ebsa110/core.c
- arch/arm/mach-ep93xx/core.c
- arch/arm/mach-footbridge/dc21285-timer.c
- arch/arm/mach-footbridge/isa-timer.c
- arch/arm/mach-h720x/cpu-h7201.c
- arch/arm/mach-h720x/cpu-h7202.c
- arch/arm/mach-integrator/core.c
- arch/arm/mach-ixp2000/core.c
- arch/arm/mach-ks8695/time.c
- arch/arm/mach-lh7a40x/time.c
- arch/arm/mach-mx3/time.c
- arch/arm/mach-netx/time.c
- arch/arm/mach-omap2/timer-gp.c
- arch/arm/mach-pnx4008/time.c
- arch/arm/mach-realview/core.c
- arch/arm/mach-sa1100/time.c
- arch/arm/mach-shark/core.c
arch/arm/kernel/time.c
arch/arm/mach-aaec2000/core.c
... | ... | @@ -130,12 +130,8 @@ |
130 | 130 | aaec2000_timer_interrupt(int irq, void *dev_id) |
131 | 131 | { |
132 | 132 | /* TODO: Check timer accuracy */ |
133 | - write_seqlock(&xtime_lock); | |
134 | - | |
135 | 133 | timer_tick(); |
136 | 134 | TIMER1_CLEAR = 1; |
137 | - | |
138 | - write_sequnlock(&xtime_lock); | |
139 | 135 | |
140 | 136 | return IRQ_HANDLED; |
141 | 137 | } |
arch/arm/mach-clps711x/time.c
arch/arm/mach-clps7500/core.c
... | ... | @@ -298,8 +298,6 @@ |
298 | 298 | static irqreturn_t |
299 | 299 | clps7500_timer_interrupt(int irq, void *dev_id) |
300 | 300 | { |
301 | - write_seqlock(&xtime_lock); | |
302 | - | |
303 | 301 | timer_tick(); |
304 | 302 | |
305 | 303 | /* Why not using do_leds interface?? */ |
... | ... | @@ -312,8 +310,6 @@ |
312 | 310 | *((volatile unsigned int *)LED_ADDRESS) = state; |
313 | 311 | } |
314 | 312 | } |
315 | - | |
316 | - write_sequnlock(&xtime_lock); | |
317 | 313 | |
318 | 314 | return IRQ_HANDLED; |
319 | 315 | } |
arch/arm/mach-ebsa110/core.c
... | ... | @@ -178,8 +178,6 @@ |
178 | 178 | { |
179 | 179 | u32 count; |
180 | 180 | |
181 | - write_seqlock(&xtime_lock); | |
182 | - | |
183 | 181 | /* latch and read timer 1 */ |
184 | 182 | __raw_writeb(0x40, PIT_CTRL); |
185 | 183 | count = __raw_readb(PIT_T1); |
... | ... | @@ -191,8 +189,6 @@ |
191 | 189 | __raw_writeb(count >> 8, PIT_T1); |
192 | 190 | |
193 | 191 | timer_tick(); |
194 | - | |
195 | - write_sequnlock(&xtime_lock); | |
196 | 192 | |
197 | 193 | return IRQ_HANDLED; |
198 | 194 | } |
arch/arm/mach-ep93xx/core.c
... | ... | @@ -99,8 +99,6 @@ |
99 | 99 | |
100 | 100 | static int ep93xx_timer_interrupt(int irq, void *dev_id) |
101 | 101 | { |
102 | - write_seqlock(&xtime_lock); | |
103 | - | |
104 | 102 | __raw_writel(1, EP93XX_TIMER1_CLEAR); |
105 | 103 | while ((signed long) |
106 | 104 | (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time) |
... | ... | @@ -108,8 +106,6 @@ |
108 | 106 | last_jiffy_time += TIMER4_TICKS_PER_JIFFY; |
109 | 107 | timer_tick(); |
110 | 108 | } |
111 | - | |
112 | - write_sequnlock(&xtime_lock); | |
113 | 109 | |
114 | 110 | return IRQ_HANDLED; |
115 | 111 | } |
arch/arm/mach-footbridge/dc21285-timer.c
arch/arm/mach-footbridge/isa-timer.c
arch/arm/mach-h720x/cpu-h7201.c
arch/arm/mach-h720x/cpu-h7202.c
arch/arm/mach-integrator/core.c
... | ... | @@ -250,16 +250,12 @@ |
250 | 250 | static irqreturn_t |
251 | 251 | integrator_timer_interrupt(int irq, void *dev_id) |
252 | 252 | { |
253 | - write_seqlock(&xtime_lock); | |
254 | - | |
255 | 253 | /* |
256 | 254 | * clear the interrupt |
257 | 255 | */ |
258 | 256 | writel(1, TIMER1_VA_BASE + TIMER_INTCLR); |
259 | 257 | |
260 | 258 | timer_tick(); |
261 | - | |
262 | - write_sequnlock(&xtime_lock); | |
263 | 259 | |
264 | 260 | return IRQ_HANDLED; |
265 | 261 | } |
arch/arm/mach-ixp2000/core.c
... | ... | @@ -206,8 +206,6 @@ |
206 | 206 | |
207 | 207 | static int ixp2000_timer_interrupt(int irq, void *dev_id) |
208 | 208 | { |
209 | - write_seqlock(&xtime_lock); | |
210 | - | |
211 | 209 | /* clear timer 1 */ |
212 | 210 | ixp2000_reg_wrb(IXP2000_T1_CLR, 1); |
213 | 211 | |
... | ... | @@ -216,8 +214,6 @@ |
216 | 214 | timer_tick(); |
217 | 215 | next_jiffy_time -= ticks_per_jiffy; |
218 | 216 | } |
219 | - | |
220 | - write_sequnlock(&xtime_lock); | |
221 | 217 | |
222 | 218 | return IRQ_HANDLED; |
223 | 219 | } |
arch/arm/mach-ks8695/time.c
arch/arm/mach-lh7a40x/time.c
arch/arm/mach-mx3/time.c
... | ... | @@ -45,8 +45,6 @@ |
45 | 45 | { |
46 | 46 | unsigned int next_match; |
47 | 47 | |
48 | - write_seqlock(&xtime_lock); | |
49 | - | |
50 | 48 | if (__raw_readl(MXC_GPT_GPTSR) & GPTSR_OF1) { |
51 | 49 | do { |
52 | 50 | timer_tick(); |
... | ... | @@ -56,8 +54,6 @@ |
56 | 54 | } while ((signed long)(next_match - |
57 | 55 | __raw_readl(MXC_GPT_GPTCNT)) <= 0); |
58 | 56 | } |
59 | - | |
60 | - write_sequnlock(&xtime_lock); | |
61 | 57 | |
62 | 58 | return IRQ_HANDLED; |
63 | 59 | } |
arch/arm/mach-netx/time.c
arch/arm/mach-omap2/timer-gp.c
... | ... | @@ -40,12 +40,8 @@ |
40 | 40 | |
41 | 41 | static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) |
42 | 42 | { |
43 | - write_seqlock(&xtime_lock); | |
44 | - | |
45 | 43 | omap_dm_timer_write_status(gptimer, OMAP_TIMER_INT_OVERFLOW); |
46 | 44 | timer_tick(); |
47 | - | |
48 | - write_sequnlock(&xtime_lock); | |
49 | 45 | |
50 | 46 | return IRQ_HANDLED; |
51 | 47 | } |
arch/arm/mach-pnx4008/time.c
... | ... | @@ -51,8 +51,6 @@ |
51 | 51 | { |
52 | 52 | if (__raw_readl(HSTIM_INT) & MATCH0_INT) { |
53 | 53 | |
54 | - write_seqlock(&xtime_lock); | |
55 | - | |
56 | 54 | do { |
57 | 55 | timer_tick(); |
58 | 56 | |
... | ... | @@ -73,8 +71,6 @@ |
73 | 71 | } while ((signed) |
74 | 72 | (__raw_readl(HSTIM_MATCH0) - |
75 | 73 | __raw_readl(HSTIM_COUNTER)) < 0); |
76 | - | |
77 | - write_sequnlock(&xtime_lock); | |
78 | 74 | } |
79 | 75 | |
80 | 76 | return IRQ_HANDLED; |
arch/arm/mach-realview/core.c
... | ... | @@ -530,8 +530,6 @@ |
530 | 530 | */ |
531 | 531 | static irqreturn_t realview_timer_interrupt(int irq, void *dev_id) |
532 | 532 | { |
533 | - write_seqlock(&xtime_lock); | |
534 | - | |
535 | 533 | // ...clear the interrupt |
536 | 534 | writel(1, TIMER0_VA_BASE + TIMER_INTCLR); |
537 | 535 | |
... | ... | @@ -541,8 +539,6 @@ |
541 | 539 | smp_send_timer(); |
542 | 540 | update_process_times(user_mode(get_irq_regs())); |
543 | 541 | #endif |
544 | - | |
545 | - write_sequnlock(&xtime_lock); | |
546 | 542 | |
547 | 543 | return IRQ_HANDLED; |
548 | 544 | } |
arch/arm/mach-sa1100/time.c
... | ... | @@ -62,8 +62,6 @@ |
62 | 62 | { |
63 | 63 | unsigned int next_match; |
64 | 64 | |
65 | - write_seqlock(&xtime_lock); | |
66 | - | |
67 | 65 | #ifdef CONFIG_NO_IDLE_HZ |
68 | 66 | if (match_posponed) { |
69 | 67 | match_posponed = 0; |
... | ... | @@ -84,8 +82,6 @@ |
84 | 82 | OSSR = OSSR_M0; /* Clear match on timer 0 */ |
85 | 83 | next_match = (OSMR0 += LATCH); |
86 | 84 | } while ((signed long)(next_match - OSCR) <= 0); |
87 | - | |
88 | - write_sequnlock(&xtime_lock); | |
89 | 85 | |
90 | 86 | return IRQ_HANDLED; |
91 | 87 | } |