Commit 2fb02a26bda1cbc3553164a8358c303d936255c5
Committed by
David S. Miller
1 parent
6b1be1990d
Exists in
master
and in
39 other branches
igb: reset sgmii phy at start of init
Our SGMII phy code was incomplete in that it was not actually placing the phy in SGMII mode and as a result the PHY was not able to establish a link when connected to a non serdes link partner. This patch updates the code to combine the SGMII/serdes PCS init and to add the necessary reset. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by: Don Skidmore <donald.c.skidmore@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Showing 4 changed files with 95 additions and 109 deletions Side-by-side Diff
drivers/net/igb/e1000_82575.c
... | ... | @@ -49,11 +49,10 @@ |
49 | 49 | static s32 igb_reset_hw_82575(struct e1000_hw *); |
50 | 50 | static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool); |
51 | 51 | static s32 igb_setup_copper_link_82575(struct e1000_hw *); |
52 | -static s32 igb_setup_fiber_serdes_link_82575(struct e1000_hw *); | |
52 | +static s32 igb_setup_serdes_link_82575(struct e1000_hw *); | |
53 | 53 | static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16); |
54 | 54 | static void igb_clear_hw_cntrs_82575(struct e1000_hw *); |
55 | 55 | static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16); |
56 | -static void igb_configure_pcs_link_82575(struct e1000_hw *); | |
57 | 56 | static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *, |
58 | 57 | u16 *); |
59 | 58 | static s32 igb_get_phy_id_82575(struct e1000_hw *); |
60 | 59 | |
61 | 60 | |
62 | 61 | |
... | ... | @@ -105,16 +104,20 @@ |
105 | 104 | dev_spec->sgmii_active = false; |
106 | 105 | |
107 | 106 | ctrl_ext = rd32(E1000_CTRL_EXT); |
108 | - if ((ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) == | |
109 | - E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES) { | |
110 | - hw->phy.media_type = e1000_media_type_internal_serdes; | |
111 | - ctrl_ext |= E1000_CTRL_I2C_ENA; | |
112 | - } else if (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII) { | |
107 | + switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { | |
108 | + case E1000_CTRL_EXT_LINK_MODE_SGMII: | |
113 | 109 | dev_spec->sgmii_active = true; |
114 | 110 | ctrl_ext |= E1000_CTRL_I2C_ENA; |
115 | - } else { | |
111 | + break; | |
112 | + case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: | |
113 | + hw->phy.media_type = e1000_media_type_internal_serdes; | |
114 | + ctrl_ext |= E1000_CTRL_I2C_ENA; | |
115 | + break; | |
116 | + default: | |
116 | 117 | ctrl_ext &= ~E1000_CTRL_I2C_ENA; |
118 | + break; | |
117 | 119 | } |
120 | + | |
118 | 121 | wr32(E1000_CTRL_EXT, ctrl_ext); |
119 | 122 | |
120 | 123 | /* Set mta register count */ |
... | ... | @@ -134,7 +137,7 @@ |
134 | 137 | mac->ops.setup_physical_interface = |
135 | 138 | (hw->phy.media_type == e1000_media_type_copper) |
136 | 139 | ? igb_setup_copper_link_82575 |
137 | - : igb_setup_fiber_serdes_link_82575; | |
140 | + : igb_setup_serdes_link_82575; | |
138 | 141 | |
139 | 142 | /* NVM initialization */ |
140 | 143 | eecd = rd32(E1000_EECD); |
... | ... | @@ -379,6 +382,7 @@ |
379 | 382 | struct e1000_phy_info *phy = &hw->phy; |
380 | 383 | s32 ret_val = 0; |
381 | 384 | u16 phy_id; |
385 | + u32 ctrl_ext; | |
382 | 386 | |
383 | 387 | /* |
384 | 388 | * For SGMII PHYs, we try the list of possible addresses until |
... | ... | @@ -393,6 +397,12 @@ |
393 | 397 | goto out; |
394 | 398 | } |
395 | 399 | |
400 | + /* Power on sgmii phy if it is disabled */ | |
401 | + ctrl_ext = rd32(E1000_CTRL_EXT); | |
402 | + wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); | |
403 | + wrfl(); | |
404 | + msleep(300); | |
405 | + | |
396 | 406 | /* |
397 | 407 | * The address field in the I2CCMD register is 3 bits and 0 is invalid. |
398 | 408 | * Therefore, we need to test 1-7 |
399 | 409 | |
... | ... | @@ -418,9 +428,12 @@ |
418 | 428 | phy->addr = 0; |
419 | 429 | ret_val = -E1000_ERR_PHY; |
420 | 430 | goto out; |
431 | + } else { | |
432 | + ret_val = igb_get_phy_id(hw); | |
421 | 433 | } |
422 | 434 | |
423 | - ret_val = igb_get_phy_id(hw); | |
435 | + /* restore previous sfp cage power state */ | |
436 | + wr32(E1000_CTRL_EXT, ctrl_ext); | |
424 | 437 | |
425 | 438 | out: |
426 | 439 | return ret_val; |
427 | 440 | |
428 | 441 | |
... | ... | @@ -766,17 +779,18 @@ |
766 | 779 | } |
767 | 780 | |
768 | 781 | /** |
769 | - * igb_shutdown_fiber_serdes_link_82575 - Remove link during power down | |
782 | + * igb_shutdown_serdes_link_82575 - Remove link during power down | |
770 | 783 | * @hw: pointer to the HW structure |
771 | 784 | * |
772 | 785 | * In the case of fiber serdes, shut down optics and PCS on driver unload |
773 | 786 | * when management pass thru is not enabled. |
774 | 787 | **/ |
775 | -void igb_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw) | |
788 | +void igb_shutdown_serdes_link_82575(struct e1000_hw *hw) | |
776 | 789 | { |
777 | 790 | u32 reg; |
778 | 791 | |
779 | - if (hw->phy.media_type != e1000_media_type_internal_serdes) | |
792 | + if (hw->phy.media_type != e1000_media_type_internal_serdes || | |
793 | + igb_sgmii_active_82575(hw)) | |
780 | 794 | return; |
781 | 795 | |
782 | 796 | /* if the management interface is not enabled, then power down */ |
... | ... | @@ -788,7 +802,7 @@ |
788 | 802 | |
789 | 803 | /* shutdown the laser */ |
790 | 804 | reg = rd32(E1000_CTRL_EXT); |
791 | - reg |= E1000_CTRL_EXT_SDP7_DATA; | |
805 | + reg |= E1000_CTRL_EXT_SDP3_DATA; | |
792 | 806 | wr32(E1000_CTRL_EXT, reg); |
793 | 807 | |
794 | 808 | /* flush the write to verify completion */ |
... | ... | @@ -927,6 +941,17 @@ |
927 | 941 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
928 | 942 | wr32(E1000_CTRL, ctrl); |
929 | 943 | |
944 | + ret_val = igb_setup_serdes_link_82575(hw); | |
945 | + if (ret_val) | |
946 | + goto out; | |
947 | + | |
948 | + if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) { | |
949 | + ret_val = hw->phy.ops.reset(hw); | |
950 | + if (ret_val) { | |
951 | + hw_dbg("Error resetting the PHY.\n"); | |
952 | + goto out; | |
953 | + } | |
954 | + } | |
930 | 955 | switch (hw->phy.type) { |
931 | 956 | case e1000_phy_m88: |
932 | 957 | ret_val = igb_copper_link_setup_m88(hw); |
... | ... | @@ -963,8 +988,6 @@ |
963 | 988 | } |
964 | 989 | } |
965 | 990 | |
966 | - igb_configure_pcs_link_82575(hw); | |
967 | - | |
968 | 991 | /* |
969 | 992 | * Check link status. Wait up to 100 microseconds for link to become |
970 | 993 | * valid. |
971 | 994 | |
972 | 995 | |
973 | 996 | |
... | ... | @@ -987,15 +1010,19 @@ |
987 | 1010 | } |
988 | 1011 | |
989 | 1012 | /** |
990 | - * igb_setup_fiber_serdes_link_82575 - Setup link for fiber/serdes | |
1013 | + * igb_setup_serdes_link_82575 - Setup link for fiber/serdes | |
991 | 1014 | * @hw: pointer to the HW structure |
992 | 1015 | * |
993 | 1016 | * Configures speed and duplex for fiber and serdes links. |
994 | 1017 | **/ |
995 | -static s32 igb_setup_fiber_serdes_link_82575(struct e1000_hw *hw) | |
1018 | +static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw) | |
996 | 1019 | { |
997 | - u32 reg; | |
1020 | + u32 ctrl_reg, reg; | |
998 | 1021 | |
1022 | + if ((hw->phy.media_type != e1000_media_type_internal_serdes) && | |
1023 | + !igb_sgmii_active_82575(hw)) | |
1024 | + return 0; | |
1025 | + | |
999 | 1026 | /* |
1000 | 1027 | * On the 82575, SerDes loopback mode persists until it is |
1001 | 1028 | * explicitly turned off or a power cycle is performed. A read to |
1002 | 1029 | |
1003 | 1030 | |
1004 | 1031 | |
1005 | 1032 | |
1006 | 1033 | |
... | ... | @@ -1004,39 +1031,60 @@ |
1004 | 1031 | */ |
1005 | 1032 | wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); |
1006 | 1033 | |
1007 | - /* Force link up, set 1gb, set both sw defined pins */ | |
1008 | - reg = rd32(E1000_CTRL); | |
1009 | - reg |= E1000_CTRL_SLU | | |
1010 | - E1000_CTRL_SPD_1000 | | |
1011 | - E1000_CTRL_FRCSPD | | |
1012 | - E1000_CTRL_SWDPIN0 | | |
1013 | - E1000_CTRL_SWDPIN1; | |
1014 | - wr32(E1000_CTRL, reg); | |
1034 | + /* power on the sfp cage if present */ | |
1035 | + reg = rd32(E1000_CTRL_EXT); | |
1036 | + reg &= ~E1000_CTRL_EXT_SDP3_DATA; | |
1037 | + wr32(E1000_CTRL_EXT, reg); | |
1015 | 1038 | |
1016 | - /* Power on phy for 82576 fiber adapters */ | |
1017 | - if (hw->mac.type == e1000_82576) { | |
1018 | - reg = rd32(E1000_CTRL_EXT); | |
1019 | - reg &= ~E1000_CTRL_EXT_SDP7_DATA; | |
1020 | - wr32(E1000_CTRL_EXT, reg); | |
1039 | + ctrl_reg = rd32(E1000_CTRL); | |
1040 | + ctrl_reg |= E1000_CTRL_SLU; | |
1041 | + | |
1042 | + if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) { | |
1043 | + /* set both sw defined pins */ | |
1044 | + ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; | |
1045 | + | |
1046 | + /* Set switch control to serdes energy detect */ | |
1047 | + reg = rd32(E1000_CONNSW); | |
1048 | + reg |= E1000_CONNSW_ENRGSRC; | |
1049 | + wr32(E1000_CONNSW, reg); | |
1021 | 1050 | } |
1022 | 1051 | |
1023 | - /* Set switch control to serdes energy detect */ | |
1024 | - reg = rd32(E1000_CONNSW); | |
1025 | - reg |= E1000_CONNSW_ENRGSRC; | |
1026 | - wr32(E1000_CONNSW, reg); | |
1052 | + reg = rd32(E1000_PCS_LCTL); | |
1027 | 1053 | |
1054 | + if (igb_sgmii_active_82575(hw)) { | |
1055 | + /* allow time for SFP cage to power up phy */ | |
1056 | + msleep(300); | |
1057 | + | |
1058 | + /* AN time out should be disabled for SGMII mode */ | |
1059 | + reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); | |
1060 | + } else { | |
1061 | + ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD | | |
1062 | + E1000_CTRL_FD | E1000_CTRL_FRCDPX; | |
1063 | + } | |
1064 | + | |
1065 | + wr32(E1000_CTRL, ctrl_reg); | |
1066 | + | |
1028 | 1067 | /* |
1029 | 1068 | * New SerDes mode allows for forcing speed or autonegotiating speed |
1030 | 1069 | * at 1gb. Autoneg should be default set by most drivers. This is the |
1031 | 1070 | * mode that will be compatible with older link partners and switches. |
1032 | 1071 | * However, both are supported by the hardware and some drivers/tools. |
1033 | 1072 | */ |
1034 | - reg = rd32(E1000_PCS_LCTL); | |
1035 | 1073 | |
1036 | 1074 | reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | |
1037 | 1075 | E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); |
1038 | 1076 | |
1039 | - if (hw->mac.autoneg) { | |
1077 | + /* | |
1078 | + * We force flow control to prevent the CTRL register values from being | |
1079 | + * overwritten by the autonegotiated flow control values | |
1080 | + */ | |
1081 | + reg |= E1000_PCS_LCTL_FORCE_FCTRL; | |
1082 | + | |
1083 | + /* | |
1084 | + * we always set sgmii to autoneg since it is the phy that will be | |
1085 | + * forcing the link and the serdes is just a go-between | |
1086 | + */ | |
1087 | + if (hw->mac.autoneg || igb_sgmii_active_82575(hw)) { | |
1040 | 1088 | /* Set PCS register for autoneg */ |
1041 | 1089 | reg |= E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ |
1042 | 1090 | E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ |
1043 | 1091 | |
1044 | 1092 | |
... | ... | @@ -1053,78 +1101,15 @@ |
1053 | 1101 | hw_dbg("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg); |
1054 | 1102 | } |
1055 | 1103 | |
1056 | - if (hw->mac.type == e1000_82576) { | |
1057 | - reg |= E1000_PCS_LCTL_FORCE_FCTRL; | |
1058 | - igb_force_mac_fc(hw); | |
1059 | - } | |
1060 | - | |
1061 | 1104 | wr32(E1000_PCS_LCTL, reg); |
1062 | 1105 | |
1106 | + if (!igb_sgmii_active_82575(hw)) | |
1107 | + igb_force_mac_fc(hw); | |
1108 | + | |
1063 | 1109 | return 0; |
1064 | 1110 | } |
1065 | 1111 | |
1066 | 1112 | /** |
1067 | - * igb_configure_pcs_link_82575 - Configure PCS link | |
1068 | - * @hw: pointer to the HW structure | |
1069 | - * | |
1070 | - * Configure the physical coding sub-layer (PCS) link. The PCS link is | |
1071 | - * only used on copper connections where the serialized gigabit media | |
1072 | - * independent interface (sgmii) is being used. Configures the link | |
1073 | - * for auto-negotiation or forces speed/duplex. | |
1074 | - **/ | |
1075 | -static void igb_configure_pcs_link_82575(struct e1000_hw *hw) | |
1076 | -{ | |
1077 | - struct e1000_mac_info *mac = &hw->mac; | |
1078 | - u32 reg = 0; | |
1079 | - | |
1080 | - if (hw->phy.media_type != e1000_media_type_copper || | |
1081 | - !(igb_sgmii_active_82575(hw))) | |
1082 | - return; | |
1083 | - | |
1084 | - /* For SGMII, we need to issue a PCS autoneg restart */ | |
1085 | - reg = rd32(E1000_PCS_LCTL); | |
1086 | - | |
1087 | - /* AN time out should be disabled for SGMII mode */ | |
1088 | - reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); | |
1089 | - | |
1090 | - if (mac->autoneg) { | |
1091 | - /* Make sure forced speed and force link are not set */ | |
1092 | - reg &= ~(E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); | |
1093 | - | |
1094 | - /* | |
1095 | - * The PHY should be setup prior to calling this function. | |
1096 | - * All we need to do is restart autoneg and enable autoneg. | |
1097 | - */ | |
1098 | - reg |= E1000_PCS_LCTL_AN_RESTART | E1000_PCS_LCTL_AN_ENABLE; | |
1099 | - } else { | |
1100 | - /* Set PCS register for forced speed */ | |
1101 | - | |
1102 | - /* Turn off bits for full duplex, speed, and autoneg */ | |
1103 | - reg &= ~(E1000_PCS_LCTL_FSV_1000 | | |
1104 | - E1000_PCS_LCTL_FSV_100 | | |
1105 | - E1000_PCS_LCTL_FDV_FULL | | |
1106 | - E1000_PCS_LCTL_AN_ENABLE); | |
1107 | - | |
1108 | - /* Check for duplex first */ | |
1109 | - if (mac->forced_speed_duplex & E1000_ALL_FULL_DUPLEX) | |
1110 | - reg |= E1000_PCS_LCTL_FDV_FULL; | |
1111 | - | |
1112 | - /* Now set speed */ | |
1113 | - if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) | |
1114 | - reg |= E1000_PCS_LCTL_FSV_100; | |
1115 | - | |
1116 | - /* Force speed and force link */ | |
1117 | - reg |= E1000_PCS_LCTL_FSD | | |
1118 | - E1000_PCS_LCTL_FORCE_LINK | | |
1119 | - E1000_PCS_LCTL_FLV_LINK_UP; | |
1120 | - | |
1121 | - hw_dbg("Wrote 0x%08X to PCS_LCTL to configure forced link\n", | |
1122 | - reg); | |
1123 | - } | |
1124 | - wr32(E1000_PCS_LCTL, reg); | |
1125 | -} | |
1126 | - | |
1127 | -/** | |
1128 | 1113 | * igb_sgmii_active_82575 - Return sgmii state |
1129 | 1114 | * @hw: pointer to the HW structure |
1130 | 1115 | * |
... | ... | @@ -1248,7 +1233,8 @@ |
1248 | 1233 | temp = rd32(E1000_LENERRS); |
1249 | 1234 | |
1250 | 1235 | /* This register should not be read in copper configurations */ |
1251 | - if (hw->phy.media_type == e1000_media_type_internal_serdes) | |
1236 | + if (hw->phy.media_type == e1000_media_type_internal_serdes || | |
1237 | + igb_sgmii_active_82575(hw)) | |
1252 | 1238 | temp = rd32(E1000_SCVPC); |
1253 | 1239 | } |
1254 | 1240 |
drivers/net/igb/e1000_82575.h
... | ... | @@ -28,7 +28,7 @@ |
28 | 28 | #ifndef _E1000_82575_H_ |
29 | 29 | #define _E1000_82575_H_ |
30 | 30 | |
31 | -extern void igb_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw); | |
31 | +extern void igb_shutdown_serdes_link_82575(struct e1000_hw *hw); | |
32 | 32 | extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw); |
33 | 33 | |
34 | 34 | #define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \ |
drivers/net/igb/e1000_defines.h
... | ... | @@ -44,7 +44,7 @@ |
44 | 44 | #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ |
45 | 45 | |
46 | 46 | /* Extended Device Control */ |
47 | -#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */ | |
47 | +#define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Defineable Pin 3 */ | |
48 | 48 | /* Physical Func Reset Done Indication */ |
49 | 49 | #define E1000_CTRL_EXT_PFRSTD 0x00004000 |
50 | 50 | #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 |
drivers/net/igb/igb_main.c
... | ... | @@ -5320,7 +5320,7 @@ |
5320 | 5320 | |
5321 | 5321 | *enable_wake = wufc || adapter->en_mng_pt; |
5322 | 5322 | if (!*enable_wake) |
5323 | - igb_shutdown_fiber_serdes_link_82575(hw); | |
5323 | + igb_shutdown_serdes_link_82575(hw); | |
5324 | 5324 | |
5325 | 5325 | /* Release control of h/w to f/w. If f/w is AMT enabled, this |
5326 | 5326 | * would have already happened in close and is redundant. */ |