Eric Lee / smarc-fsl-linux-kernel

Download as
Browse Code ยป

Commit 34acb09025a132943555d0f0ffca6cb05c698cd4

Authored by dmitry pervushin
Committed by Russell King
1 parent 1e3dd535d6

[ARM] 5468/1: Freescale STMP platform support [3/10] 

Minimal definition of register set for 37xx boards

Signed-off-by: dmitry pervushin <dpervushin@embeddedalley.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Showing 7 changed files with 574 additions and 0 deletions Side-by-side Diff

arch/arm/mach-stmp37xx/include/mach/regs-apbh.h
Diff comments   View file @ 34acb09
  1 +/*
  2 + * STMP APBH Register Definitions
  3 + *
  4 + * Copyright (c) 2008 Freescale Semiconductor
  5 + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
  6 + *
  7 + * This program is free software; you can redistribute it and/or modify
  8 + * it under the terms of the GNU General Public License as published by
  9 + * the Free Software Foundation; either version 2 of the License, or
  10 + * (at your option) any later version.
  11 + *
  12 + * This program is distributed in the hope that it will be useful,
  13 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 + * GNU General Public License for more details.
  16 + *
  17 + * You should have received a copy of the GNU General Public License
  18 + * along with this program; if not, write to the Free Software
  19 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20 + */
  21 +#ifndef _INCLUDE_ASM_ARCH_REGS_APBH_H
  22 +#define _INCLUDE_ASM_ARCH_REGS_APBH_H
  23 +
  24 +#include <mach/stmp3xxx_regs.h>
  25 +
  26 +#ifndef REGS_APBH_BASE
  27 +#define REGS_APBH_BASE (REGS_BASE + 0x00004000)
  28 +#endif
  29 +
  30 +HW_REGISTER(HW_APBH_CTRL0, REGS_APBH_BASE, 0x00)
  31 +#define BP_APBH_CTRL0_SFTRST 31
  32 +#define BM_APBH_CTRL0_SFTRST 0x80000000
  33 +#define BP_APBH_CTRL0_CLKGATE 30
  34 +#define BM_APBH_CTRL0_CLKGATE 0x40000000
  35 +#define BP_APBH_CTRL0_RESET_CHANNEL 16
  36 +#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000
  37 +#define BF_APBH_CTRL0_RESET_CHANNEL(v) \
  38 + (((v) << BP_APBH_CTRL0_RESET_CHANNEL) & BM_APBH_CTRL0_RESET_CHANNEL)
  39 +HW_REGISTER(HW_APBH_CTRL1, REGS_APBH_BASE, 0x10)
  40 +#define BP_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN 9
  41 +#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN 0x00000200
  42 +#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN 8
  43 +#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN 0x00000100
  44 +#define BP_APBH_CTRL1_CH7_CMDCMPLT_IRQ 7
  45 +#define BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ 0x00000080
  46 +#define BP_APBH_CTRL1_CH1_CMDCMPLT_IRQ 1
  47 +#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ 0x00000002
  48 +#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0
  49 +#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001
  50 +#define BP_APBH_CTRL1_CH1_ERR_IRQ 17
  51 +#define BM_APBH_CTRL1_CH1_ERR_IRQ 0x00020000
  52 +HW_REGISTER_0(HW_APBH_DEVSEL, REGS_APBH_BASE, 0x20)
  53 +HW_REGISTER_RO_INDEXED(HW_APBH_CHn_CURCMDAR, REGS_APBH_BASE, 0x40, 0x70)
  54 +HW_REGISTER_0_INDEXED(HW_APBH_CHn_NXTCMDAR, REGS_APBH_BASE, 0x50, 0x70)
  55 +#define BP_APBH_CHn_NXTCMDAR_CMD_ADDR 0
  56 +#define BM_APBH_CHn_NXTCMDAR_CMD_ADDR 0xFFFFFFFF
  57 +#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v) ((u32) v)
  58 +HW_REGISTER_RO_INDEXED(HW_APBH_CHn_CMD, REGS_APBH_BASE, 0x60, 0x70)
  59 +#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000
  60 +#define BP_APBH_CHn_CMD_XFER_COUNT 16
  61 +#define BF_APBH_CHn_CMD_XFER_COUNT(v) \
  62 + (((v) << BP_APBH_CHn_CMD_XFER_COUNT) & BM_APBH_CHn_CMD_XFER_COUNT)
  63 +#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000
  64 +#define BP_APBH_CHn_CMD_CMDWORDS 12
  65 +#define BF_APBH_CHn_CMD_CMDWORDS(v) \
  66 + (((v) << BP_APBH_CHn_CMD_CMDWORDS) & BM_APBH_CHn_CMD_CMDWORDS)
  67 +#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080
  68 +#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040
  69 +#define BP_APBH_CHn_CMD_SEMAPHORE 6
  70 +#define BF_APBH_CHn_CMD_SEMAPHORE(v) \
  71 + (((v) << BP_APBH_CHn_CMD_SEMAPHORE) & BM_APBH_CHn_CMD_SEMAPHORE)
  72 +#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020
  73 +#define BP_APBH_CHn_CMD_NANDLOCK 4
  74 +#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010
  75 +#define BF_APBH_CHn_CMD_NANDLOCK(v) \
  76 + (((v) << BP_APBH_CHn_CMD_NANDLOCK) & BM_APBH_CHn_CMD_NANDLOCK)
  77 +#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008
  78 +#define BM_APBH_CHn_CMD_CHAIN 0x00000004
  79 +#define BM_APBH_CHn_CMD_DMA_READ 0x00000003
  80 +#define BP_APBH_CHn_CMD_DMA_READ 0
  81 +#define BF_APBH_CHn_CMD_DMA_READ(v) \
  82 + (((v) << BP_APBH_CHn_CMD_DMA_READ) & BM_APBH_CHn_CMD_DMA_READ)
  83 +#define BF_APBH_CHn_CMD_COMMAND(v) \
  84 + (((v) << BP_APBH_CHn_CMD_DMA_READ) & BM_APBH_CHn_CMD_DMA_READ)
  85 +#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0x0
  86 +#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 0x1
  87 +#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 0x2
  88 +#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 0x3
  89 +HW_REGISTER_INDEXED(HW_APBH_CHn_BAR, REGS_APBH_BASE, 0x70, 0x70)
  90 +HW_REGISTER_0_INDEXED(HW_APBH_CHn_SEMA, REGS_APBH_BASE, 0x80, 0x70)
  91 +#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0
  92 +#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF
  93 +#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v) \
  94 + (((v) << BP_APBH_CHn_SEMA_INCREMENT_SEMA) & \
  95 + BM_APBH_CHn_SEMA_INCREMENT_SEMA)
  96 +#define BP_APBH_CHn_SEMA_PHORE 16
  97 +#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000
  98 +HW_REGISTER_RO_INDEXED(HW_APBH_CHn_DEBUG1, REGS_APBH_BASE, 0x90, 0x70)
  99 +HW_REGISTER_RO_INDEXED(HW_APBH_CHn_DEBUG2, REGS_APBH_BASE, 0xA0, 0x70)
  100 +HW_REGISTER_RO(HW_APBH_VERSION, REGS_APBH_BASE, 0x3F0)
  101 +
  102 +#endif /* _INCLUDE_ASM_ARCH_REGS_APBH_H */
arch/arm/mach-stmp37xx/include/mach/regs-apbx.h
Diff comments   View file @ 34acb09
  1 +/*
  2 + * STMP APBX Register Definitions
  3 + *
  4 + * Copyright (c) 2008 Freescale Semiconductor
  5 + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
  6 + *
  7 + * This program is free software; you can redistribute it and/or modify
  8 + * it under the terms of the GNU General Public License as published by
  9 + * the Free Software Foundation; either version 2 of the License, or
  10 + * (at your option) any later version.
  11 + *
  12 + * This program is distributed in the hope that it will be useful,
  13 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 + * GNU General Public License for more details.
  16 + *
  17 + * You should have received a copy of the GNU General Public License
  18 + * along with this program; if not, write to the Free Software
  19 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20 + */
  21 +#ifndef _INCLUDE_ASM_ARCH_REGS_APBX_H
  22 +#define _INCLUDE_ASM_ARCH_REGS_APBX_H
  23 +
  24 +#include <mach/stmp3xxx_regs.h>
  25 +
  26 +#ifndef REGS_APBX_BASE
  27 +#define REGS_APBX_BASE (REGS_BASE + 0x00024000)
  28 +#endif
  29 +
  30 +HW_REGISTER(HW_APBX_CTRL0, REGS_APBX_BASE, 0x00)
  31 +#define BP_APBX_CTRL0_SFTRST 31
  32 +#define BM_APBX_CTRL0_SFTRST 0x80000000
  33 +#define BP_APBX_CTRL0_CLKGATE 30
  34 +#define BM_APBX_CTRL0_CLKGATE 0x40000000
  35 +#define BP_APBX_CTRL0_RESET_CHANNEL 16
  36 +#define BM_APBX_CTRL0_RESET_CHANNEL 0x00FF0000
  37 +#define BF_APBX_CTRL0_RESET_CHANNEL(v) \
  38 + (((v) << BP_APBX_CTRL0_RESET_CHANNEL) & BM_APBX_CTRL0_RESET_CHANNEL)
  39 +HW_REGISTER(HW_APBX_CTRL1, REGS_APBX_BASE, 0x10)
  40 +HW_REGISTER_0(HW_APBX_DEVSEL, REGS_APBX_BASE, 0x20)
  41 +#define BP_APBX_DEVSEL_CH7 28
  42 +#define BM_APBX_DEVSEL_CH7 0xF0000000
  43 +#define BF_APBX_DEVSEL_CH7(v) \
  44 + (((v) << BP_APBX_DEVSEL_CH7) & BM_APBX_DEVSEL_CH7)
  45 +#define BV_APBX_DEVSEL_CH7__USE_UART 0x0
  46 +#define BV_APBX_DEVSEL_CH7__USE_IRDA 0x1
  47 +#define BP_APBX_DEVSEL_CH6 24
  48 +#define BM_APBX_DEVSEL_CH6 0x0F000000
  49 +#define BF_APBX_DEVSEL_CH6(v) \
  50 + (((v) << BP_APBX_DEVSEL_CH6) & BM_APBX_DEVSEL_CH6)
  51 +#define BV_APBX_DEVSEL_CH6__USE_UART 0x0
  52 +#define BV_APBX_DEVSEL_CH6__USE_IRDA 0x1
  53 +#define BP_APBX_CTRL1_CH7_AHB_ERROR_IRQ 23
  54 +#define BM_APBX_CTRL1_CH7_AHB_ERROR_IRQ 0x00800000
  55 +#define BP_APBX_CTRL1_CH6_AHB_ERROR_IRQ 22
  56 +#define BM_APBX_CTRL1_CH6_AHB_ERROR_IRQ 0x00400000
  57 +#define BP_APBX_CTRL1_CH7_CMDCMPLT_IRQ_EN 15
  58 +#define BM_APBX_CTRL1_CH7_CMDCMPLT_IRQ_EN 0x00008000
  59 +#define BP_APBX_CTRL1_CH6_CMDCMPLT_IRQ_EN 14
  60 +#define BM_APBX_CTRL1_CH6_CMDCMPLT_IRQ_EN 0x00004000
  61 +
  62 +HW_REGISTER_RO_INDEXED(HW_APBX_CHn_CURCMDAR, REGS_APBX_BASE, 0x40, 0x70)
  63 +HW_REGISTER_0_INDEXED(HW_APBX_CHn_NXTCMDAR, REGS_APBX_BASE, 0x50, 0x70)
  64 +#define BP_APBX_CHn_NXTCMDAR_CMD_ADDR 0
  65 +#define BM_APBX_CHn_NXTCMDAR_CMD_ADDR 0xFFFFFFFF
  66 +#define BF_APBX_CHn_NXTCMDAR_CMD_ADDR(v) ((u32) v)
  67 +HW_REGISTER_RO_INDEXED(HW_APBX_CHn_CMD, REGS_APBX_BASE, 0x60, 0x70)
  68 +#define BP_APBX_CHn_CMD_XFER_COUNT 16
  69 +#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000
  70 +#define BF_APBX_CHn_CMD_XFER_COUNT(v) \
  71 + (((v) << BP_APBX_CHn_CMD_XFER_COUNT) & BM_APBX_CHn_CMD_XFER_COUNT)
  72 +#define BP_APBX_CHn_CMD_CMDWORDS 12
  73 +#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000
  74 +#define BF_APBX_CHn_CMD_CMDWORDS(v) \
  75 + (((v) << BP_APBX_CHn_CMD_CMDWORDS) & BM_APBX_CHn_CMD_CMDWORDS)
  76 +#define BP_APBX_CHn_CMD_WAIT4ENDCMD 7
  77 +#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080
  78 +#define BP_APBX_CHn_CMD_SEMAPHORE 6
  79 +#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040
  80 +#define BP_APBX_CHn_CMD_IRQONCMPLT 3
  81 +#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008
  82 +#define BP_APBX_CHn_CMD_CHAIN 2
  83 +#define BM_APBX_CHn_CMD_CHAIN 0x00000004
  84 +#define BM_APBX_CHn_CMD_DMA_READ 0x00000003
  85 +#define BP_APBX_CHn_CMD_DMA_READ 0
  86 +#define BF_APBX_CHn_CMD_DMA_READ(v) \
  87 + (((v) << BP_APBX_CHn_CMD_DMA_READ) & BM_APBX_CHn_CMD_DMA_READ)
  88 +#define BP_APBX_CHn_CMD_COMMAND 0
  89 +#define BM_APBX_CHn_CMD_COMMAND 0x00000003
  90 +#define BF_APBX_CHn_CMD_COMMAND(v) \
  91 + (((v) << BP_APBX_CHn_CMD_COMMAND) & BM_APBX_CHn_CMD_COMMAND)
  92 +#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0x0
  93 +#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 0x1
  94 +#define BV_APBX_CHn_CMD_COMMAND__DMA_READ 0x2
  95 +
  96 +HW_REGISTER_RO_INDEXED(HW_APBX_CHn_BAR, REGS_APBX_BASE, 0x70, 0x70)
  97 +HW_REGISTER_0_INDEXED(HW_APBX_CHn_SEMA, REGS_APBX_BASE, 0x80, 0x70)
  98 +#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0
  99 +#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF
  100 +#define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v) \
  101 + (((v) << BP_APBX_CHn_SEMA_INCREMENT_SEMA) & \
  102 + BM_APBX_CHn_SEMA_INCREMENT_SEMA)
  103 +#define BP_APBX_CHn_SEMA_PHORE 16
  104 +#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000
  105 +HW_REGISTER_RO_INDEXED(HW_APBX_CHn_DEBUG1, REGS_APBX_BASE, 0x90, 0x70)
  106 +HW_REGISTER_RO_INDEXED(HW_APBX_CHn_DEBUG2, REGS_APBX_BASE, 0xA0, 0x70)
  107 +HW_REGISTER_RO(HW_APBX_VERSION, REGS_APBX_BASE, 0x3F0)
  108 +
  109 +#endif /* _INCLUDE_ASM_ARCH_REGS_APBX_H */
arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h
Diff comments   View file @ 34acb09
  1 +#ifndef _INCLUDE_ASM_ARCH_REGS_CLKCTRL_H
  2 +#define _INCLUDE_ASM_ARCH_REGS_CLKCTRL_H
  3 +
  4 +#include <mach/stmp3xxx_regs.h>
  5 +
  6 +#define REGS_CLKCTRL_BASE (REGS_BASE + 0x00040000)
  7 +
  8 +#define HW_CLKCTRL_PLLCTRL0_ADDR (REGS_CLKCTRL_BASE + 0x00)
  9 +HW_REGISTER(HW_CLKCTRL_PLLCTRL0, REGS_CLKCTRL_BASE, 0x00)
  10 +#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
  11 +#define HW_CLKCTRL_PLLCTRL1_ADDR (REGS_CLKCTRL_BASE + 0x10)
  12 +HW_REGISTER(HW_CLKCTRL_PLLCTRL1, REGS_CLKCTRL_BASE, 0x10)
  13 +
  14 +#define HW_CLKCTRL_CPU_ADDR (REGS_CLKCTRL_BASE + 0x20)
  15 +HW_REGISTER(HW_CLKCTRL_CPU, REGS_CLKCTRL_BASE, 0x20)
  16 +#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
  17 +#define BF_CLKCTRL_CPU_DIV_CPU(v) \
  18 + (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU)
  19 +
  20 +#define HW_CLKCTRL_HBUS_ADDR (REGS_CLKCTRL_BASE + 0x30)
  21 +HW_REGISTER(HW_CLKCTRL_HBUS, REGS_CLKCTRL_BASE, 0x30)
  22 +#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0 /* for compatitibility */
  23 +#define BM_CLKCTRL_HBUS_DIV 0x0000001F
  24 +#define BF_CLKCTRL_HBUS_DIV(v) \
  25 + (((v) << 0) & BM_CLKCTRL_HBUS_DIV)
  26 +#define HW_CLKCTRL_XBUS_ADDR (REGS_CLKCTRL_BASE + 0x40)
  27 +HW_REGISTER(HW_CLKCTRL_XBUS, REGS_CLKCTRL_BASE, 0x40)
  28 +#define HW_CLKCTRL_XTAL_ADDR (REGS_CLKCTRL_BASE + 0x50)
  29 +HW_REGISTER(HW_CLKCTRL_XTAL, REGS_CLKCTRL_BASE, 0x50)
  30 +#define HW_CLKCTRL_PIX_ADDR (REGS_CLKCTRL_BASE + 0x60)
  31 +HW_REGISTER(HW_CLKCTRL_PIX, REGS_CLKCTRL_BASE, 0x60)
  32 +#define BM_CLKCTRL_PIX_CLKGATE 0x80000000
  33 +#define BM_CLKCTRL_PIX_BUSY 0x20000000
  34 +#define BM_CLKCTRL_PIX_DIV 0x00007FFF
  35 +#define BP_CLKCTRL_PIX_DIV 0
  36 +#define BF_CLKCTRL_PIX_DIV(v) \
  37 + (((v) << BP_CLKCTRL_PIX_DIV) & BM_CLKCTRL_PIX_DIV)
  38 +#define HW_CLKCTRL_SSP_ADDR (REGS_CLKCTRL_BASE + 0x70)
  39 +HW_REGISTER(HW_CLKCTRL_SSP, REGS_CLKCTRL_BASE, 0x70)
  40 +#define HW_CLKCTRL_GPMI_ADDR (REGS_CLKCTRL_BASE + 0x80)
  41 +HW_REGISTER(HW_CLKCTRL_GPMI, REGS_CLKCTRL_BASE, 0x80)
  42 +#define HW_CLKCTRL_SPDIF_ADDR (REGS_CLKCTRL_BASE + 0x90)
  43 +HW_REGISTER(HW_CLKCTRL_SPDIF, REGS_CLKCTRL_BASE, 0x90)
  44 +#define HW_CLKCTRL_EMI_ADDR (REGS_CLKCTRL_BASE + 0xA0)
  45 +HW_REGISTER(HW_CLKCTRL_EMI, REGS_CLKCTRL_BASE, 0xA0)
  46 +#define HW_CLKCTRL_IR_ADDR (REGS_CLKCTRL_BASE + 0xB0)
  47 +HW_REGISTER(HW_CLKCTRL_IR, REGS_CLKCTRL_BASE, 0xB0)
  48 +#define HW_CLKCTRL_SAIF_ADDR (REGS_CLKCTRL_BASE + 0xC0)
  49 +HW_REGISTER(HW_CLKCTRL_SAIF, REGS_CLKCTRL_BASE, 0xC0)
  50 +#define HW_CLKCTRL_FRAC_ADDR (REGS_CLKCTRL_BASE + 0xD0)
  51 +HW_REGISTER(HW_CLKCTRL_FRAC, REGS_CLKCTRL_BASE, 0xD0)
  52 +#define BM_CLKCTRL_FRAC_CLKGATEIO 0x80000000
  53 +#define BM_CLKCTRL_FRAC_IO_STABLE 0x40000000
  54 +#define BM_CLKCTRL_FRAC_IOFRAC 0x3F000000
  55 +#define BP_CLKCTRL_FRAC_IOFRAC 24
  56 +#define BF_CLKCTRL_FRAC_IOFRAC(v) \
  57 + (((v) << BP_CLKCTRL_FRAC_IOFRAC) & BM_CLKCTRL_FRAC_IOFRAC)
  58 +#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000
  59 +#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000
  60 +#define BP_CLKCTRL_FRAC_PIXFRAC 16
  61 +#define BF_CLKCTRL_FRAC_PIXFRAC(v) \
  62 + (((v) << BP_CLKCTRL_FRAC_PIXFRAC) & BM_CLKCTRL_FRAC_PIXFRAC)
  63 +#define BM_CLKCTRL_FRAC_CLKGATEEMI 0x00008000
  64 +#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00
  65 +#define BP_CLKCTRL_FRAC_EMIFRAC 8
  66 +#define BF_CLKCTRL_FRAC_EMIFRAC(v) \
  67 + (((v) << BP_CLKCTRL_FRAC_EMIFRAC) & BM_CLKCTRL_FRAC_EMIFRAC)
  68 +#define BM_CLKCTRL_FRAC_CLKGATECPU 0x00000080
  69 +#define BM_CLKCTRL_FRAC_CPUFRAC 0x0000003F
  70 +#define BP_CLKCTRL_FRAC_CPUFRAC 0
  71 +#define BF_CLKCTRL_FRAC_CPUFRAC(v) \
  72 + (((v) << BP_CLKCTRL_FRAC_CPUFRAC) & BM_CLKCTRL_FRAC_CPUFRAC)
  73 +#define HW_CLKCTRL_CLKSEQ_ADDR (REGS_CLKCTRL_BASE + 0xE0)
  74 +HW_REGISTER(HW_CLKCTRL_CLKSEQ, REGS_CLKCTRL_BASE, 0xE0)
  75 +#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00000080
  76 +#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000040
  77 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x00000020
  78 +#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000010
  79 +#define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x00000008
  80 +#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002
  81 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x00000001
  82 +HW_REGISTER_WO(HW_CLKCTRL_RESET, REGS_CLKCTRL_BASE, 0xF0)
  83 +#define BM_CLKCTRL_RESET_CHIP 0x00000002
  84 +#define BM_CLKCTRL_RESET_DIG 0x00000001
  85 +#endif /* _INCLUDE_ASM_ARCH_REGS_CLKCTRL_H */
arch/arm/mach-stmp37xx/include/mach/regs-icoll.h
Diff comments   View file @ 34acb09
  1 +/*
  2 + * Freescale STMP378X: clock registers definitions
  3 + *
  4 + * Embedded Alley Solutions, Inc <source@embeddedalley.com>
  5 + *
  6 + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
  7 + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
  8 + */
  9 +
  10 +/*
  11 + * The code contained herein is licensed under the GNU General Public
  12 + * License. You may obtain a copy of the GNU General Public License
  13 + * Version 2 or later at the following locations:
  14 + *
  15 + * http://www.opensource.org/licenses/gpl-license.html
  16 + * http://www.gnu.org/copyleft/gpl.html
  17 + */
  18 +
  19 +#ifndef _INCLUDE_ASM_ARCH_REGS_ICOLL_H
  20 +#define _INCLUDE_ASM_ARCH_REGS_ICOLL_H
  21 +
  22 +
  23 +#include <mach/stmp3xxx_regs.h>
  24 +
  25 +#define REGS_ICOLL_BASE (REGS_BASE + 0x00000000)
  26 +
  27 +HW_REGISTER(HW_ICOLL_VECTOR, REGS_ICOLL_BASE, 0x00)
  28 +HW_REGISTER_WO(HW_ICOLL_LEVELACK, REGS_ICOLL_BASE, 0x10)
  29 +HW_REGISTER(HW_ICOLL_CTRL, REGS_ICOLL_BASE, 0x20)
  30 +#define BM_ICOLL_CTRL_CLKGATE 0x40000000
  31 +#define BM_ICOLL_CTRL_SFTRST 0x80000000
  32 +HW_REGISTER_RO(HW_ICOLL_STAT, REGS_ICOLL_BASE, 0x30)
  33 +
  34 +HW_REGISTER_INDEXED(HW_ICOLL_PRIORITYn, REGS_ICOLL_BASE, 0x60, 0x10)
  35 +
  36 +#endif /* _INCLUDE_ASM_ARCH_REGS_CLKCTRL_H */
arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h
Diff comments   View file @ 34acb09
  1 +/*
  2 + * STMP pinmux register definitions
  3 + *
  4 + * Copyright (c) 2008 Freescale Semiconductor
  5 + *
  6 + * This program is free software; you can redistribute it and/or modify
  7 + * it under the terms of the GNU General Public License as published by
  8 + * the Free Software Foundation; either version 2 of the License, or
  9 + * (at your option) any later version.
  10 + *
  11 + * This program is distributed in the hope that it will be useful,
  12 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14 + * GNU General Public License for more details.
  15 + *
  16 + * You should have received a copy of the GNU General Public License
  17 + * along with this program; if not, write to the Free Software
  18 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19 + */
  20 +#ifndef _INCLUDE_ASM_ARCH_REGS_PINCTRL_H
  21 +#define _INCLUDE_ASM_ARCH_REGS_PINCTRL_H
  22 +
  23 +#include <mach/stmp3xxx_regs.h>
  24 +
  25 +#ifndef REGS_PINCTRL_BASE
  26 +#define REGS_PINCTRL_BASE (REGS_BASE + 0x00018000)
  27 +#endif /* REGS_PINCTRL_BASE */
  28 +
  29 +HW_REGISTER(HW_PINCTRL_CTRL, REGS_PINCTRL_BASE, 0)
  30 +
  31 +#define HW_PINCTRL_MUXSEL0_ADDR (REGS_PINCTRL_BASE + 0x100)
  32 +HW_REGISTER(HW_PINCTRL_MUXSEL0, REGS_PINCTRL_BASE, 0x100)
  33 +#define HW_PINCTRL_MUXSEL1_ADDR (REGS_PINCTRL_BASE + 0x110)
  34 +HW_REGISTER(HW_PINCTRL_MUXSEL1, REGS_PINCTRL_BASE, 0x110)
  35 +#define HW_PINCTRL_MUXSEL2_ADDR (REGS_PINCTRL_BASE + 0x120)
  36 +HW_REGISTER(HW_PINCTRL_MUXSEL2, REGS_PINCTRL_BASE, 0x120)
  37 +#define HW_PINCTRL_MUXSEL3_ADDR (REGS_PINCTRL_BASE + 0x130)
  38 +HW_REGISTER(HW_PINCTRL_MUXSEL3, REGS_PINCTRL_BASE, 0x130)
  39 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN28 0x03000000
  40 +#define HW_PINCTRL_MUXSEL4_ADDR (REGS_PINCTRL_BASE + 0x140)
  41 +HW_REGISTER(HW_PINCTRL_MUXSEL4, REGS_PINCTRL_BASE, 0x140)
  42 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN03 0x000000C0
  43 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN04 0x00000300
  44 +#define HW_PINCTRL_MUXSEL5_ADDR (REGS_PINCTRL_BASE + 0x150)
  45 +HW_REGISTER(HW_PINCTRL_MUXSEL5, REGS_PINCTRL_BASE, 0x150)
  46 +#define HW_PINCTRL_MUXSEL6_ADDR (REGS_PINCTRL_BASE + 0x160)
  47 +HW_REGISTER(HW_PINCTRL_MUXSEL6, REGS_PINCTRL_BASE, 0x160)
  48 +#define HW_PINCTRL_MUXSEL7_ADDR (REGS_PINCTRL_BASE + 0x170)
  49 +HW_REGISTER(HW_PINCTRL_MUXSEL7, REGS_PINCTRL_BASE, 0x170)
  50 +
  51 +HW_REGISTER(HW_PINCTRL_DRIVE0, REGS_PINCTRL_BASE, 0x200)
  52 +#define HW_PINCTRL_DRIVE0_ADDR (REGS_PINCTRL_BASE + 0x200)
  53 +HW_REGISTER(HW_PINCTRL_DRIVE1, REGS_PINCTRL_BASE, 0x210)
  54 +#define HW_PINCTRL_DRIVE1_ADDR (REGS_PINCTRL_BASE + 0x210)
  55 +HW_REGISTER(HW_PINCTRL_DRIVE2, REGS_PINCTRL_BASE, 0x220)
  56 +#define HW_PINCTRL_DRIVE2_ADDR (REGS_PINCTRL_BASE + 0x220)
  57 +HW_REGISTER(HW_PINCTRL_DRIVE3, REGS_PINCTRL_BASE, 0x230)
  58 +#define HW_PINCTRL_DRIVE3_ADDR (REGS_PINCTRL_BASE + 0x230)
  59 +HW_REGISTER(HW_PINCTRL_DRIVE4, REGS_PINCTRL_BASE, 0x240)
  60 +#define HW_PINCTRL_DRIVE4_ADDR (REGS_PINCTRL_BASE + 0x240)
  61 +HW_REGISTER(HW_PINCTRL_DRIVE5, REGS_PINCTRL_BASE, 0x250)
  62 +#define HW_PINCTRL_DRIVE5_ADDR (REGS_PINCTRL_BASE + 0x250)
  63 +HW_REGISTER(HW_PINCTRL_DRIVE6, REGS_PINCTRL_BASE, 0x260)
  64 +#define HW_PINCTRL_DRIVE6_ADDR (REGS_PINCTRL_BASE + 0x260)
  65 +HW_REGISTER(HW_PINCTRL_DRIVE7, REGS_PINCTRL_BASE, 0x270)
  66 +#define HW_PINCTRL_DRIVE7_ADDR (REGS_PINCTRL_BASE + 0x270)
  67 +HW_REGISTER(HW_PINCTRL_DRIVE8, REGS_PINCTRL_BASE, 0x280)
  68 +#define HW_PINCTRL_DRIVE8_ADDR (REGS_PINCTRL_BASE + 0x280)
  69 +HW_REGISTER(HW_PINCTRL_DRIVE9, REGS_PINCTRL_BASE, 0x290)
  70 +#define HW_PINCTRL_DRIVE9_ADDR (REGS_PINCTRL_BASE + 0x290)
  71 +HW_REGISTER(HW_PINCTRL_DRIVE10, REGS_PINCTRL_BASE, 0x2a0)
  72 +#define HW_PINCTRL_DRIVE10_ADDR (REGS_PINCTRL_BASE + 0x2a0)
  73 +HW_REGISTER(HW_PINCTRL_DRIVE11, REGS_PINCTRL_BASE, 0x2b0)
  74 +#define HW_PINCTRL_DRIVE11_ADDR (REGS_PINCTRL_BASE + 0x2b0)
  75 +HW_REGISTER(HW_PINCTRL_DRIVE12, REGS_PINCTRL_BASE, 0x2c0)
  76 +#define HW_PINCTRL_DRIVE12_ADDR (REGS_PINCTRL_BASE + 0x2c0)
  77 +HW_REGISTER(HW_PINCTRL_DRIVE13, REGS_PINCTRL_BASE, 0x2d0)
  78 +#define HW_PINCTRL_DRIVE13_ADDR (REGS_PINCTRL_BASE + 0x2d0)
  79 +HW_REGISTER(HW_PINCTRL_DRIVE14, REGS_PINCTRL_BASE, 0x2e0)
  80 +#define HW_PINCTRL_DRIVE14_ADDR (REGS_PINCTRL_BASE + 0x2e0)
  81 +
  82 +
  83 +HW_REGISTER(HW_PINCTRL_PULL0, REGS_PINCTRL_BASE, 0x300)
  84 +#define HW_PINCTRL_PULL0_ADDR (REGS_PINCTRL_BASE + 0x300)
  85 +#define BM_PINCTRL_PULL0_BANK0_PIN01 0x00000002
  86 +#define BM_PINCTRL_PULL0_BANK0_PIN02 0x00000004
  87 +#define BM_PINCTRL_PULL0_BANK0_PIN03 0x00000008
  88 +#define BM_PINCTRL_PULL0_BANK0_PIN04 0x00000010
  89 +#define BM_PINCTRL_PULL0_BANK0_PIN20 0x00100000
  90 +HW_REGISTER(HW_PINCTRL_PULL1, REGS_PINCTRL_BASE, 0x310)
  91 +#define HW_PINCTRL_PULL1_ADDR (REGS_PINCTRL_BASE + 0x310)
  92 +#define BM_PINCTRL_PULL1_BANK1_PIN22 0x00400000
  93 +#define BM_PINCTRL_PULL1_BANK1_PIN24 0x01000000
  94 +#define BM_PINCTRL_PULL1_BANK1_PIN25 0x02000000
  95 +#define BM_PINCTRL_PULL1_BANK1_PIN26 0x04000000
  96 +#define BM_PINCTRL_PULL1_BANK1_PIN27 0x08000000
  97 +HW_REGISTER(HW_PINCTRL_PULL2, REGS_PINCTRL_BASE, 0x320)
  98 +#define HW_PINCTRL_PULL2_ADDR (REGS_PINCTRL_BASE + 0x320)
  99 +HW_REGISTER(HW_PINCTRL_PULL3, REGS_PINCTRL_BASE, 0x330)
  100 +#define HW_PINCTRL_PULL3_ADDR (REGS_PINCTRL_BASE + 0x330)
  101 +
  102 +#define HW_PINCTRL_DOUT0_ADDR (REGS_PINCTRL_BASE + 0x400)
  103 +HW_REGISTER(HW_PINCTRL_DOUT0, REGS_PINCTRL_BASE, 0x400)
  104 +#define HW_PINCTRL_DOUT1_ADDR (REGS_PINCTRL_BASE + 0x410)
  105 +HW_REGISTER(HW_PINCTRL_DOUT1, REGS_PINCTRL_BASE, 0x410)
  106 +#define HW_PINCTRL_DOUT2_ADDR (REGS_PINCTRL_BASE + 0x420)
  107 +HW_REGISTER(HW_PINCTRL_DOUT2, REGS_PINCTRL_BASE, 0x420)
  108 +
  109 +#define HW_PINCTRL_DIN0_ADDR (REGS_PINCTRL_BASE + 0x500)
  110 +HW_REGISTER_RO(HW_PINCTRL_DIN0, REGS_PINCTRL_BASE, 0x500)
  111 +#define HW_PINCTRL_DIN1_ADDR (REGS_PINCTRL_BASE + 0x510)
  112 +HW_REGISTER_RO(HW_PINCTRL_DIN1, REGS_PINCTRL_BASE, 0x510)
  113 +#define HW_PINCTRL_DIN2_ADDR (REGS_PINCTRL_BASE + 0x520)
  114 +HW_REGISTER_RO(HW_PINCTRL_DIN2, REGS_PINCTRL_BASE, 0x520)
  115 +
  116 +#define HW_PINCTRL_DOE0_ADDR (REGS_PINCTRL_BASE + 0x600)
  117 +HW_REGISTER(HW_PINCTRL_DOE0, REGS_PINCTRL_BASE, 0x600)
  118 +#define HW_PINCTRL_DOE1_ADDR (REGS_PINCTRL_BASE + 0x610)
  119 +HW_REGISTER(HW_PINCTRL_DOE1, REGS_PINCTRL_BASE, 0x610)
  120 +#define HW_PINCTRL_DOE2_ADDR (REGS_PINCTRL_BASE + 0x620)
  121 +HW_REGISTER(HW_PINCTRL_DOE2, REGS_PINCTRL_BASE, 0x620)
  122 +
  123 +HW_REGISTER(HW_PINCTRL_PIN2IRQ0, REGS_PINCTRL_BASE, 0x700)
  124 +#define HW_PINCTRL_PIN2IRQ0_ADDR (REGS_PINCTRL_BASE + 0x700)
  125 +HW_REGISTER(HW_PINCTRL_PIN2IRQ1, REGS_PINCTRL_BASE, 0x710)
  126 +#define HW_PINCTRL_PIN2IRQ1_ADDR (REGS_PINCTRL_BASE + 0x710)
  127 +HW_REGISTER(HW_PINCTRL_PIN2IRQ2, REGS_PINCTRL_BASE, 0x720)
  128 +#define HW_PINCTRL_PIN2IRQ2_ADDR (REGS_PINCTRL_BASE + 0x720)
  129 +
  130 +HW_REGISTER(HW_PINCTRL_IRQEN0, REGS_PINCTRL_BASE, 0x800)
  131 +#define HW_PINCTRL_IRQEN0_ADDR (REGS_PINCTRL_BASE + 0x800)
  132 +HW_REGISTER(HW_PINCTRL_IRQEN1, REGS_PINCTRL_BASE, 0x810)
  133 +#define HW_PINCTRL_IRQEN1_ADDR (REGS_PINCTRL_BASE + 0x810)
  134 +HW_REGISTER(HW_PINCTRL_IRQEN2, REGS_PINCTRL_BASE, 0x820)
  135 +#define HW_PINCTRL_IRQEN2_ADDR (REGS_PINCTRL_BASE + 0x820)
  136 +
  137 +HW_REGISTER(HW_PINCTRL_IRQLEVEL0, REGS_PINCTRL_BASE, 0x900)
  138 +#define HW_PINCTRL_IRQLEVEL0_ADDR (REGS_PINCTRL_BASE + 0x900)
  139 +HW_REGISTER(HW_PINCTRL_IRQLEVEL1, REGS_PINCTRL_BASE, 0x910)
  140 +#define HW_PINCTRL_IRQLEVEL1_ADDR (REGS_PINCTRL_BASE + 0x910)
  141 +HW_REGISTER(HW_PINCTRL_IRQLEVEL2, REGS_PINCTRL_BASE, 0x920)
  142 +#define HW_PINCTRL_IRQLEVEL2_ADDR (REGS_PINCTRL_BASE + 0x920)
  143 +
  144 +HW_REGISTER(HW_PINCTRL_IRQPOL0, REGS_PINCTRL_BASE, 0xA00)
  145 +#define HW_PINCTRL_IRQPOL0_ADDR (REGS_PINCTRL_BASE + 0xa00)
  146 +HW_REGISTER(HW_PINCTRL_IRQPOL1, REGS_PINCTRL_BASE, 0xA10)
  147 +#define HW_PINCTRL_IRQPOL1_ADDR (REGS_PINCTRL_BASE + 0xa10)
  148 +HW_REGISTER(HW_PINCTRL_IRQPOL2, REGS_PINCTRL_BASE, 0xA20)
  149 +#define HW_PINCTRL_IRQPOL2_ADDR (REGS_PINCTRL_BASE + 0xa20)
  150 +
  151 +HW_REGISTER(HW_PINCTRL_IRQSTAT0, REGS_PINCTRL_BASE, 0xB00)
  152 +#define HW_PINCTRL_IRQSTAT0_ADDR (REGS_PINCTRL_BASE + 0xb00)
  153 +HW_REGISTER(HW_PINCTRL_IRQSTAT1, REGS_PINCTRL_BASE, 0xB10)
  154 +#define HW_PINCTRL_IRQSTAT1_ADDR (REGS_PINCTRL_BASE + 0xb10)
  155 +HW_REGISTER(HW_PINCTRL_IRQSTAT2, REGS_PINCTRL_BASE, 0xB20)
  156 +#define HW_PINCTRL_IRQSTAT2_ADDR (REGS_PINCTRL_BASE + 0xb20)
  157 +
  158 +#endif /* _INCLUDE_ASM_ARCH_REGS_PINCTRL_H */
arch/arm/mach-stmp37xx/include/mach/regs-power.h
Diff comments   View file @ 34acb09
  1 +/*
  2 + * STMP POWER Register Definitions
  3 + *
  4 + * Copyright (c) 2008 Freescale Semiconductor
  5 + *
  6 + * This program is free software; you can redistribute it and/or modify
  7 + * it under the terms of the GNU General Public License as published by
  8 + * the Free Software Foundation; either version 2 of the License, or
  9 + * (at your option) any later version.
  10 + *
  11 + * This program is distributed in the hope that it will be useful,
  12 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14 + * GNU General Public License for more details.
  15 + *
  16 + * You should have received a copy of the GNU General Public License
  17 + * along with this program; if not, write to the Free Software
  18 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19 + */
  20 +
  21 +#ifndef __ARCH_ARM___POWER_H
  22 +#define __ARCH_ARM___POWER_H 1
  23 +
  24 +#include <mach/stmp3xxx_regs.h>
  25 +
  26 +#define REGS_POWER_BASE (void __iomem *)(REGS_BASE + 0x44000)
  27 +#define REGS_POWER_BASE_PHYS (0x80044000)
  28 +#define REGS_POWER_SIZE 0x00002000
  29 +HW_REGISTER(HW_POWER_MINPWR, REGS_POWER_BASE, 0x00000020)
  30 +HW_REGISTER(HW_POWER_CHARGE, REGS_POWER_BASE, 0x00000030)
  31 +#endif /* __ARCH_ARM___POWER_H */
arch/arm/mach-stmp37xx/include/mach/regs-timrot.h
Diff comments   View file @ 34acb09
  1 +/*
  2 + * include/asm-arm/arch-stmp3xxx/regstimer.h
  3 + *
  4 + * Copyright (c) 2008 SigmaTel Inc
  5 + * Copyright (c) 2008 Embedded Alley Solutions, Inc
  6 + *
  7 + * This program is free software; you can redistribute it and/or modify
  8 + * it under the terms of the GNU General Public License as published by
  9 + * the Free Software Foundation; either version 2 of the License, or
  10 + * (at your option) any later version.
  11 + *
  12 + * This program is distributed in the hope that it will be useful,
  13 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 + * GNU General Public License for more details.
  16 + *
  17 + * You should have received a copy of the GNU General Public License
  18 + * along with this program; if not, write to the Free Software
  19 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20 + */
  21 +#ifndef __ARCH_ARM_REGS_TIMROT_H
  22 +#define __ARCH_ARM_REGS_TIMROT_H
  23 +
  24 +#include <mach/stmp3xxx_regs.h>
  25 +
  26 +#define REGS_TIMROT_BASE (REGS_BASE + 0x00068000)
  27 +
  28 +HW_REGISTER(HW_TIMROT_ROTCTRL, REGS_TIMROT_BASE, 0)
  29 +#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000
  30 +#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000
  31 +
  32 +HW_REGISTER_INDEXED(HW_TIMROT_TIMCTRLn, REGS_TIMROT_BASE, 0x20, 0x20)
  33 +#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F
  34 +#define BF_TIMROT_TIMCTRLn_SELECT(v) (((v) << 0) & BM_TIMROT_TIMCTRLn_SELECT)
  35 +#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030
  36 +#define BF_TIMROT_TIMCTRLn_PRESCALE(v) \
  37 + (((v) << 4) & BM_TIMROT_TIMCTRLn_PRESCALE)
  38 +#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040
  39 +#define BF_TIMROT_TIMCTRLn_RELOAD(v) (((v) << 6) & BM_TIMROT_TIMCTRLn_RELOAD)
  40 +#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080
  41 +#define BF_TIMROT_TIMCTRLn_UPDATE(v) (((v) << 7) & BM_TIMROT_TIMCTRLn_UPDATE)
  42 +#define BM_TIMROT_TIMCTRLn_POLARITY 0x00000100
  43 +#define BF_TIMROT_TIMCTRLn_POLARITY(v) \
  44 + (((v) << 8) & BM_TIMROT_TIMCTRLn_POLARITY)
  45 +#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000
  46 +#define BF_TIMROT_TIMCTRLn_IRQ_EN(v) \
  47 + (((v) << 14) & BM_TIMROT_TIMCTRLn_IRQ_EN)
  48 +#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000
  49 +#define BF_TIMROT_TIMCTRLn_IRQ(v) (((v) << 15) & BM_TIMROT_TIMCTRLn_IRQ)
  50 +HW_REGISTER_0_INDEXED(HW_TIMROT_TIMCOUNTn, REGS_TIMROT_BASE, 0x30, 0x20)
  51 +
  52 +#endif /* __ARCH_ARM_REGSTIMER_H */