Commit 3d9cd95f90b2987ef95182a4340a9150e06c4253

Authored by Marc Zyngier
1 parent 6134993789

ARM: gic-v3: Work around definition of gic_write_bpr1

A new accessor for gic_write_bpr1 is added to arch_gicv3.h in 4.9,
whilst the CP15 accessors are redifined in a separate branch.
This leads to a horrible clash, where the new accessor ends up with
a crap "asm volatile" definition.

Work around this by carrying our own definition of gic_write_bpr1,
creating a small conflict which will be obvious to resolve.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

Showing 1 changed file with 9 additions and 0 deletions Side-by-side Diff

arch/arm/include/asm/arch_gicv3.h
... ... @@ -216,6 +216,15 @@
216 216 isb();
217 217 }
218 218  
  219 +static inline void gic_write_bpr1(u32 val)
  220 +{
  221 +#if defined(__write_sysreg) && defined(ICC_BPR1)
  222 + write_sysreg(val, ICC_BPR1);
  223 +#else
  224 + asm volatile("mcr " __stringify(ICC_BPR1) : : "r" (val));
  225 +#endif
  226 +}
  227 +
219 228 /*
220 229 * Even in 32bit systems that use LPAE, there is no guarantee that the I/O
221 230 * interface provides true 64bit atomic accesses, so using strd/ldrd doesn't