Eric Lee / smarc-fsl-linux-kernel

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Commit 43608372b84d7f0142ee8b2f56277a60f0f0a2a5

Authored by Eran Ben Elisha
Committed by Greg Kroah-Hartman
1 parent 8901896f69

net/mlx5: Verify Hardware supports requested ptp function on a given pin 

[ Upstream commit 071995c877a8646209d55ff8edddd2b054e7424c ]

Fix a bug where driver did not verify Hardware pin capabilities for
PTP functions.

Fixes: ee7f12205abc ("net/mlx5e: Implement 1PPS support")
Signed-off-by: Eran Ben Elisha <eranbe@mellanox.com>
Reviewed-by: Ariel Levkovich <lariel@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

Showing 1 changed file with 22 additions and 1 deletions Side-by-side Diff

drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
Diff comments   View file @ 4360837
... ... @@ -388,10 +388,31 @@
388 388 return 0;
389 389 }
390 390  
  391 +enum {
  392 + MLX5_MTPPS_REG_CAP_PIN_X_MODE_SUPPORT_PPS_IN = BIT(0),
  393 + MLX5_MTPPS_REG_CAP_PIN_X_MODE_SUPPORT_PPS_OUT = BIT(1),
  394 +};
  395 +
391 396 static int mlx5_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,
392 397 enum ptp_pin_function func, unsigned int chan)
393 398 {
394   - return (func == PTP_PF_PHYSYNC) ? -EOPNOTSUPP : 0;
  399 + struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock,
  400 + ptp_info);
  401 +
  402 + switch (func) {
  403 + case PTP_PF_NONE:
  404 + return 0;
  405 + case PTP_PF_EXTTS:
  406 + return !(clock->pps_info.pin_caps[pin] &
  407 + MLX5_MTPPS_REG_CAP_PIN_X_MODE_SUPPORT_PPS_IN);
  408 + case PTP_PF_PEROUT:
  409 + return !(clock->pps_info.pin_caps[pin] &
  410 + MLX5_MTPPS_REG_CAP_PIN_X_MODE_SUPPORT_PPS_OUT);
  411 + default:
  412 + return -EOPNOTSUPP;
  413 + }
  414 +
  415 + return -EOPNOTSUPP;
395 416 }
396 417  
397 418 static const struct ptp_clock_info mlx5_ptp_clock_info = {