Eric Lee / smarc-fsl-linux-kernel

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Commit 43a1a3ed6bf5a1b9ae197b4f5f20033baf19db61

Authored by Ira Snyder
Committed by Dan Williams
1 parent be30b226f2

fsldma: do not clear bandwidth control bits on the 83xx controller 

The 83xx controller does not support the external pause feature. The bit
in the mode register that controls external pause on the 85xx controller
happens to be part of the bandwidth control settings for the 83xx
controller.

This patch fixes the driver so that it only clears the external pause bit
if the hardware is the 85xx controller. When driving the 83xx controller,
the bit is left untouched. This follows the existing convention that mode
registers settings are not touched unless necessary.

Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>

Showing 1 changed file with 2 additions and 1 deletions Side-by-side Diff

drivers/dma/fsldma.c
Diff comments   View file @ 43a1a3e
... ... @@ -147,10 +147,11 @@
147 147 if (fsl_chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
148 148 DMA_OUT(fsl_chan, &fsl_chan->reg_base->bcr, 0, 32);
149 149 mr_set |= FSL_DMA_MR_EMP_EN;
150   - } else
  150 + } else if ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
151 151 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
152 152 DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32)
153 153 & ~FSL_DMA_MR_EMP_EN, 32);
  154 + }
154 155  
155 156 if (fsl_chan->feature & FSL_DMA_CHAN_START_EXT)
156 157 mr_set |= FSL_DMA_MR_EMS_EN;