bcma: add constants for chip ids

The chip IDs are used all over bcma and no constants where defined. This patch adds the constants and makes bcma use them. Acked-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>

bcma: add constants for chip ids
The chip IDs are used all over bcma and no constants where defined. This patch adds the constants and makes bcma use them. Acked-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Hauke Mehrtens · John W. Linville
1 parent 00eeedcf08
Showing 5 changed files with 90 additions and 55 deletions Side-by-side Diff
drivers/bcma/driver_chipcommon_pmu.c
drivers/bcma/driver_mips.c
drivers/bcma/driver_pci_host.c
drivers/bcma/sprom.c
include/linux/bcma/bcma.h
@@ -59,10 +59,10 @@
 	struct bcma_bus *bus = cc->core->bus;
  
 	switch (bus->chipinfo.id) {
-	case 0x4313:
-	case 0x4331:
-	case 43224:
-	case 43225:
+	case BCMA_CHIP_ID_BCM4313:
+	case BCMA_CHIP_ID_BCM4331:
+	case BCMA_CHIP_ID_BCM43224:
+	case BCMA_CHIP_ID_BCM43225:
 		break;
 	default:
 		pr_err("PLL init unknown for device 0x%04X\n",
  
@@ -76,13 +76,13 @@
 	u32 min_msk = 0, max_msk = 0;
  
 	switch (bus->chipinfo.id) {
-	case 0x4313:
+	case BCMA_CHIP_ID_BCM4313:
 		min_msk = 0x200D;
 		max_msk = 0xFFFF;
 		break;
-	case 0x4331:
-	case 43224:
-	case 43225:
+	case BCMA_CHIP_ID_BCM4331:
+	case BCMA_CHIP_ID_BCM43224:
+	case BCMA_CHIP_ID_BCM43225:
 		break;
 	default:
 		pr_err("PMU resource config unknown for device 0x%04X\n",
@@ -101,10 +101,10 @@
 	struct bcma_bus *bus = cc->core->bus;
  
 	switch (bus->chipinfo.id) {
-	case 0x4313:
-	case 0x4331:
-	case 43224:
-	case 43225:
+	case BCMA_CHIP_ID_BCM4313:
+	case BCMA_CHIP_ID_BCM4331:
+	case BCMA_CHIP_ID_BCM43224:
+	case BCMA_CHIP_ID_BCM43225:
 		break;
 	default:
 		pr_err("PMU switch/regulators init unknown for device "
  
  
@@ -138,15 +138,15 @@
 	struct bcma_bus *bus = cc->core->bus;
  
 	switch (bus->chipinfo.id) {
-	case 0x4313:
+	case BCMA_CHIP_ID_BCM4313:
 		bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x7);
 		break;
-	case 0x4331:
-	case 43431:
+	case BCMA_CHIP_ID_BCM4331:
+	case BCMA_CHIP_ID_BCM43431:
 		/* Ext PA lines must be enabled for tx on BCM4331 */
 		bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true);
 		break;
-	case 43224:
+	case BCMA_CHIP_ID_BCM43224:
 		if (bus->chipinfo.rev == 0) {
 			pr_err("Workarounds for 43224 rev 0 not fully "
 				"implemented\n");
@@ -155,7 +155,7 @@
 			bcma_chipco_chipctl_maskset(cc, 0, ~0, 0xF0);
 		}
 		break;
-	case 43225:
+	case BCMA_CHIP_ID_BCM43225:
 		break;
 	default:
 		pr_err("Workarounds unknown for device 0x%04X\n",
  
@@ -194,17 +194,17 @@
 	struct bcma_bus *bus = cc->core->bus;
  
 	switch (bus->chipinfo.id) {
-	case 0x4716:
-	case 0x4748:
-	case 47162:
-	case 0x4313:
-	case 0x5357:
-	case 0x4749:
-	case 53572:
+	case BCMA_CHIP_ID_BCM4716:
+	case BCMA_CHIP_ID_BCM4748:
+	case BCMA_CHIP_ID_BCM47162:
+	case BCMA_CHIP_ID_BCM4313:
+	case BCMA_CHIP_ID_BCM5357:
+	case BCMA_CHIP_ID_BCM4749:
+	case BCMA_CHIP_ID_BCM53572:
 		/* always 20Mhz */
 		return 20000 * 1000;
-	case 0x5356:
-	case 0x5300:
+	case BCMA_CHIP_ID_BCM5356:
+	case BCMA_CHIP_ID_BCM4706:
 		/* always 25Mhz */
 		return 25000 * 1000;
 	default:
@@ -227,7 +227,8 @@
  
 	BUG_ON(!m || m > 4);
  
-	if (bus->chipinfo.id == 0x5357 || bus->chipinfo.id == 0x4749) {
+	if (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
+	    bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) {
 		/* Detect failure in clock setting */
 		tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
 		if (tmp & 0x40000)
  
  
  
  
@@ -259,22 +260,22 @@
 	struct bcma_bus *bus = cc->core->bus;
  
 	switch (bus->chipinfo.id) {
-	case 0x4716:
-	case 0x4748:
-	case 47162:
+	case BCMA_CHIP_ID_BCM4716:
+	case BCMA_CHIP_ID_BCM4748:
+	case BCMA_CHIP_ID_BCM47162:
 		return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
 				      BCMA_CC_PMU5_MAINPLL_SSB);
-	case 0x5356:
+	case BCMA_CHIP_ID_BCM5356:
 		return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
 				      BCMA_CC_PMU5_MAINPLL_SSB);
-	case 0x5357:
-	case 0x4749:
+	case BCMA_CHIP_ID_BCM5357:
+	case BCMA_CHIP_ID_BCM4749:
 		return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
 				      BCMA_CC_PMU5_MAINPLL_SSB);
-	case 0x5300:
+	case BCMA_CHIP_ID_BCM4706:
 		return bcma_pmu_clock(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
 				      BCMA_CC_PMU5_MAINPLL_SSB);
-	case 53572:
+	case BCMA_CHIP_ID_BCM53572:
 		return 75000000;
 	default:
 		pr_warn("No backplane clock specified for %04X device, "
  
  
@@ -289,17 +290,17 @@
 {
 	struct bcma_bus *bus = cc->core->bus;
  
-	if (bus->chipinfo.id == 53572)
+	if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
 		return 300000000;
  
 	if (cc->pmu.rev >= 5) {
 		u32 pll;
 		switch (bus->chipinfo.id) {
-		case 0x5356:
+		case BCMA_CHIP_ID_BCM5356:
 			pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
 			break;
-		case 0x5357:
-		case 0x4749:
+		case BCMA_CHIP_ID_BCM5357:
+		case BCMA_CHIP_ID_BCM4749:
 			pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
 			break;
 		default:
@@ -307,7 +308,7 @@
 			break;
 		}
  
-		/* TODO: if (bus->chipinfo.id == 0x5300)
+		/* TODO: if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
 		  return si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_CPU); */
 		return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
 	}
@@ -22,15 +22,15 @@
 /* The 47162a0 hangs when reading MIPS DMP registers registers */
 static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
 {
-	return dev->bus->chipinfo.id == 47162 && dev->bus->chipinfo.rev == 0 &&
-	       dev->id.id == BCMA_CORE_MIPS_74K;
+	return dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM47162 &&
+	       dev->bus->chipinfo.rev == 0 && dev->id.id == BCMA_CORE_MIPS_74K;
 }
  
 /* The 5357b0 hangs when reading USB20H DMP registers */
 static inline bool bcma_core_mips_bcm5357b0_quirk(struct bcma_device *dev)
 {
-	return (dev->bus->chipinfo.id == 0x5357 ||
-		dev->bus->chipinfo.id == 0x4749) &&
+	return (dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
+		dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) &&
 	       dev->bus->chipinfo.pkg == 11 &&
 	       dev->id.id == BCMA_CORE_USB20_HOST;
 }
@@ -215,7 +215,8 @@
 	} else {
 		writel(val, mmio);
  
-		if (chipid == 0x4716 || chipid == 0x4748)
+		if (chipid == BCMA_CHIP_ID_BCM4716 ||
+		    chipid == BCMA_CHIP_ID_BCM4748)
 			readl(mmio);
 	}
  
  
@@ -434,13 +435,14 @@
 	 * as mips can't generate 64-bit address on the
 	 * backplane.
 	 */
-	if (bus->chipinfo.id == 0x4716 || bus->chipinfo.id == 0x4748) {
+	if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4716 ||
+	    bus->chipinfo.id == BCMA_CHIP_ID_BCM4748) {
 		pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
 		pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
 					    BCMA_SOC_PCI_MEM_SZ - 1;
 		pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
 				BCMA_CORE_PCI_SBTOPCI_MEM | BCMA_SOC_PCI_MEM);
-	} else if (bus->chipinfo.id == 0x5300) {
+	} else if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
 		tmp = BCMA_CORE_PCI_SBTOPCI_MEM;
 		tmp |= BCMA_CORE_PCI_SBTOPCI_PREF;
 		tmp |= BCMA_CORE_PCI_SBTOPCI_BURST;
@@ -468,11 +468,11 @@
 	/* older chipcommon revisions use chip status register */
 	chip_status = bcma_read32(bus->drv_cc.core, BCMA_CC_CHIPSTAT);
 	switch (bus->chipinfo.id) {
-	case 0x4313:
+	case BCMA_CHIP_ID_BCM4313:
 		present_mask = BCMA_CC_CHIPST_4313_SPROM_PRESENT;
 		break;
  
-	case 0x4331:
+	case BCMA_CHIP_ID_BCM4331:
 		present_mask = BCMA_CC_CHIPST_4331_SPROM_PRESENT;
 		break;
  
  
  
@@ -494,16 +494,16 @@
  
 	chip_status = bcma_read32(bus->drv_cc.core, BCMA_CC_CHIPSTAT);
 	switch (bus->chipinfo.id) {
-	case 0x4313:
+	case BCMA_CHIP_ID_BCM4313:
 		present = chip_status & BCMA_CC_CHIPST_4313_OTP_PRESENT;
 		break;
  
-	case 0x4331:
+	case BCMA_CHIP_ID_BCM4331:
 		present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
 		break;
  
-	case 43224:
-	case 43225:
+	case BCMA_CHIP_ID_BCM43224:
+	case BCMA_CHIP_ID_BCM43225:
 		/* for these chips OTP is always available */
 		present = true;
 		break;
  
@@ -579,13 +579,15 @@
 	if (!sprom)
 		return -ENOMEM;
  
-	if (bus->chipinfo.id == 0x4331 || bus->chipinfo.id == 43431)
+	if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
+	    bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
 		bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
  
 	pr_debug("SPROM offset 0x%x\n", offset);
 	bcma_sprom_read(bus, offset, sprom);
  
-	if (bus->chipinfo.id == 0x4331 || bus->chipinfo.id == 43431)
+	if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
+	    bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
 		bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
  
 	err = bcma_sprom_valid(sprom);
@@ -137,6 +137,36 @@
  
 #define BCMA_MAX_NR_CORES		16
  
+/* Chip IDs of PCIe devices */
+#define BCMA_CHIP_ID_BCM4313	0x4313
+#define BCMA_CHIP_ID_BCM43224	43224
+#define  BCMA_PKG_ID_BCM43224_FAB_CSM	0x8
+#define  BCMA_PKG_ID_BCM43224_FAB_SMIC	0xa
+#define BCMA_CHIP_ID_BCM43225	43225
+#define BCMA_CHIP_ID_BCM43227	43227
+#define BCMA_CHIP_ID_BCM43228	43228
+#define BCMA_CHIP_ID_BCM43421	43421
+#define BCMA_CHIP_ID_BCM43428	43428
+#define BCMA_CHIP_ID_BCM43431	43431
+#define BCMA_CHIP_ID_BCM43460	43460
+#define BCMA_CHIP_ID_BCM4331	0x4331
+#define BCMA_CHIP_ID_BCM6362	0x6362
+#define BCMA_CHIP_ID_BCM4360	0x4360
+#define BCMA_CHIP_ID_BCM4352	0x4352
+
+/* Chip IDs of SoCs */
+#define BCMA_CHIP_ID_BCM4706	0x5300
+#define BCMA_CHIP_ID_BCM4716	0x4716
+#define  BCMA_PKG_ID_BCM4716	8
+#define  BCMA_PKG_ID_BCM4717	9
+#define  BCMA_PKG_ID_BCM4718	10
+#define BCMA_CHIP_ID_BCM47162	47162
+#define BCMA_CHIP_ID_BCM4748	0x4748
+#define BCMA_CHIP_ID_BCM4749	0x4749
+#define BCMA_CHIP_ID_BCM5356	0x5356
+#define BCMA_CHIP_ID_BCM5357	0x5357
+#define BCMA_CHIP_ID_BCM53572	53572
+
 struct bcma_device {
 	struct bcma_bus *bus;
 	struct bcma_device_id id;
...	...	@@ -59,10 +59,10 @@
59	59	struct bcma_bus *bus = cc->core->bus;
60	60
61	61	switch (bus->chipinfo.id) {
62		- case 0x4313:
63		- case 0x4331:
64		- case 43224:
65		- case 43225:
	62	+ case BCMA_CHIP_ID_BCM4313:
	63	+ case BCMA_CHIP_ID_BCM4331:
	64	+ case BCMA_CHIP_ID_BCM43224:
	65	+ case BCMA_CHIP_ID_BCM43225:
66	66	break;
67	67	default:
68	68	pr_err("PLL init unknown for device 0x%04X\n",
69	69
...	...	@@ -76,13 +76,13 @@
76	76	u32 min_msk = 0, max_msk = 0;
77	77
78	78	switch (bus->chipinfo.id) {
79		- case 0x4313:
	79	+ case BCMA_CHIP_ID_BCM4313:
80	80	min_msk = 0x200D;
81	81	max_msk = 0xFFFF;
82	82	break;
83		- case 0x4331:
84		- case 43224:
85		- case 43225:
	83	+ case BCMA_CHIP_ID_BCM4331:
	84	+ case BCMA_CHIP_ID_BCM43224:
	85	+ case BCMA_CHIP_ID_BCM43225:
86	86	break;
87	87	default:
88	88	pr_err("PMU resource config unknown for device 0x%04X\n",
...	...	@@ -101,10 +101,10 @@
101	101	struct bcma_bus *bus = cc->core->bus;
102	102
103	103	switch (bus->chipinfo.id) {
104		- case 0x4313:
105		- case 0x4331:
106		- case 43224:
107		- case 43225:
	104	+ case BCMA_CHIP_ID_BCM4313:
	105	+ case BCMA_CHIP_ID_BCM4331:
	106	+ case BCMA_CHIP_ID_BCM43224:
	107	+ case BCMA_CHIP_ID_BCM43225:
108	108	break;
109	109	default:
110	110	pr_err("PMU switch/regulators init unknown for device "
111	111
112	112
...	...	@@ -138,15 +138,15 @@
138	138	struct bcma_bus *bus = cc->core->bus;
139	139
140	140	switch (bus->chipinfo.id) {
141		- case 0x4313:
	141	+ case BCMA_CHIP_ID_BCM4313:
142	142	bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x7);
143	143	break;
144		- case 0x4331:
145		- case 43431:
	144	+ case BCMA_CHIP_ID_BCM4331:
	145	+ case BCMA_CHIP_ID_BCM43431:
146	146	/* Ext PA lines must be enabled for tx on BCM4331 */
147	147	bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true);
148	148	break;
149		- case 43224:
	149	+ case BCMA_CHIP_ID_BCM43224:
150	150	if (bus->chipinfo.rev == 0) {
151	151	pr_err("Workarounds for 43224 rev 0 not fully "
152	152	"implemented\n");
...	...	@@ -155,7 +155,7 @@
155	155	bcma_chipco_chipctl_maskset(cc, 0, ~0, 0xF0);
156	156	}
157	157	break;
158		- case 43225:
	158	+ case BCMA_CHIP_ID_BCM43225:
159	159	break;
160	160	default:
161	161	pr_err("Workarounds unknown for device 0x%04X\n",
162	162
...	...	@@ -194,17 +194,17 @@
194	194	struct bcma_bus *bus = cc->core->bus;
195	195
196	196	switch (bus->chipinfo.id) {
197		- case 0x4716:
198		- case 0x4748:
199		- case 47162:
200		- case 0x4313:
201		- case 0x5357:
202		- case 0x4749:
203		- case 53572:
	197	+ case BCMA_CHIP_ID_BCM4716:
	198	+ case BCMA_CHIP_ID_BCM4748:
	199	+ case BCMA_CHIP_ID_BCM47162:
	200	+ case BCMA_CHIP_ID_BCM4313:
	201	+ case BCMA_CHIP_ID_BCM5357:
	202	+ case BCMA_CHIP_ID_BCM4749:
	203	+ case BCMA_CHIP_ID_BCM53572:
204	204	/* always 20Mhz */
205	205	return 20000 * 1000;
206		- case 0x5356:
207		- case 0x5300:
	206	+ case BCMA_CHIP_ID_BCM5356:
	207	+ case BCMA_CHIP_ID_BCM4706:
208	208	/* always 25Mhz */
209	209	return 25000 * 1000;
210	210	default:
...	...	@@ -227,7 +227,8 @@
227	227
228	228	BUG_ON(!m \|\| m > 4);
229	229
230		- if (bus->chipinfo.id == 0x5357 \|\| bus->chipinfo.id == 0x4749) {
	230	+ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 \|\|
	231	+ bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) {
231	232	/* Detect failure in clock setting */
232	233	tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
233	234	if (tmp & 0x40000)
234	235
235	236
236	237
237	238
...	...	@@ -259,22 +260,22 @@
259	260	struct bcma_bus *bus = cc->core->bus;
260	261
261	262	switch (bus->chipinfo.id) {
262		- case 0x4716:
263		- case 0x4748:
264		- case 47162:
	263	+ case BCMA_CHIP_ID_BCM4716:
	264	+ case BCMA_CHIP_ID_BCM4748:
	265	+ case BCMA_CHIP_ID_BCM47162:
265	266	return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
266	267	BCMA_CC_PMU5_MAINPLL_SSB);
267		- case 0x5356:
	268	+ case BCMA_CHIP_ID_BCM5356:
268	269	return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
269	270	BCMA_CC_PMU5_MAINPLL_SSB);
270		- case 0x5357:
271		- case 0x4749:
	271	+ case BCMA_CHIP_ID_BCM5357:
	272	+ case BCMA_CHIP_ID_BCM4749:
272	273	return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
273	274	BCMA_CC_PMU5_MAINPLL_SSB);
274		- case 0x5300:
	275	+ case BCMA_CHIP_ID_BCM4706:
275	276	return bcma_pmu_clock(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
276	277	BCMA_CC_PMU5_MAINPLL_SSB);
277		- case 53572:
	278	+ case BCMA_CHIP_ID_BCM53572:
278	279	return 75000000;
279	280	default:
280	281	pr_warn("No backplane clock specified for %04X device, "
281	282
282	283
...	...	@@ -289,17 +290,17 @@
289	290	{
290	291	struct bcma_bus *bus = cc->core->bus;
291	292
292		- if (bus->chipinfo.id == 53572)
	293	+ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
293	294	return 300000000;
294	295
295	296	if (cc->pmu.rev >= 5) {
296	297	u32 pll;
297	298	switch (bus->chipinfo.id) {
298		- case 0x5356:
	299	+ case BCMA_CHIP_ID_BCM5356:
299	300	pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
300	301	break;
301		- case 0x5357:
302		- case 0x4749:
	302	+ case BCMA_CHIP_ID_BCM5357:
	303	+ case BCMA_CHIP_ID_BCM4749:
303	304	pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
304	305	break;
305	306	default:
...	...	@@ -307,7 +308,7 @@
307	308	break;
308	309	}
309	310
310		- /* TODO: if (bus->chipinfo.id == 0x5300)
	311	+ /* TODO: if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
311	312	return si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_CPU); */
312	313	return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
313	314	}
...	...	@@ -22,15 +22,15 @@
22	22	/* The 47162a0 hangs when reading MIPS DMP registers registers */
23	23	static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
24	24	{
25		- return dev->bus->chipinfo.id == 47162 && dev->bus->chipinfo.rev == 0 &&
26		- dev->id.id == BCMA_CORE_MIPS_74K;
	25	+ return dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM47162 &&
	26	+ dev->bus->chipinfo.rev == 0 && dev->id.id == BCMA_CORE_MIPS_74K;
27	27	}
28	28
29	29	/* The 5357b0 hangs when reading USB20H DMP registers */
30	30	static inline bool bcma_core_mips_bcm5357b0_quirk(struct bcma_device *dev)
31	31	{
32		- return (dev->bus->chipinfo.id == 0x5357 \|\|
33		- dev->bus->chipinfo.id == 0x4749) &&
	32	+ return (dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 \|\|
	33	+ dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) &&
34	34	dev->bus->chipinfo.pkg == 11 &&
35	35	dev->id.id == BCMA_CORE_USB20_HOST;
36	36	}
...	...	@@ -215,7 +215,8 @@
215	215	} else {
216	216	writel(val, mmio);
217	217
218		- if (chipid == 0x4716 \|\| chipid == 0x4748)
	218	+ if (chipid == BCMA_CHIP_ID_BCM4716 \|\|
	219	+ chipid == BCMA_CHIP_ID_BCM4748)
219	220	readl(mmio);
220	221	}
221	222
222	223
...	...	@@ -434,13 +435,14 @@
434	435	* as mips can't generate 64-bit address on the
435	436	* backplane.
436	437	*/
437		- if (bus->chipinfo.id == 0x4716 \|\| bus->chipinfo.id == 0x4748) {
	438	+ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4716 \|\|
	439	+ bus->chipinfo.id == BCMA_CHIP_ID_BCM4748) {
438	440	pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
439	441	pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
440	442	BCMA_SOC_PCI_MEM_SZ - 1;
441	443	pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
442	444	BCMA_CORE_PCI_SBTOPCI_MEM \| BCMA_SOC_PCI_MEM);
443		- } else if (bus->chipinfo.id == 0x5300) {
	445	+ } else if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
444	446	tmp = BCMA_CORE_PCI_SBTOPCI_MEM;
445	447	tmp \|= BCMA_CORE_PCI_SBTOPCI_PREF;
446	448	tmp \|= BCMA_CORE_PCI_SBTOPCI_BURST;
...	...	@@ -468,11 +468,11 @@
468	468	/* older chipcommon revisions use chip status register */
469	469	chip_status = bcma_read32(bus->drv_cc.core, BCMA_CC_CHIPSTAT);
470	470	switch (bus->chipinfo.id) {
471		- case 0x4313:
	471	+ case BCMA_CHIP_ID_BCM4313:
472	472	present_mask = BCMA_CC_CHIPST_4313_SPROM_PRESENT;
473	473	break;
474	474
475		- case 0x4331:
	475	+ case BCMA_CHIP_ID_BCM4331:
476	476	present_mask = BCMA_CC_CHIPST_4331_SPROM_PRESENT;
477	477	break;
478	478
479	479
480	480
...	...	@@ -494,16 +494,16 @@
494	494
495	495	chip_status = bcma_read32(bus->drv_cc.core, BCMA_CC_CHIPSTAT);
496	496	switch (bus->chipinfo.id) {
497		- case 0x4313:
	497	+ case BCMA_CHIP_ID_BCM4313:
498	498	present = chip_status & BCMA_CC_CHIPST_4313_OTP_PRESENT;
499	499	break;
500	500
501		- case 0x4331:
	501	+ case BCMA_CHIP_ID_BCM4331:
502	502	present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
503	503	break;
504	504
505		- case 43224:
506		- case 43225:
	505	+ case BCMA_CHIP_ID_BCM43224:
	506	+ case BCMA_CHIP_ID_BCM43225:
507	507	/* for these chips OTP is always available */
508	508	present = true;
509	509	break;
510	510
...	...	@@ -579,13 +579,15 @@
579	579	if (!sprom)
580	580	return -ENOMEM;
581	581
582		- if (bus->chipinfo.id == 0x4331 \|\| bus->chipinfo.id == 43431)
	582	+ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 \|\|
	583	+ bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
583	584	bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
584	585
585	586	pr_debug("SPROM offset 0x%x\n", offset);
586	587	bcma_sprom_read(bus, offset, sprom);
587	588
588		- if (bus->chipinfo.id == 0x4331 \|\| bus->chipinfo.id == 43431)
	589	+ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 \|\|
	590	+ bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
589	591	bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
590	592
591	593	err = bcma_sprom_valid(sprom);
...	...	@@ -137,6 +137,36 @@
137	137
138	138	#define BCMA_MAX_NR_CORES 16
139	139
	140	+/* Chip IDs of PCIe devices */
	141	+#define BCMA_CHIP_ID_BCM4313 0x4313
	142	+#define BCMA_CHIP_ID_BCM43224 43224
	143	+#define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
	144	+#define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
	145	+#define BCMA_CHIP_ID_BCM43225 43225
	146	+#define BCMA_CHIP_ID_BCM43227 43227
	147	+#define BCMA_CHIP_ID_BCM43228 43228
	148	+#define BCMA_CHIP_ID_BCM43421 43421
	149	+#define BCMA_CHIP_ID_BCM43428 43428
	150	+#define BCMA_CHIP_ID_BCM43431 43431
	151	+#define BCMA_CHIP_ID_BCM43460 43460
	152	+#define BCMA_CHIP_ID_BCM4331 0x4331
	153	+#define BCMA_CHIP_ID_BCM6362 0x6362
	154	+#define BCMA_CHIP_ID_BCM4360 0x4360
	155	+#define BCMA_CHIP_ID_BCM4352 0x4352
	156	+
	157	+/* Chip IDs of SoCs */
	158	+#define BCMA_CHIP_ID_BCM4706 0x5300
	159	+#define BCMA_CHIP_ID_BCM4716 0x4716
	160	+#define BCMA_PKG_ID_BCM4716 8
	161	+#define BCMA_PKG_ID_BCM4717 9
	162	+#define BCMA_PKG_ID_BCM4718 10
	163	+#define BCMA_CHIP_ID_BCM47162 47162
	164	+#define BCMA_CHIP_ID_BCM4748 0x4748
	165	+#define BCMA_CHIP_ID_BCM4749 0x4749
	166	+#define BCMA_CHIP_ID_BCM5356 0x5356
	167	+#define BCMA_CHIP_ID_BCM5357 0x5357
	168	+#define BCMA_CHIP_ID_BCM53572 53572
	169	+
140	170	struct bcma_device {
141	171	struct bcma_bus *bus;
142	172	struct bcma_device_id id;