[PATCH] i386: inline asm cleanup

i386 Inline asm cleanup. Use cr/dr accessor functions. Also, a potential bugfix. Also, some CR accessors really should be volatile. Reads from CR0 (numeric state may change in an exception handler), writes to CR4 (flipping CR4.TSD) and reads from CR2 (page fault) prevent instruction re-ordering. I did not add memory clobber to CR3 / CR4 / CR0 updates, as it was not there to begin with, and in no case should kernel memory be clobbered, except when doing a TLB flush, which already has memory clobber. I noticed that page invalidation does not have a memory clobber. I can't find a bug as a result, but there is definitely a potential for a bug here: #define __flush_tlb_single(addr) \ __asm__ __volatile__("invlpg %0": :"m" (*(char *) addr)) Signed-off-by: Zachary Amsden <zach@vmware.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>

[PATCH] i386: inline asm cleanup
i386 Inline asm cleanup. Use cr/dr accessor functions. Also, a potential bugfix. Also, some CR accessors really should be volatile. Reads from CR0 (numeric state may change in an exception handler), writes to CR4 (flipping CR4.TSD) and reads from CR2 (page fault) prevent instruction re-ordering. I did not add memory clobber to CR3 / CR4 / CR0 updates, as it was not there to begin with, and in no case should kernel memory be clobbered, except when doing a TLB flush, which already has memory clobber. I noticed that page invalidation does not have a memory clobber. I can't find a bug as a result, but there is definitely a potential for a bug here: #define __flush_tlb_single(addr) \ __asm__ __volatile__("invlpg %0": :"m" (*(char *) addr)) Signed-off-by: Zachary Amsden <zach@vmware.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Zachary Amsden · Linus Torvalds
1 parent 2a0694d15d
Showing 15 changed files with 84 additions and 83 deletions Side-by-side Diff
arch/i386/kernel/cpu/common.c
arch/i386/kernel/cpu/cpufreq/longhaul.c
arch/i386/kernel/cpu/cyrix.c
arch/i386/kernel/efi.c
arch/i386/kernel/machine_kexec.c
arch/i386/kernel/process.c
arch/i386/kernel/smp.c
arch/i386/mm/fault.c
arch/i386/mm/pageattr.c
arch/i386/power/cpu.c
include/asm-i386/agp.h
include/asm-i386/bugs.h
include/asm-i386/processor.h
include/asm-i386/system.h
include/asm-i386/xor.h
@@ -642,12 +642,12 @@
 	asm volatile ("xorl %eax, %eax; movl %eax, %fs; movl %eax, %gs");
  
 	/* Clear all 6 debug registers: */
-
-#define CD(register) set_debugreg(0, register)
-
-	CD(0); CD(1); CD(2); CD(3); /* no db4 and db5 */; CD(6); CD(7);
-
-#undef CD
+	set_debugreg(0, 0);
+	set_debugreg(0, 1);
+	set_debugreg(0, 2);
+	set_debugreg(0, 3);
+	set_debugreg(0, 6);
+	set_debugreg(0, 7);
  
 	/*
 	 * Force FPU initialization:
@@ -64,8 +64,6 @@
 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "longhaul", msg)
  
  
-#define __hlt()     __asm__ __volatile__("hlt": : :"memory")
-
 /* Clock ratios multiplied by 10 */
 static int clock_ratio[32];
 static int eblcr_table[32];
  
@@ -168,11 +166,9 @@
 	outb(0xFE,0x21);	/* TMR0 only */
 	outb(0xFF,0x80);	/* delay */
  
-	local_irq_enable();
-
-	__hlt();
+	safe_halt();
 	wrmsrl(MSR_VIA_LONGHAUL, longhaul->val);
-	__hlt();
+	halt();
  
 	local_irq_disable();
  
@@ -251,9 +247,7 @@
 		bcr2.bits.CLOCKMUL = clock_ratio_index;
 		local_irq_disable();
 		wrmsrl (MSR_VIA_BCR2, bcr2.val);
-		local_irq_enable();
-
-		__hlt();
+		safe_halt();
  
 		/* Disable software clock multiplier */
 		rdmsrl (MSR_VIA_BCR2, bcr2.val);
@@ -132,11 +132,7 @@
 	setCx86(CX86_CCR2, getCx86(CX86_CCR2) & ~0x04);
 	/* set 'Not Write-through' */
 	cr0 = 0x20000000;
-	__asm__("movl %%cr0,%%eax\n\t"
-		"orl %0,%%eax\n\t"
-		"movl %%eax,%%cr0\n"
-		: : "r" (cr0)
-		:"ax");
+	write_cr0(read_cr0() | cr0);
 	/* CCR2 bit 2: lock NW bit and set WT1 */
 	setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x14 );
 }
@@ -79,7 +79,7 @@
 	 * directory. If I have PSE, I just need to duplicate one entry in
 	 * page directory.
 	 */
-	__asm__ __volatile__("movl %%cr4, %0":"=r"(cr4));
+	cr4 = read_cr4();
  
 	if (cr4 & X86_CR4_PSE) {
 		efi_bak_pg_dir_pointer[0].pgd =
@@ -115,7 +115,7 @@
 	cpu_gdt_descr[0].address =
 		(unsigned long) __va(cpu_gdt_descr[0].address);
 	__asm__ __volatile__("lgdt %0":"=m"(cpu_gdt_descr));
-	__asm__ __volatile__("movl %%cr4, %0":"=r"(cr4));
+	cr4 = read_cr4();
  
 	if (cr4 & X86_CR4_PSE) {
 		swapper_pg_dir[pgd_index(0)].pgd =
@@ -17,13 +17,7 @@
 #include <asm/apic.h>
 #include <asm/cpufeature.h>
 #include <asm/desc.h>
-
-static inline unsigned long read_cr3(void)
-{
-	unsigned long cr3;
-	asm volatile("movl %%cr3,%0": "=r"(cr3));
-	return cr3;
-}
+#include <asm/system.h>
  
 #define PAGE_ALIGNED __attribute__ ((__aligned__(PAGE_SIZE)))
  
@@ -313,16 +313,12 @@
 	printk(" DS: %04x ES: %04x\n",
 		0xffff & regs->xds,0xffff & regs->xes);
  
-	__asm__("movl %%cr0, %0": "=r" (cr0));
-	__asm__("movl %%cr2, %0": "=r" (cr2));
-	__asm__("movl %%cr3, %0": "=r" (cr3));
-	/* This could fault if %cr4 does not exist */
-	__asm__("1: movl %%cr4, %0		\n"
-		"2:				\n"
-		".section __ex_table,\"a\"	\n"
-		".long 1b,2b			\n"
-		".previous			\n"
-		: "=r" (cr4): "0" (0));
+	cr0 = read_cr0();
+	cr2 = read_cr2();
+	cr3 = read_cr3();
+	if (current_cpu_data.x86 > 4) {
+		cr4 = read_cr4();
+	}
 	printk("CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n", cr0, cr2, cr3, cr4);
 	show_trace(NULL, &regs->esp);
 }
@@ -576,7 +576,7 @@
 	local_irq_disable();
 	disable_local_APIC();
 	if (cpu_data[smp_processor_id()].hlt_works_ok)
-		for(;;) __asm__("hlt");
+		for(;;) halt();
 	for (;;);
 }
  
@@ -233,7 +233,7 @@
 	int write, si_code;
  
 	/* get the address */
-	__asm__("movl %%cr2,%0":"=r" (address));
+        address = read_cr2();
  
 	if (notify_die(DIE_PAGE_FAULT, "page fault", regs, error_code, 14,
 					SIGSEGV) == NOTIFY_STOP)
@@ -453,7 +453,7 @@
 	printk(" at virtual address %08lx\n",address);
 	printk(KERN_ALERT " printing eip:\n");
 	printk("%08lx\n", regs->eip);
-	asm("movl %%cr3,%0":"=r" (page));
+	page = read_cr3();
 	page = ((unsigned long *) __va(page))[address >> 22];
 	printk(KERN_ALERT "*pde = %08lx\n", page);
 	/*
@@ -526,7 +526,7 @@
 		pmd_t *pmd, *pmd_k;
 		pte_t *pte_k;
  
-		asm("movl %%cr3,%0":"=r" (pgd_paddr));
+		pgd_paddr = read_cr3();
 		pgd = index + (pgd_t *)__va(pgd_paddr);
 		pgd_k = init_mm.pgd + index;
  
@@ -62,7 +62,7 @@
 { 
 	/* Could use CLFLUSH here if the CPU supports it (Hammer,P4) */
 	if (boot_cpu_data.x86_model >= 4) 
-		asm volatile("wbinvd":::"memory"); 
+		wbinvd();
 	/* Flush all to work around Errata in early athlons regarding 
 	 * large page flushing. 
 	 */
@@ -57,10 +57,10 @@
 	/*
 	 * control registers 
 	 */
-	asm volatile ("movl %%cr0, %0" : "=r" (ctxt->cr0));
-	asm volatile ("movl %%cr2, %0" : "=r" (ctxt->cr2));
-	asm volatile ("movl %%cr3, %0" : "=r" (ctxt->cr3));
-	asm volatile ("movl %%cr4, %0" : "=r" (ctxt->cr4));
+	ctxt->cr0 = read_cr0();
+	ctxt->cr2 = read_cr2();
+	ctxt->cr3 = read_cr3();
+	ctxt->cr4 = read_cr4();
 }
  
 void save_processor_state(void)
@@ -109,10 +109,10 @@
 	/*
 	 * control registers
 	 */
-	asm volatile ("movl %0, %%cr4" :: "r" (ctxt->cr4));
-	asm volatile ("movl %0, %%cr3" :: "r" (ctxt->cr3));
-	asm volatile ("movl %0, %%cr2" :: "r" (ctxt->cr2));
-	asm volatile ("movl %0, %%cr0" :: "r" (ctxt->cr0));
+	write_cr4(ctxt->cr4);
+	write_cr3(ctxt->cr3);
+	write_cr2(ctxt->cr2);
+	write_cr2(ctxt->cr0);
  
 	/*
 	 * now restore the descriptor tables to their proper values
@@ -19,7 +19,7 @@
 /* Could use CLFLUSH here if the cpu supports it. But then it would
    need to be called for each cacheline of the whole page so it may not be 
    worth it. Would need a page for it. */
-#define flush_agp_cache() asm volatile("wbinvd":::"memory")
+#define flush_agp_cache() wbinvd()
  
 /* Convert a physical address to an address suitable for the GART. */
 #define phys_to_gart(x) (x)
@@ -118,7 +118,10 @@
 		printk("disabled\n");
 		return;
 	}
-	__asm__ __volatile__("hlt ; hlt ; hlt ; hlt");
+	halt();
+	halt();
+	halt();
+	halt();
 	printk("OK.\n");
 }
  
@@ -203,10 +203,8 @@
 	return edx;
 }
  
-#define load_cr3(pgdir) \
-	asm volatile("movl %0,%%cr3": :"r" (__pa(pgdir)))
+#define load_cr3(pgdir) write_cr3(__pa(pgdir))
  
-
 /*
  * Intel CPU features in CR4
  */
  
  
  
@@ -232,22 +230,20 @@
  
 static inline void set_in_cr4 (unsigned long mask)
 {
+	unsigned cr4;
 	mmu_cr4_features |= mask;
-	__asm__("movl %%cr4,%%eax\n\t"
-		"orl %0,%%eax\n\t"
-		"movl %%eax,%%cr4\n"
-		: : "irg" (mask)
-		:"ax");
+	cr4 = read_cr4();
+	cr4 |= mask;
+	write_cr4(cr4);
 }
  
 static inline void clear_in_cr4 (unsigned long mask)
 {
+	unsigned cr4;
 	mmu_cr4_features &= ~mask;
-	__asm__("movl %%cr4,%%eax\n\t"
-		"andl %0,%%eax\n\t"
-		"movl %%eax,%%cr4\n"
-		: : "irg" (~mask)
-		:"ax");
+	cr4 = read_cr4();
+	cr4 &= ~mask;
+	write_cr4(cr4);
 }
  
 /*
@@ -107,14 +107,34 @@
 #define clts() __asm__ __volatile__ ("clts")
 #define read_cr0() ({ \
 	unsigned int __dummy; \
-	__asm__( \
+	__asm__ __volatile__( \
 		"movl %%cr0,%0\n\t" \
 		:"=r" (__dummy)); \
 	__dummy; \
 })
 #define write_cr0(x) \
-	__asm__("movl %0,%%cr0": :"r" (x));
+	__asm__ __volatile__("movl %0,%%cr0": :"r" (x));
  
+#define read_cr2() ({ \
+	unsigned int __dummy; \
+	__asm__ __volatile__( \
+		"movl %%cr2,%0\n\t" \
+		:"=r" (__dummy)); \
+	__dummy; \
+})
+#define write_cr2(x) \
+	__asm__ __volatile__("movl %0,%%cr2": :"r" (x));
+
+#define read_cr3() ({ \
+	unsigned int __dummy; \
+	__asm__ ( \
+		"movl %%cr3,%0\n\t" \
+		:"=r" (__dummy)); \
+	__dummy; \
+})
+#define write_cr3(x) \
+	__asm__ __volatile__("movl %0,%%cr3": :"r" (x));
+
 #define read_cr4() ({ \
 	unsigned int __dummy; \
 	__asm__( \
@@ -123,7 +143,7 @@
 	__dummy; \
 })
 #define write_cr4(x) \
-	__asm__("movl %0,%%cr4": :"r" (x));
+	__asm__ __volatile__("movl %0,%%cr4": :"r" (x));
 #define stts() write_cr0(8 | read_cr0())
  
 #endif	/* __KERNEL__ */
@@ -447,6 +467,8 @@
 #define local_irq_enable()	__asm__ __volatile__("sti": : :"memory")
 /* used in the idle loop; sti takes one instruction cycle to complete */
 #define safe_halt()		__asm__ __volatile__("sti; hlt": : :"memory")
+/* used when interrupts are already enabled or to shutdown the processor */
+#define halt()			__asm__ __volatile__("hlt": : :"memory")
  
 #define irqs_disabled()			\
 ({					\
@@ -535,14 +535,14 @@
  
 #define XMMS_SAVE do {				\
 	preempt_disable();			\
+	cr0 = read_cr0();			\
+	clts();					\
 	__asm__ __volatile__ ( 			\
-		"movl %%cr0,%0		;\n\t"	\
-		"clts			;\n\t"	\
-		"movups %%xmm0,(%1)	;\n\t"	\
-		"movups %%xmm1,0x10(%1)	;\n\t"	\
-		"movups %%xmm2,0x20(%1)	;\n\t"	\
-		"movups %%xmm3,0x30(%1)	;\n\t"	\
-		: "=&r" (cr0)			\
+		"movups %%xmm0,(%0)	;\n\t"	\
+		"movups %%xmm1,0x10(%0)	;\n\t"	\
+		"movups %%xmm2,0x20(%0)	;\n\t"	\
+		"movups %%xmm3,0x30(%0)	;\n\t"	\
+		:				\
 		: "r" (xmm_save) 		\
 		: "memory");			\
 } while(0)
  
  
@@ -550,14 +550,14 @@
 #define XMMS_RESTORE do {			\
 	__asm__ __volatile__ ( 			\
 		"sfence			;\n\t"	\
-		"movups (%1),%%xmm0	;\n\t"	\
-		"movups 0x10(%1),%%xmm1	;\n\t"	\
-		"movups 0x20(%1),%%xmm2	;\n\t"	\
-		"movups 0x30(%1),%%xmm3	;\n\t"	\
-		"movl 	%0,%%cr0	;\n\t"	\
+		"movups (%0),%%xmm0	;\n\t"	\
+		"movups 0x10(%0),%%xmm1	;\n\t"	\
+		"movups 0x20(%0),%%xmm2	;\n\t"	\
+		"movups 0x30(%0),%%xmm3	;\n\t"	\
 		:				\
-		: "r" (cr0), "r" (xmm_save)	\
+		: "r" (xmm_save)		\
 		: "memory");			\
+	write_cr0(cr0);				\
 	preempt_enable();			\
 } while(0)
...	...	@@ -642,12 +642,12 @@
642	642	asm volatile ("xorl %eax, %eax; movl %eax, %fs; movl %eax, %gs");
643	643
644	644	/* Clear all 6 debug registers: */
645		-
646		-#define CD(register) set_debugreg(0, register)
647		-
648		- CD(0); CD(1); CD(2); CD(3); /* no db4 and db5 */; CD(6); CD(7);
649		-
650		-#undef CD
	645	+ set_debugreg(0, 0);
	646	+ set_debugreg(0, 1);
	647	+ set_debugreg(0, 2);
	648	+ set_debugreg(0, 3);
	649	+ set_debugreg(0, 6);
	650	+ set_debugreg(0, 7);
651	651
652	652	/*
653	653	* Force FPU initialization:
...	...	@@ -64,8 +64,6 @@
64	64	#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "longhaul", msg)
65	65
66	66
67		-#define __hlt() __asm__ __volatile__("hlt": : :"memory")
68		-
69	67	/* Clock ratios multiplied by 10 */
70	68	static int clock_ratio[32];
71	69	static int eblcr_table[32];
72	70
...	...	@@ -168,11 +166,9 @@
168	166	outb(0xFE,0x21); /* TMR0 only */
169	167	outb(0xFF,0x80); /* delay */
170	168
171		- local_irq_enable();
172		-
173		- __hlt();
	169	+ safe_halt();
174	170	wrmsrl(MSR_VIA_LONGHAUL, longhaul->val);
175		- __hlt();
	171	+ halt();
176	172
177	173	local_irq_disable();
178	174
...	...	@@ -251,9 +247,7 @@
251	247	bcr2.bits.CLOCKMUL = clock_ratio_index;
252	248	local_irq_disable();
253	249	wrmsrl (MSR_VIA_BCR2, bcr2.val);
254		- local_irq_enable();
255		-
256		- __hlt();
	250	+ safe_halt();
257	251
258	252	/* Disable software clock multiplier */
259	253	rdmsrl (MSR_VIA_BCR2, bcr2.val);
...	...	@@ -132,11 +132,7 @@
132	132	setCx86(CX86_CCR2, getCx86(CX86_CCR2) & ~0x04);
133	133	/* set 'Not Write-through' */
134	134	cr0 = 0x20000000;
135		- __asm__("movl %%cr0,%%eax\n\t"
136		- "orl %0,%%eax\n\t"
137		- "movl %%eax,%%cr0\n"
138		- : : "r" (cr0)
139		- :"ax");
	135	+ write_cr0(read_cr0() \| cr0);
140	136	/* CCR2 bit 2: lock NW bit and set WT1 */
141	137	setCx86(CX86_CCR2, getCx86(CX86_CCR2) \| 0x14 );
142	138	}
...	...	@@ -79,7 +79,7 @@
79	79	* directory. If I have PSE, I just need to duplicate one entry in
80	80	* page directory.
81	81	*/
82		- __asm__ __volatile__("movl %%cr4, %0":"=r"(cr4));
	82	+ cr4 = read_cr4();
83	83
84	84	if (cr4 & X86_CR4_PSE) {
85	85	efi_bak_pg_dir_pointer[0].pgd =
...	...	@@ -115,7 +115,7 @@
115	115	cpu_gdt_descr[0].address =
116	116	(unsigned long) __va(cpu_gdt_descr[0].address);
117	117	__asm__ __volatile__("lgdt %0":"=m"(cpu_gdt_descr));
118		- __asm__ __volatile__("movl %%cr4, %0":"=r"(cr4));
	118	+ cr4 = read_cr4();
119	119
120	120	if (cr4 & X86_CR4_PSE) {
121	121	swapper_pg_dir[pgd_index(0)].pgd =
...	...	@@ -17,13 +17,7 @@
17	17	#include <asm/apic.h>
18	18	#include <asm/cpufeature.h>
19	19	#include <asm/desc.h>
20		-
21		-static inline unsigned long read_cr3(void)
22		-{
23		- unsigned long cr3;
24		- asm volatile("movl %%cr3,%0": "=r"(cr3));
25		- return cr3;
26		-}
	20	+#include <asm/system.h>
27	21
28	22	#define PAGE_ALIGNED __attribute__ ((__aligned__(PAGE_SIZE)))
29	23
...	...	@@ -313,16 +313,12 @@
313	313	printk(" DS: %04x ES: %04x\n",
314	314	0xffff & regs->xds,0xffff & regs->xes);
315	315
316		- __asm__("movl %%cr0, %0": "=r" (cr0));
317		- __asm__("movl %%cr2, %0": "=r" (cr2));
318		- __asm__("movl %%cr3, %0": "=r" (cr3));
319		- /* This could fault if %cr4 does not exist */
320		- __asm__("1: movl %%cr4, %0 \n"
321		- "2: \n"
322		- ".section __ex_table,\"a\" \n"
323		- ".long 1b,2b \n"
324		- ".previous \n"
325		- : "=r" (cr4): "0" (0));
	316	+ cr0 = read_cr0();
	317	+ cr2 = read_cr2();
	318	+ cr3 = read_cr3();
	319	+ if (current_cpu_data.x86 > 4) {
	320	+ cr4 = read_cr4();
	321	+ }
326	322	printk("CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n", cr0, cr2, cr3, cr4);
327	323	show_trace(NULL, &regs->esp);
328	324	}
...	...	@@ -576,7 +576,7 @@
576	576	local_irq_disable();
577	577	disable_local_APIC();
578	578	if (cpu_data[smp_processor_id()].hlt_works_ok)
579		- for(;;) __asm__("hlt");
	579	+ for(;;) halt();
580	580	for (;;);
581	581	}
582	582
...	...	@@ -233,7 +233,7 @@
233	233	int write, si_code;
234	234
235	235	/* get the address */
236		- __asm__("movl %%cr2,%0":"=r" (address));
	236	+ address = read_cr2();
237	237
238	238	if (notify_die(DIE_PAGE_FAULT, "page fault", regs, error_code, 14,
239	239	SIGSEGV) == NOTIFY_STOP)
...	...	@@ -453,7 +453,7 @@
453	453	printk(" at virtual address %08lx\n",address);
454	454	printk(KERN_ALERT " printing eip:\n");
455	455	printk("%08lx\n", regs->eip);
456		- asm("movl %%cr3,%0":"=r" (page));
	456	+ page = read_cr3();
457	457	page = ((unsigned long *) __va(page))[address >> 22];
458	458	printk(KERN_ALERT "*pde = %08lx\n", page);
459	459	/*
...	...	@@ -526,7 +526,7 @@
526	526	pmd_t pmd, pmd_k;
527	527	pte_t *pte_k;
528	528
529		- asm("movl %%cr3,%0":"=r" (pgd_paddr));
	529	+ pgd_paddr = read_cr3();
530	530	pgd = index + (pgd_t *)__va(pgd_paddr);
531	531	pgd_k = init_mm.pgd + index;
532	532
...	...	@@ -62,7 +62,7 @@
62	62	{
63	63	/* Could use CLFLUSH here if the CPU supports it (Hammer,P4) */
64	64	if (boot_cpu_data.x86_model >= 4)
65		- asm volatile("wbinvd":::"memory");
	65	+ wbinvd();
66	66	/* Flush all to work around Errata in early athlons regarding
67	67	* large page flushing.
68	68	*/
...	...	@@ -57,10 +57,10 @@
57	57	/*
58	58	* control registers
59	59	*/
60		- asm volatile ("movl %%cr0, %0" : "=r" (ctxt->cr0));
61		- asm volatile ("movl %%cr2, %0" : "=r" (ctxt->cr2));
62		- asm volatile ("movl %%cr3, %0" : "=r" (ctxt->cr3));
63		- asm volatile ("movl %%cr4, %0" : "=r" (ctxt->cr4));
	60	+ ctxt->cr0 = read_cr0();
	61	+ ctxt->cr2 = read_cr2();
	62	+ ctxt->cr3 = read_cr3();
	63	+ ctxt->cr4 = read_cr4();
64	64	}
65	65
66	66	void save_processor_state(void)
...	...	@@ -109,10 +109,10 @@
109	109	/*
110	110	* control registers
111	111	*/
112		- asm volatile ("movl %0, %%cr4" :: "r" (ctxt->cr4));
113		- asm volatile ("movl %0, %%cr3" :: "r" (ctxt->cr3));
114		- asm volatile ("movl %0, %%cr2" :: "r" (ctxt->cr2));
115		- asm volatile ("movl %0, %%cr0" :: "r" (ctxt->cr0));
	112	+ write_cr4(ctxt->cr4);
	113	+ write_cr3(ctxt->cr3);
	114	+ write_cr2(ctxt->cr2);
	115	+ write_cr2(ctxt->cr0);
116	116
117	117	/*
118	118	* now restore the descriptor tables to their proper values