drivers/block/umem: trim trailing whitespace

Signed-off-by: Jeff Garzik <jeff@garzik.org>

drivers/block/umem: trim trailing whitespace
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Jeff Garzik · Jens Axboe
1 parent ee4a7b6874
Showing 2 changed files with 18 additions and 18 deletions Side-by-side Diff
drivers/block/umem.c
drivers/block/umem.h
@@ -293,7 +293,7 @@
 	desc->control_bits &= ~cpu_to_le32(DMASCR_CHAIN_EN);
 	desc->sem_control_bits = desc->control_bits;
  
-			       
+
 	if (debug & DEBUG_LED_ON_TRANSFER)
 		set_led(card, LED_REMOVE, LED_ON);
  
@@ -327,7 +327,7 @@
  
 static void activate(struct cardinfo *card)
 {
-	/* if No page is Active, and Ready is 
+	/* if No page is Active, and Ready is
 	 * not empty, then switch Ready page
 	 * to active and start IO.
 	 * Then add any bh's that are available to Ready
@@ -366,7 +366,7 @@
 	spin_unlock_irqrestore(&card->lock, flags);
 }
  
-/* 
+/*
  * If there is room on Ready page, take
  * one bh off list and add it.
  * return 1 if there was room, else 0.
@@ -467,7 +467,7 @@
 	if (card->Active < 0)
 		goto out_unlock;
 	page = &card->mm_pages[card->Active];
-	
+
 	while (page->headcnt < page->cnt) {
 		struct bio *bio = page->bio;
 		struct mm_dma_desc *desc = &page->desc[page->headcnt];
@@ -477,7 +477,7 @@
  
 		if (!(control & DMASCR_DMA_COMPLETE)) {
 			control = dma_status;
-			last=1; 
+			last=1;
 		}
 		page->headcnt++;
 		idx = page->idx;
@@ -487,7 +487,7 @@
 			page->idx = page->bio->bi_idx;
 		}
  
-		pci_unmap_page(card->dev, desc->data_dma_handle, 
+		pci_unmap_page(card->dev, desc->data_dma_handle,
 			       bio_iovec_idx(bio,idx)->bv_len,
 				 (control& DMASCR_TRANSFER_READ) ?
 				PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
@@ -592,7 +592,7 @@
 	else
 		writeb((DMASCR_DMA_COMPLETE|DMASCR_CHAIN_COMPLETE) >> 16,
 		       card->csr_remap+ DMA_STATUS_CTRL + 2);
-	
+
 	/* log errors and clear interrupt status */
 	if (dma_status & DMASCR_ANY_ERR) {
 		unsigned int	data_log1, data_log2;
@@ -668,7 +668,7 @@
  
 HW_TRACE(0x36);
  
-	return IRQ_HANDLED; 
+	return IRQ_HANDLED;
 }
 /*
 -----------------------------------------------------------------------------------
@@ -761,7 +761,7 @@
 {
 	int i;
  
-	for (i = 0; i < num_cards; i++) 
+	for (i = 0; i < num_cards; i++)
 		if (!(cards[i].flags & UM_FLAG_NO_BATT)) {
 			struct cardinfo *card = &cards[i];
 			spin_lock_bh(&card->lock);
@@ -972,7 +972,7 @@
 	tasklet_init(&card->tasklet, process_page, (unsigned long)card);
  
 	card->check_batteries = 0;
-	
+
 	mem_present = readb(card->csr_remap + MEMCTRLSTATUS_MEMORY);
 	switch (mem_present) {
 	case MEM_128_MB:
@@ -1005,7 +1005,7 @@
 	card->battery[1].good = !(batt_status & BATTERY_2_FAILURE);
 	card->battery[0].last_change = card->battery[1].last_change = jiffies;
  
-	if (card->flags & UM_FLAG_NO_BATT) 
+	if (card->flags & UM_FLAG_NO_BATT)
 		dev_printk(KERN_INFO, &card->dev->dev,
 			"Size %d KB\n", card->mm_size);
 	else {
@@ -87,13 +87,13 @@
 #define  DMASCR_DMA_COMPLETE	0x40000
 #define  DMASCR_CHAIN_COMPLETE	0x80000
  
-/* 
-3.SOME PCs HAVE HOST BRIDGES WHICH APPARENTLY DO NOT CORRECTLY HANDLE 
-READ-LINE (0xE) OR READ-MULTIPLE (0xC) PCI COMMAND CODES DURING DMA 
-TRANSFERS. IN OTHER SYSTEMS THESE COMMAND CODES WILL CAUSE THE HOST BRIDGE 
-TO ALLOW LONGER BURSTS DURING DMA READ OPERATIONS. THE UPPER FOUR BITS 
-(31..28) OF THE DMA CSR HAVE BEEN MADE PROGRAMMABLE, SO THAT EITHER A 0x6, 
-AN 0xE OR A 0xC CAN BE WRITTEN TO THEM TO SET THE COMMAND CODE USED DURING 
+/*
+3.SOME PCs HAVE HOST BRIDGES WHICH APPARENTLY DO NOT CORRECTLY HANDLE
+READ-LINE (0xE) OR READ-MULTIPLE (0xC) PCI COMMAND CODES DURING DMA
+TRANSFERS. IN OTHER SYSTEMS THESE COMMAND CODES WILL CAUSE THE HOST BRIDGE
+TO ALLOW LONGER BURSTS DURING DMA READ OPERATIONS. THE UPPER FOUR BITS
+(31..28) OF THE DMA CSR HAVE BEEN MADE PROGRAMMABLE, SO THAT EITHER A 0x6,
+AN 0xE OR A 0xC CAN BE WRITTEN TO THEM TO SET THE COMMAND CODE USED DURING
 DMA READ OPERATIONS.
 */
 #define        DMASCR_READ   0x60000000
...	...	@@ -293,7 +293,7 @@
293	293	desc->control_bits &= ~cpu_to_le32(DMASCR_CHAIN_EN);
294	294	desc->sem_control_bits = desc->control_bits;
295	295
296		-
	296	+
297	297	if (debug & DEBUG_LED_ON_TRANSFER)
298	298	set_led(card, LED_REMOVE, LED_ON);
299	299
...	...	@@ -327,7 +327,7 @@
327	327
328	328	static void activate(struct cardinfo *card)
329	329	{
330		- /* if No page is Active, and Ready is
	330	+ /* if No page is Active, and Ready is
331	331	* not empty, then switch Ready page
332	332	* to active and start IO.
333	333	* Then add any bh's that are available to Ready
...	...	@@ -366,7 +366,7 @@
366	366	spin_unlock_irqrestore(&card->lock, flags);
367	367	}
368	368
369		-/*
	369	+/*
370	370	* If there is room on Ready page, take
371	371	* one bh off list and add it.
372	372	* return 1 if there was room, else 0.
...	...	@@ -467,7 +467,7 @@
467	467	if (card->Active < 0)
468	468	goto out_unlock;
469	469	page = &card->mm_pages[card->Active];
470		-
	470	+
471	471	while (page->headcnt < page->cnt) {
472	472	struct bio *bio = page->bio;
473	473	struct mm_dma_desc *desc = &page->desc[page->headcnt];
...	...	@@ -477,7 +477,7 @@
477	477
478	478	if (!(control & DMASCR_DMA_COMPLETE)) {
479	479	control = dma_status;
480		- last=1;
	480	+ last=1;
481	481	}
482	482	page->headcnt++;
483	483	idx = page->idx;
...	...	@@ -487,7 +487,7 @@
487	487	page->idx = page->bio->bi_idx;
488	488	}
489	489
490		- pci_unmap_page(card->dev, desc->data_dma_handle,
	490	+ pci_unmap_page(card->dev, desc->data_dma_handle,
491	491	bio_iovec_idx(bio,idx)->bv_len,
492	492	(control& DMASCR_TRANSFER_READ) ?
493	493	PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
...	...	@@ -592,7 +592,7 @@
592	592	else
593	593	writeb((DMASCR_DMA_COMPLETE\|DMASCR_CHAIN_COMPLETE) >> 16,
594	594	card->csr_remap+ DMA_STATUS_CTRL + 2);
595		-
	595	+
596	596	/* log errors and clear interrupt status */
597	597	if (dma_status & DMASCR_ANY_ERR) {
598	598	unsigned int data_log1, data_log2;
...	...	@@ -668,7 +668,7 @@
668	668
669	669	HW_TRACE(0x36);
670	670
671		- return IRQ_HANDLED;
	671	+ return IRQ_HANDLED;
672	672	}
673	673	/*
674	674	-----------------------------------------------------------------------------------
...	...	@@ -761,7 +761,7 @@
761	761	{
762	762	int i;
763	763
764		- for (i = 0; i < num_cards; i++)
	764	+ for (i = 0; i < num_cards; i++)
765	765	if (!(cards[i].flags & UM_FLAG_NO_BATT)) {
766	766	struct cardinfo *card = &cards[i];
767	767	spin_lock_bh(&card->lock);
...	...	@@ -972,7 +972,7 @@
972	972	tasklet_init(&card->tasklet, process_page, (unsigned long)card);
973	973
974	974	card->check_batteries = 0;
975		-
	975	+
976	976	mem_present = readb(card->csr_remap + MEMCTRLSTATUS_MEMORY);
977	977	switch (mem_present) {
978	978	case MEM_128_MB:
...	...	@@ -1005,7 +1005,7 @@
1005	1005	card->battery[1].good = !(batt_status & BATTERY_2_FAILURE);
1006	1006	card->battery[0].last_change = card->battery[1].last_change = jiffies;
1007	1007
1008		- if (card->flags & UM_FLAG_NO_BATT)
	1008	+ if (card->flags & UM_FLAG_NO_BATT)
1009	1009	dev_printk(KERN_INFO, &card->dev->dev,
1010	1010	"Size %d KB\n", card->mm_size);
1011	1011	else {
...	...	@@ -87,13 +87,13 @@
87	87	#define DMASCR_DMA_COMPLETE 0x40000
88	88	#define DMASCR_CHAIN_COMPLETE 0x80000
89	89
90		-/*
91		-3.SOME PCs HAVE HOST BRIDGES WHICH APPARENTLY DO NOT CORRECTLY HANDLE
92		-READ-LINE (0xE) OR READ-MULTIPLE (0xC) PCI COMMAND CODES DURING DMA
93		-TRANSFERS. IN OTHER SYSTEMS THESE COMMAND CODES WILL CAUSE THE HOST BRIDGE
94		-TO ALLOW LONGER BURSTS DURING DMA READ OPERATIONS. THE UPPER FOUR BITS
95		-(31..28) OF THE DMA CSR HAVE BEEN MADE PROGRAMMABLE, SO THAT EITHER A 0x6,
96		-AN 0xE OR A 0xC CAN BE WRITTEN TO THEM TO SET THE COMMAND CODE USED DURING
	90	+/*
	91	+3.SOME PCs HAVE HOST BRIDGES WHICH APPARENTLY DO NOT CORRECTLY HANDLE
	92	+READ-LINE (0xE) OR READ-MULTIPLE (0xC) PCI COMMAND CODES DURING DMA
	93	+TRANSFERS. IN OTHER SYSTEMS THESE COMMAND CODES WILL CAUSE THE HOST BRIDGE
	94	+TO ALLOW LONGER BURSTS DURING DMA READ OPERATIONS. THE UPPER FOUR BITS
	95	+(31..28) OF THE DMA CSR HAVE BEEN MADE PROGRAMMABLE, SO THAT EITHER A 0x6,
	96	+AN 0xE OR A 0xC CAN BE WRITTEN TO THEM TO SET THE COMMAND CODE USED DURING
97	97	DMA READ OPERATIONS.
98	98	*/
99	99	#define DMASCR_READ 0x60000000