Eric Lee / smarc-fsl-linux-kernel

Download as
Browse Code ยป

Commit 521674718af0f20fada7311a74c3f8fe23767d55

Authored by Sebastian Hesselbarth
Committed by Jason Cooper
1 parent 5817d10b8b

ARM: dove: add clock gating control 

This patch adds clock gates from the clock gating control register
available on dove. All clock gates are hooked up to tclk, except for
gigabit ethernet controller (ge) which is a child of gephy to allow
both enabled/disabled at the same time.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

Showing 2 changed files with 92 additions and 19 deletions Side-by-side Diff

arch/arm/mach-dove/common.c
Diff comments   View file @ 5216747
... ... @@ -24,6 +24,7 @@
24 24 #include <asm/mach/time.h>
25 25 #include <asm/mach/pci.h>
26 26 #include <mach/dove.h>
  27 +#include <mach/pm.h>
27 28 #include <mach/bridge-regs.h>
28 29 #include <asm/mach/arch.h>
29 30 #include <linux/irq.h>
30 31  
31 32  
32 33  
... ... @@ -69,14 +70,68 @@
69 70 * CLK tree
70 71 ****************************************************************************/
71 72 static int dove_tclk;
  73 +
  74 +static DEFINE_SPINLOCK(gating_lock);
72 75 static struct clk *tclk;
73 76  
  77 +static struct clk __init *dove_register_gate(const char *name,
  78 + const char *parent, u8 bit_idx)
  79 +{
  80 + return clk_register_gate(NULL, name, parent, 0,
  81 + (void __iomem *)CLOCK_GATING_CONTROL,
  82 + bit_idx, 0, &gating_lock);
  83 +}
  84 +
74 85 static void __init dove_clk_init(void)
75 86 {
  87 + struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1;
  88 + struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma;
  89 + struct clk *xor0, *xor1, *ge, *gephy;
  90 +
76 91 tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
77 92 dove_tclk);
78 93  
79   - orion_clkdev_init(tclk);
  94 + usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
  95 + usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
  96 + sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
  97 + pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0);
  98 + pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
  99 + sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
  100 + sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
  101 + nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
  102 + camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
  103 + i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
  104 + i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
  105 + crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
  106 + ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
  107 + pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
  108 + xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
  109 + xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
  110 + gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
  111 + ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);
  112 +
  113 + orion_clkdev_add(NULL, "orion_spi.0", tclk);
  114 + orion_clkdev_add(NULL, "orion_spi.1", tclk);
  115 + orion_clkdev_add(NULL, "orion_wdt", tclk);
  116 + orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk);
  117 +
  118 + orion_clkdev_add(NULL, "orion-ehci.0", usb0);
  119 + orion_clkdev_add(NULL, "orion-ehci.1", usb1);
  120 + orion_clkdev_add(NULL, "mv643xx_eth.0", ge);
  121 + orion_clkdev_add("0", "sata_mv.0", sata);
  122 + orion_clkdev_add("0", "pcie", pex0);
  123 + orion_clkdev_add("1", "pcie", pex1);
  124 + orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
  125 + orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
  126 + orion_clkdev_add(NULL, "orion_nand", nand);
  127 + orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
  128 + orion_clkdev_add(NULL, "kirkwood-i2s.0", i2s0);
  129 + orion_clkdev_add(NULL, "kirkwood-i2s.1", i2s1);
  130 + orion_clkdev_add(NULL, "mv_crypto", crypto);
  131 + orion_clkdev_add(NULL, "dove-ac97", ac97);
  132 + orion_clkdev_add(NULL, "dove-pdma", pdma);
  133 + orion_clkdev_add(NULL, "mv_xor_shared.0", xor0);
  134 + orion_clkdev_add(NULL, "mv_xor_shared.1", xor1);
80 135 }
81 136  
82 137 /*****************************************************************************
arch/arm/mach-dove/include/mach/pm.h
Diff comments   View file @ 5216747
... ... @@ -13,24 +13,42 @@
13 13 #include <mach/irqs.h>
14 14  
15 15 #define CLOCK_GATING_CONTROL (DOVE_PMU_VIRT_BASE + 0x38)
16   -#define CLOCK_GATING_USB0_MASK (1 << 0)
17   -#define CLOCK_GATING_USB1_MASK (1 << 1)
18   -#define CLOCK_GATING_GBE_MASK (1 << 2)
19   -#define CLOCK_GATING_SATA_MASK (1 << 3)
20   -#define CLOCK_GATING_PCIE0_MASK (1 << 4)
21   -#define CLOCK_GATING_PCIE1_MASK (1 << 5)
22   -#define CLOCK_GATING_SDIO0_MASK (1 << 8)
23   -#define CLOCK_GATING_SDIO1_MASK (1 << 9)
24   -#define CLOCK_GATING_NAND_MASK (1 << 10)
25   -#define CLOCK_GATING_CAMERA_MASK (1 << 11)
26   -#define CLOCK_GATING_I2S0_MASK (1 << 12)
27   -#define CLOCK_GATING_I2S1_MASK (1 << 13)
28   -#define CLOCK_GATING_CRYPTO_MASK (1 << 15)
29   -#define CLOCK_GATING_AC97_MASK (1 << 21)
30   -#define CLOCK_GATING_PDMA_MASK (1 << 22)
31   -#define CLOCK_GATING_XOR0_MASK (1 << 23)
32   -#define CLOCK_GATING_XOR1_MASK (1 << 24)
33   -#define CLOCK_GATING_GIGA_PHY_MASK (1 << 30)
  16 +#define CLOCK_GATING_BIT_USB0 0
  17 +#define CLOCK_GATING_BIT_USB1 1
  18 +#define CLOCK_GATING_BIT_GBE 2
  19 +#define CLOCK_GATING_BIT_SATA 3
  20 +#define CLOCK_GATING_BIT_PCIE0 4
  21 +#define CLOCK_GATING_BIT_PCIE1 5
  22 +#define CLOCK_GATING_BIT_SDIO0 8
  23 +#define CLOCK_GATING_BIT_SDIO1 9
  24 +#define CLOCK_GATING_BIT_NAND 10
  25 +#define CLOCK_GATING_BIT_CAMERA 11
  26 +#define CLOCK_GATING_BIT_I2S0 12
  27 +#define CLOCK_GATING_BIT_I2S1 13
  28 +#define CLOCK_GATING_BIT_CRYPTO 15
  29 +#define CLOCK_GATING_BIT_AC97 21
  30 +#define CLOCK_GATING_BIT_PDMA 22
  31 +#define CLOCK_GATING_BIT_XOR0 23
  32 +#define CLOCK_GATING_BIT_XOR1 24
  33 +#define CLOCK_GATING_BIT_GIGA_PHY 30
  34 +#define CLOCK_GATING_USB0_MASK (1 << CLOCK_GATING_BIT_USB0)
  35 +#define CLOCK_GATING_USB1_MASK (1 << CLOCK_GATING_BIT_USB1)
  36 +#define CLOCK_GATING_GBE_MASK (1 << CLOCK_GATING_BIT_GBE)
  37 +#define CLOCK_GATING_SATA_MASK (1 << CLOCK_GATING_BIT_SATA)
  38 +#define CLOCK_GATING_PCIE0_MASK (1 << CLOCK_GATING_BIT_PCIE0)
  39 +#define CLOCK_GATING_PCIE1_MASK (1 << CLOCK_GATING_BIT_PCIE1)
  40 +#define CLOCK_GATING_SDIO0_MASK (1 << CLOCK_GATING_BIT_SDIO0)
  41 +#define CLOCK_GATING_SDIO1_MASK (1 << CLOCK_GATING_BIT_SDIO1)
  42 +#define CLOCK_GATING_NAND_MASK (1 << CLOCK_GATING_BIT_NAND)
  43 +#define CLOCK_GATING_CAMERA_MASK (1 << CLOCK_GATING_BIT_CAMERA)
  44 +#define CLOCK_GATING_I2S0_MASK (1 << CLOCK_GATING_BIT_I2S0)
  45 +#define CLOCK_GATING_I2S1_MASK (1 << CLOCK_GATING_BIT_I2S1)
  46 +#define CLOCK_GATING_CRYPTO_MASK (1 << CLOCK_GATING_BIT_CRYPTO)
  47 +#define CLOCK_GATING_AC97_MASK (1 << CLOCK_GATING_BIT_AC97)
  48 +#define CLOCK_GATING_PDMA_MASK (1 << CLOCK_GATING_BIT_PDMA)
  49 +#define CLOCK_GATING_XOR0_MASK (1 << CLOCK_GATING_BIT_XOR0)
  50 +#define CLOCK_GATING_XOR1_MASK (1 << CLOCK_GATING_BIT_XOR1)
  51 +#define CLOCK_GATING_GIGA_PHY_MASK (1 << CLOCK_GATING_BIT_GIGA_PHY)
34 52  
35 53 #define PMU_INTERRUPT_CAUSE (DOVE_PMU_VIRT_BASE + 0x50)
36 54 #define PMU_INTERRUPT_MASK (DOVE_PMU_VIRT_BASE + 0x54)