Commit 5aef1ff2397d021f93d874b57dff032fdfac73de

Authored by Shengjiu Wang
Committed by Mark Brown
1 parent da3f23fde9

ASoC: fsl_sai: Fix value of FSL_SAI_CR1_RFW_MASK

The fifo_depth is 64 on i.MX8QM/i.MX8QXP, 128 on i.MX8MQ, 16 on
i.MX7ULP.

Original FSL_SAI_CR1_RFW_MASK value 0x1F is not suitable for
these platform, the FIFO watermark mask should be updated
according to the fifo_depth.

Fixes: a860fac42097 ("ASoC: fsl_sai: Add support for imx7ulp/imx8mq")
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Link: https://lore.kernel.org/r/1596176895-28724-1-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>

Showing 2 changed files with 4 additions and 3 deletions Side-by-side Diff

sound/soc/fsl/fsl_sai.c
... ... @@ -680,10 +680,11 @@
680 680 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
681 681  
682 682 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs),
683   - FSL_SAI_CR1_RFW_MASK,
  683 + FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
684 684 sai->soc_data->fifo_depth - FSL_SAI_MAXBURST_TX);
685 685 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs),
686   - FSL_SAI_CR1_RFW_MASK, FSL_SAI_MAXBURST_RX - 1);
  686 + FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
  687 + FSL_SAI_MAXBURST_RX - 1);
687 688  
688 689 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
689 690 &sai->dma_params_rx);
sound/soc/fsl/fsl_sai.h
... ... @@ -94,7 +94,7 @@
94 94 #define FSL_SAI_CSR_FRDE BIT(0)
95 95  
96 96 /* SAI Transmit and Receive Configuration 1 Register */
97   -#define FSL_SAI_CR1_RFW_MASK 0x1f
  97 +#define FSL_SAI_CR1_RFW_MASK(x) ((x) - 1)
98 98  
99 99 /* SAI Transmit and Receive Configuration 2 Register */
100 100 #define FSL_SAI_CR2_SYNC BIT(30)