bcma: unify naming schema for clock functions

Signed-off-by: John W. Linville <linville@tuxdriver.com>

bcma: unify naming schema for clock functions
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Rafał Miłecki · John W. Linville
1 parent 576d28a7c7
Showing 4 changed files with 29 additions and 26 deletions Side-by-side Diff
drivers/bcma/bcma_private.h
drivers/bcma/driver_chipcommon.c
drivers/bcma/driver_chipcommon_pmu.c
drivers/bcma/driver_mips.c
@@ -48,8 +48,8 @@
 #endif /* CONFIG_BCMA_DRIVER_MIPS */
  
 /* driver_chipcommon_pmu.c */
-u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
-u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
+u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
+u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
  
 #ifdef CONFIG_BCMA_SFLASH
 /* driver_chipcommon_sflash.c */
@@ -25,10 +25,10 @@
 	return value;
 }
  
-static u32 bcma_chipco_alp_clock(struct bcma_drv_cc *cc)
+static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
 {
 	if (cc->capabilities & BCMA_CC_CAP_PMU)
-		return bcma_pmu_alp_clock(cc);
+		return bcma_pmu_get_alp_clock(cc);
  
 	return 20000000;
 }
  
@@ -79,12 +79,12 @@
 	if (cc->capabilities & BCMA_CC_CAP_PMU) {
 		if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
 			/* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */
-			return bcma_chipco_alp_clock(cc) / 4000;
+			return bcma_chipco_get_alp_clock(cc) / 4000;
 		else
 			/* based on 32KHz ILP clock */
 			return 32;
 	} else {
-		return bcma_chipco_alp_clock(cc) / 1000;
+		return bcma_chipco_get_alp_clock(cc) / 1000;
 	}
 }
  
@@ -236,7 +236,7 @@
 	struct bcma_serial_port *ports = cc->serial_ports;
  
 	if (ccrev >= 11 && ccrev != 15) {
-		baud_base = bcma_chipco_alp_clock(cc);
+		baud_base = bcma_chipco_get_alp_clock(cc);
 		if (ccrev >= 21) {
 			/* Turn off UART clock before switching clocksource. */
 			bcma_cc_write32(cc, BCMA_CC_CORECTL,
@@ -168,7 +168,7 @@
 	bcma_pmu_workarounds(cc);
 }
  
-u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
+u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
 {
 	struct bcma_bus *bus = cc->core->bus;
  
@@ -196,7 +196,7 @@
 /* Find the output of the "m" pll divider given pll controls that start with
  * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
  */
-static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
+static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
 {
 	u32 tmp, div, ndiv, p1, p2, fc;
 	struct bcma_bus *bus = cc->core->bus;
  
@@ -225,14 +225,14 @@
 	ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
  
 	/* Do calculation in Mhz */
-	fc = bcma_pmu_alp_clock(cc) / 1000000;
+	fc = bcma_pmu_get_alp_clock(cc) / 1000000;
 	fc = (p1 * ndiv * fc) / p2;
  
 	/* Return clock in Hertz */
 	return (fc / div) * 1000000;
 }
  
-static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
+static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
 {
 	u32 tmp, ndiv, p1div, p2div;
 	u32 clock;
@@ -263,7 +263,7 @@
 }
  
 /* query bus clock frequency for PMU-enabled chipcommon */
-static u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
+static u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
 {
 	struct bcma_bus *bus = cc->core->bus;
  
  
  
  
  
  
  
  
@@ -271,40 +271,42 @@
 	case BCMA_CHIP_ID_BCM4716:
 	case BCMA_CHIP_ID_BCM4748:
 	case BCMA_CHIP_ID_BCM47162:
-		return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
-				      BCMA_CC_PMU5_MAINPLL_SSB);
+		return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
+					  BCMA_CC_PMU5_MAINPLL_SSB);
 	case BCMA_CHIP_ID_BCM5356:
-		return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
-				      BCMA_CC_PMU5_MAINPLL_SSB);
+		return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
+					  BCMA_CC_PMU5_MAINPLL_SSB);
 	case BCMA_CHIP_ID_BCM5357:
 	case BCMA_CHIP_ID_BCM4749:
-		return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
-				      BCMA_CC_PMU5_MAINPLL_SSB);
+		return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
+					  BCMA_CC_PMU5_MAINPLL_SSB);
 	case BCMA_CHIP_ID_BCM4706:
-		return bcma_pmu_clock_bcm4706(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
-					      BCMA_CC_PMU5_MAINPLL_SSB);
+		return bcma_pmu_pll_clock_bcm4706(cc,
+						  BCMA_CC_PMU4706_MAINPLL_PLL0,
+						  BCMA_CC_PMU5_MAINPLL_SSB);
 	case BCMA_CHIP_ID_BCM53572:
 		return 75000000;
 	default:
-		bcma_warn(bus, "No backplane clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
+		bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
 			  bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
 	}
 	return BCMA_CC_PMU_HT_CLOCK;
 }
  
 /* query cpu clock frequency for PMU-enabled chipcommon */
-u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
+u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
 {
 	struct bcma_bus *bus = cc->core->bus;
  
 	if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
 		return 300000000;
  
+	/* New PMUs can have different clock for bus and CPU */
 	if (cc->pmu.rev >= 5) {
 		u32 pll;
 		switch (bus->chipinfo.id) {
 		case BCMA_CHIP_ID_BCM4706:
-			return bcma_pmu_clock_bcm4706(cc,
+			return bcma_pmu_pll_clock_bcm4706(cc,
 						BCMA_CC_PMU4706_MAINPLL_PLL0,
 						BCMA_CC_PMU5_MAINPLL_CPU);
 		case BCMA_CHIP_ID_BCM5356:
  
@@ -319,10 +321,11 @@
 			break;
 		}
  
-		return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
+		return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
 	}
  
-	return bcma_pmu_get_clockcontrol(cc);
+	/* On old PMUs CPU has the same clock as the bus */
+	return bcma_pmu_get_bus_clock(cc);
 }
  
 static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
@@ -171,7 +171,7 @@
 	struct bcma_bus *bus = mcore->core->bus;
  
 	if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
-		return bcma_pmu_get_clockcpu(&bus->drv_cc);
+		return bcma_pmu_get_cpu_clock(&bus->drv_cc);
  
 	bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
 	return 0;
...	...	@@ -48,8 +48,8 @@
48	48	#endif /* CONFIG_BCMA_DRIVER_MIPS */
49	49
50	50	/* driver_chipcommon_pmu.c */
51		-u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
52		-u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
	51	+u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
	52	+u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
53	53
54	54	#ifdef CONFIG_BCMA_SFLASH
55	55	/* driver_chipcommon_sflash.c */
...	...	@@ -25,10 +25,10 @@
25	25	return value;
26	26	}
27	27
28		-static u32 bcma_chipco_alp_clock(struct bcma_drv_cc *cc)
	28	+static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
29	29	{
30	30	if (cc->capabilities & BCMA_CC_CAP_PMU)
31		- return bcma_pmu_alp_clock(cc);
	31	+ return bcma_pmu_get_alp_clock(cc);
32	32
33	33	return 20000000;
34	34	}
35	35
...	...	@@ -79,12 +79,12 @@
79	79	if (cc->capabilities & BCMA_CC_CAP_PMU) {
80	80	if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
81	81	/* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */
82		- return bcma_chipco_alp_clock(cc) / 4000;
	82	+ return bcma_chipco_get_alp_clock(cc) / 4000;
83	83	else
84	84	/* based on 32KHz ILP clock */
85	85	return 32;
86	86	} else {
87		- return bcma_chipco_alp_clock(cc) / 1000;
	87	+ return bcma_chipco_get_alp_clock(cc) / 1000;
88	88	}
89	89	}
90	90
...	...	@@ -236,7 +236,7 @@
236	236	struct bcma_serial_port *ports = cc->serial_ports;
237	237
238	238	if (ccrev >= 11 && ccrev != 15) {
239		- baud_base = bcma_chipco_alp_clock(cc);
	239	+ baud_base = bcma_chipco_get_alp_clock(cc);
240	240	if (ccrev >= 21) {
241	241	/* Turn off UART clock before switching clocksource. */
242	242	bcma_cc_write32(cc, BCMA_CC_CORECTL,
...	...	@@ -168,7 +168,7 @@
168	168	bcma_pmu_workarounds(cc);
169	169	}
170	170
171		-u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
	171	+u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
172	172	{
173	173	struct bcma_bus *bus = cc->core->bus;
174	174
...	...	@@ -196,7 +196,7 @@
196	196	/* Find the output of the "m" pll divider given pll controls that start with
197	197	* pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
198	198	*/
199		-static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
	199	+static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
200	200	{
201	201	u32 tmp, div, ndiv, p1, p2, fc;
202	202	struct bcma_bus *bus = cc->core->bus;
203	203
...	...	@@ -225,14 +225,14 @@
225	225	ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
226	226
227	227	/* Do calculation in Mhz */
228		- fc = bcma_pmu_alp_clock(cc) / 1000000;
	228	+ fc = bcma_pmu_get_alp_clock(cc) / 1000000;
229	229	fc = (p1 * ndiv * fc) / p2;
230	230
231	231	/* Return clock in Hertz */
232	232	return (fc / div) * 1000000;
233	233	}
234	234
235		-static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
	235	+static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
236	236	{
237	237	u32 tmp, ndiv, p1div, p2div;
238	238	u32 clock;
...	...	@@ -263,7 +263,7 @@
263	263	}
264	264
265	265	/* query bus clock frequency for PMU-enabled chipcommon */
266		-static u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
	266	+static u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
267	267	{
268	268	struct bcma_bus *bus = cc->core->bus;
269	269
270	270
271	271
272	272
273	273
274	274
275	275
276	276
...	...	@@ -271,40 +271,42 @@
271	271	case BCMA_CHIP_ID_BCM4716:
272	272	case BCMA_CHIP_ID_BCM4748:
273	273	case BCMA_CHIP_ID_BCM47162:
274		- return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
275		- BCMA_CC_PMU5_MAINPLL_SSB);
	274	+ return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
	275	+ BCMA_CC_PMU5_MAINPLL_SSB);
276	276	case BCMA_CHIP_ID_BCM5356:
277		- return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
278		- BCMA_CC_PMU5_MAINPLL_SSB);
	277	+ return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
	278	+ BCMA_CC_PMU5_MAINPLL_SSB);
279	279	case BCMA_CHIP_ID_BCM5357:
280	280	case BCMA_CHIP_ID_BCM4749:
281		- return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
282		- BCMA_CC_PMU5_MAINPLL_SSB);
	281	+ return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
	282	+ BCMA_CC_PMU5_MAINPLL_SSB);
283	283	case BCMA_CHIP_ID_BCM4706:
284		- return bcma_pmu_clock_bcm4706(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
285		- BCMA_CC_PMU5_MAINPLL_SSB);
	284	+ return bcma_pmu_pll_clock_bcm4706(cc,
	285	+ BCMA_CC_PMU4706_MAINPLL_PLL0,
	286	+ BCMA_CC_PMU5_MAINPLL_SSB);
286	287	case BCMA_CHIP_ID_BCM53572:
287	288	return 75000000;
288	289	default:
289		- bcma_warn(bus, "No backplane clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
	290	+ bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
290	291	bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
291	292	}
292	293	return BCMA_CC_PMU_HT_CLOCK;
293	294	}
294	295
295	296	/* query cpu clock frequency for PMU-enabled chipcommon */
296		-u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
	297	+u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
297	298	{
298	299	struct bcma_bus *bus = cc->core->bus;
299	300
300	301	if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
301	302	return 300000000;
302	303
	304	+ /* New PMUs can have different clock for bus and CPU */
303	305	if (cc->pmu.rev >= 5) {
304	306	u32 pll;
305	307	switch (bus->chipinfo.id) {
306	308	case BCMA_CHIP_ID_BCM4706:
307		- return bcma_pmu_clock_bcm4706(cc,
	309	+ return bcma_pmu_pll_clock_bcm4706(cc,
308	310	BCMA_CC_PMU4706_MAINPLL_PLL0,
309	311	BCMA_CC_PMU5_MAINPLL_CPU);
310	312	case BCMA_CHIP_ID_BCM5356:
311	313
...	...	@@ -319,10 +321,11 @@
319	321	break;
320	322	}
321	323
322		- return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
	324	+ return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
323	325	}
324	326
325		- return bcma_pmu_get_clockcontrol(cc);
	327	+ /* On old PMUs CPU has the same clock as the bus */
	328	+ return bcma_pmu_get_bus_clock(cc);
326	329	}
327	330
328	331	static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
...	...	@@ -171,7 +171,7 @@
171	171	struct bcma_bus *bus = mcore->core->bus;
172	172
173	173	if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
174		- return bcma_pmu_get_clockcpu(&bus->drv_cc);
	174	+ return bcma_pmu_get_cpu_clock(&bus->drv_cc);
175	175
176	176	bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
177	177	return 0;