Eric Lee / smarc-fsl-linux-kernel

Download as
Browse Code »

Commit 67edf354faaf93156646e741483b2313bc756c0f

Authored by Rafał Miłecki
Committed by Kalle Valo
1 parent 0c06f5d43e

bcma: use _PMU_ in all names of PMU registers 

PMU (Power Management Unit) seems to be a separated piece of hardware,
just accessed using ChipCommon core registers. In recent Broadcom
chipsets PMU is not bounded to CC but available as separated core.

To make code cleaner & easier to review (for a correct R/W access) use
clearer names.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>

Showing 3 changed files with 33 additions and 33 deletions Side-by-side Diff

drivers/bcma/driver_chipcommon_pmu.c
Diff comments   View file @ 67edf35
... ... @@ -15,44 +15,44 @@
15 15  
16 16 u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
17 17 {
18   - bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
19   - bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
20   - return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
  18 + bcma_cc_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
  19 + bcma_cc_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
  20 + return bcma_cc_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
21 21 }
22 22 EXPORT_SYMBOL_GPL(bcma_chipco_pll_read);
23 23  
24 24 void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
25 25 {
26   - bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
27   - bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
28   - bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
  26 + bcma_cc_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
  27 + bcma_cc_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
  28 + bcma_cc_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, value);
29 29 }
30 30 EXPORT_SYMBOL_GPL(bcma_chipco_pll_write);
31 31  
32 32 void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
33 33 u32 set)
34 34 {
35   - bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
36   - bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
37   - bcma_cc_maskset32(cc, BCMA_CC_PLLCTL_DATA, mask, set);
  35 + bcma_cc_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
  36 + bcma_cc_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
  37 + bcma_cc_maskset32(cc, BCMA_CC_PMU_PLLCTL_DATA, mask, set);
38 38 }
39 39 EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset);
40 40  
41 41 void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
42 42 u32 offset, u32 mask, u32 set)
43 43 {
44   - bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset);
45   - bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
46   - bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL_DATA, mask, set);
  44 + bcma_cc_write32(cc, BCMA_CC_PMU_CHIPCTL_ADDR, offset);
  45 + bcma_cc_read32(cc, BCMA_CC_PMU_CHIPCTL_ADDR);
  46 + bcma_cc_maskset32(cc, BCMA_CC_PMU_CHIPCTL_DATA, mask, set);
47 47 }
48 48 EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset);
49 49  
50 50 void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
51 51 u32 set)
52 52 {
53   - bcma_cc_write32(cc, BCMA_CC_REGCTL_ADDR, offset);
54   - bcma_cc_read32(cc, BCMA_CC_REGCTL_ADDR);
55   - bcma_cc_maskset32(cc, BCMA_CC_REGCTL_DATA, mask, set);
  53 + bcma_cc_write32(cc, BCMA_CC_PMU_REGCTL_ADDR, offset);
  54 + bcma_cc_read32(cc, BCMA_CC_PMU_REGCTL_ADDR);
  55 + bcma_cc_maskset32(cc, BCMA_CC_PMU_REGCTL_DATA, mask, set);
56 56 }
57 57 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
58 58  
... ... @@ -472,8 +472,8 @@
472 472 static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
473 473 u32 value)
474 474 {
475   - bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
476   - bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
  475 + bcma_cc_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
  476 + bcma_cc_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, value);
477 477 }
478 478  
479 479 void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
480 480  
481 481  
482 482  
483 483  
484 484  
... ... @@ -497,20 +497,20 @@
497 497 bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;
498 498  
499 499 /* RMW only the P1 divider */
500   - bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
  500 + bcma_cc_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR,
501 501 BCMA_CC_PMU_PLL_CTL0 + phypll_offset);
502   - tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
  502 + tmp = bcma_cc_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
503 503 tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK));
504 504 tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT);
505   - bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
  505 + bcma_cc_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, tmp);
506 506  
507 507 /* RMW only the int feedback divider */
508   - bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
  508 + bcma_cc_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR,
509 509 BCMA_CC_PMU_PLL_CTL2 + phypll_offset);
510   - tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
  510 + tmp = bcma_cc_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
511 511 tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK);
512 512 tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
513   - bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
  513 + bcma_cc_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, tmp);
514 514  
515 515 tmp = BCMA_CC_PMU_CTL_PLL_UPD;
516 516 break;
drivers/net/wireless/broadcom/b43/main.c
Diff comments   View file @ 67edf35
... ... @@ -1215,10 +1215,10 @@
1215 1215 case B43_BUS_BCMA:
1216 1216 bcma_cc = &dev->dev->bdev->bus->drv_cc;
1217 1217  
1218   - bcma_cc_write32(bcma_cc, BCMA_CC_CHIPCTL_ADDR, 0);
1219   - bcma_cc_mask32(bcma_cc, BCMA_CC_CHIPCTL_DATA, ~0x4);
1220   - bcma_cc_set32(bcma_cc, BCMA_CC_CHIPCTL_DATA, 0x4);
1221   - bcma_cc_mask32(bcma_cc, BCMA_CC_CHIPCTL_DATA, ~0x4);
  1218 + bcma_cc_write32(bcma_cc, BCMA_CC_PMU_CHIPCTL_ADDR, 0);
  1219 + bcma_cc_mask32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, ~0x4);
  1220 + bcma_cc_set32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, 0x4);
  1221 + bcma_cc_mask32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, ~0x4);
1222 1222 break;
1223 1223 #endif
1224 1224 #ifdef CONFIG_B43_SSB
include/linux/bcma/bcma_driver_chipcommon.h
Diff comments   View file @ 67edf35
... ... @@ -351,12 +351,12 @@
351 351 #define BCMA_CC_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */
352 352 #define BCMA_CC_PMU_RES_REQT 0x0644 /* PMU res req timer */
353 353 #define BCMA_CC_PMU_RES_REQM 0x0648 /* PMU res req mask */
354   -#define BCMA_CC_CHIPCTL_ADDR 0x0650
355   -#define BCMA_CC_CHIPCTL_DATA 0x0654
356   -#define BCMA_CC_REGCTL_ADDR 0x0658
357   -#define BCMA_CC_REGCTL_DATA 0x065C
358   -#define BCMA_CC_PLLCTL_ADDR 0x0660
359   -#define BCMA_CC_PLLCTL_DATA 0x0664
  354 +#define BCMA_CC_PMU_CHIPCTL_ADDR 0x0650
  355 +#define BCMA_CC_PMU_CHIPCTL_DATA 0x0654
  356 +#define BCMA_CC_PMU_REGCTL_ADDR 0x0658
  357 +#define BCMA_CC_PMU_REGCTL_DATA 0x065C
  358 +#define BCMA_CC_PMU_PLLCTL_ADDR 0x0660
  359 +#define BCMA_CC_PMU_PLLCTL_DATA 0x0664
360 360 #define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */
361 361 #define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */
362 362 #define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF