Commit 69e60903aaf5aa56548656897d2b0fbe4431a7fe
1 parent
e28bb32b6d
bus: ti-sysc: Fix wrong offset for display subsystem reset quirk
Commit 7324a7a0d5e2 ("bus: ti-sysc: Implement display subsystem reset quirk") added support for DSS reset, but is using dispc offset also for DSS also registers as reported by Tomi Valkeinen <tomi.valkeinen@ti.com>. Also, we're not using dispc_offset for dispc IRQSTATUS register so let's fix that too. Fixes: 7324a7a0d5e2 ("bus: ti-sysc: Implement display subsystem reset quirk") Reported-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Showing 1 changed file with 4 additions and 4 deletions Side-by-side Diff
drivers/bus/ti-sysc.c
| ... | ... | @@ -1566,7 +1566,7 @@ |
| 1566 | 1566 | return; |
| 1567 | 1567 | |
| 1568 | 1568 | /* Clear IRQSTATUS */ |
| 1569 | - sysc_write(ddata, 0x1000 + 0x18, irq_mask); | |
| 1569 | + sysc_write(ddata, dispc_offset + 0x18, irq_mask); | |
| 1570 | 1570 | |
| 1571 | 1571 | /* Disable outputs */ |
| 1572 | 1572 | val = sysc_quirk_dispc(ddata, dispc_offset, true); |
| 1573 | 1573 | |
| 1574 | 1574 | |
| ... | ... | @@ -1580,14 +1580,14 @@ |
| 1580 | 1580 | |
| 1581 | 1581 | if (sysc_soc->soc == SOC_3430) { |
| 1582 | 1582 | /* Clear DSS_SDI_CONTROL */ |
| 1583 | - sysc_write(ddata, dispc_offset + 0x44, 0); | |
| 1583 | + sysc_write(ddata, 0x44, 0); | |
| 1584 | 1584 | |
| 1585 | 1585 | /* Clear DSS_PLL_CONTROL */ |
| 1586 | - sysc_write(ddata, dispc_offset + 0x48, 0); | |
| 1586 | + sysc_write(ddata, 0x48, 0); | |
| 1587 | 1587 | } |
| 1588 | 1588 | |
| 1589 | 1589 | /* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */ |
| 1590 | - sysc_write(ddata, dispc_offset + 0x40, 0); | |
| 1590 | + sysc_write(ddata, 0x40, 0); | |
| 1591 | 1591 | } |
| 1592 | 1592 | |
| 1593 | 1593 | /* 1-wire needs module's internal clocks enabled for reset */ |