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Commit 74c917076ab96f648b96a39ec1ce7a8a7ed361f5

Authored by Laurent Pinchart
Committed by Simon Horman
1 parent 7d6a399cf7

ARM: shmobile: r8a7791: Remove legacy code 

All r8a7791 boards are now used with multiplatform kernels only. We can
remove all the unused r8a7791 legacy device and clock registration code.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Showing 5 changed files with 1 additions and 530 deletions Side-by-side Diff

arch/arm/mach-shmobile/Kconfig
Diff comments   View file @ 74c9170
... ... @@ -145,14 +145,6 @@
145 145 select MIGHT_HAVE_PCI
146 146 select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
147 147  
148   -config ARCH_R8A7791
149   - bool "R-Car M2-W (R8A77910)"
150   - select ARCH_RCAR_GEN2
151   - select ARCH_WANT_OPTIONAL_GPIOLIB
152   - select ARM_GIC
153   - select MIGHT_HAVE_PCI
154   - select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
155   -
156 148 comment "Renesas ARM SoCs Board Type"
157 149  
158 150 config MACH_APE6EVM
arch/arm/mach-shmobile/Makefile
Diff comments   View file @ 74c9170
... ... @@ -28,7 +28,6 @@
28 28 obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o
29 29 obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o
30 30 obj-$(CONFIG_ARCH_R8A7790) += clock-r8a7790.o
31   -obj-$(CONFIG_ARCH_R8A7791) += clock-r8a7791.o
32 31 endif
33 32  
34 33 # CPU reset vector handling objects
arch/arm/mach-shmobile/clock-r8a7791.c
View file @ 74c9170
1   -/*
2   - * r8a7791 clock framework support
3   - *
4   - * Copyright (C) 2013 Renesas Electronics Corporation
5   - * Copyright (C) 2013 Renesas Solutions Corp.
6   - * Copyright (C) 2013 Magnus Damm
7   - *
8   - * This program is free software; you can redistribute it and/or modify
9   - * it under the terms of the GNU General Public License as published by
10   - * the Free Software Foundation; version 2 of the License.
11   - *
12   - * This program is distributed in the hope that it will be useful,
13   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
14   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15   - * GNU General Public License for more details.
16   - */
17   -#include <linux/init.h>
18   -#include <linux/io.h>
19   -#include <linux/kernel.h>
20   -#include <linux/sh_clk.h>
21   -#include <linux/clkdev.h>
22   -#include "clock.h"
23   -#include "common.h"
24   -#include "rcar-gen2.h"
25   -
26   -/*
27   - * MD EXTAL PLL0 PLL1 PLL3
28   - * 14 13 19 (MHz) *1 *1
29   - *---------------------------------------------------
30   - * 0 0 0 15 x 1 x172/2 x208/2 x106
31   - * 0 0 1 15 x 1 x172/2 x208/2 x88
32   - * 0 1 0 20 x 1 x130/2 x156/2 x80
33   - * 0 1 1 20 x 1 x130/2 x156/2 x66
34   - * 1 0 0 26 / 2 x200/2 x240/2 x122
35   - * 1 0 1 26 / 2 x200/2 x240/2 x102
36   - * 1 1 0 30 / 2 x172/2 x208/2 x106
37   - * 1 1 1 30 / 2 x172/2 x208/2 x88
38   - *
39   - * *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
40   - * see "p1 / 2" on R8A7791_CLOCK_ROOT() below
41   - */
42   -
43   -#define CPG_BASE 0xe6150000
44   -#define CPG_LEN 0x1000
45   -
46   -#define SMSTPCR0 0xE6150130
47   -#define SMSTPCR1 0xE6150134
48   -#define SMSTPCR2 0xe6150138
49   -#define SMSTPCR3 0xE615013C
50   -#define SMSTPCR5 0xE6150144
51   -#define SMSTPCR7 0xe615014c
52   -#define SMSTPCR8 0xE6150990
53   -#define SMSTPCR9 0xE6150994
54   -#define SMSTPCR10 0xE6150998
55   -#define SMSTPCR11 0xE615099C
56   -
57   -#define MSTPSR1 IOMEM(0xe6150038)
58   -#define MSTPSR2 IOMEM(0xe6150040)
59   -#define MSTPSR3 IOMEM(0xe6150048)
60   -#define MSTPSR5 IOMEM(0xe615003c)
61   -#define MSTPSR7 IOMEM(0xe61501c4)
62   -#define MSTPSR8 IOMEM(0xe61509a0)
63   -#define MSTPSR9 IOMEM(0xe61509a4)
64   -#define MSTPSR11 IOMEM(0xe61509ac)
65   -
66   -#define SDCKCR 0xE6150074
67   -#define SD1CKCR 0xE6150078
68   -#define SD2CKCR 0xE615026c
69   -#define MMC0CKCR 0xE6150240
70   -#define MMC1CKCR 0xE6150244
71   -#define SSPCKCR 0xE6150248
72   -#define SSPRSCKCR 0xE615024C
73   -
74   -static struct clk_mapping cpg_mapping = {
75   - .phys = CPG_BASE,
76   - .len = CPG_LEN,
77   -};
78   -
79   -static struct clk extal_clk = {
80   - /* .rate will be updated on r8a7791_clock_init() */
81   - .mapping = &cpg_mapping,
82   -};
83   -
84   -static struct sh_clk_ops followparent_clk_ops = {
85   - .recalc = followparent_recalc,
86   -};
87   -
88   -static struct clk main_clk = {
89   - /* .parent will be set r8a73a4_clock_init */
90   - .ops = &followparent_clk_ops,
91   -};
92   -
93   -/*
94   - * clock ratio of these clock will be updated
95   - * on r8a7791_clock_init()
96   - */
97   -SH_FIXED_RATIO_CLK_SET(pll1_clk, main_clk, 1, 1);
98   -SH_FIXED_RATIO_CLK_SET(pll3_clk, main_clk, 1, 1);
99   -SH_FIXED_RATIO_CLK_SET(qspi_clk, pll1_clk, 1, 1);
100   -
101   -/* fixed ratio clock */
102   -SH_FIXED_RATIO_CLK_SET(extal_div2_clk, extal_clk, 1, 2);
103   -SH_FIXED_RATIO_CLK_SET(cp_clk, extal_clk, 1, 2);
104   -
105   -SH_FIXED_RATIO_CLK_SET(pll1_div2_clk, pll1_clk, 1, 2);
106   -SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12);
107   -SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24);
108   -SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024));
109   -SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15);
110   -SH_FIXED_RATIO_CLK_SET(zg_clk, pll1_clk, 1, 3);
111   -SH_FIXED_RATIO_CLK_SET(zx_clk, pll1_clk, 1, 3);
112   -SH_FIXED_RATIO_CLK_SET(zs_clk, pll1_clk, 1, 6);
113   -
114   -static struct clk *main_clks[] = {
115   - &extal_clk,
116   - &extal_div2_clk,
117   - &main_clk,
118   - &pll1_clk,
119   - &pll1_div2_clk,
120   - &pll3_clk,
121   - &hp_clk,
122   - &p_clk,
123   - &qspi_clk,
124   - &rclk_clk,
125   - &mp_clk,
126   - &cp_clk,
127   - &zg_clk,
128   - &zx_clk,
129   - &zs_clk,
130   -};
131   -
132   -/* SDHI (DIV4) clock */
133   -static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 };
134   -
135   -static struct clk_div_mult_table div4_div_mult_table = {
136   - .divisors = divisors,
137   - .nr_divisors = ARRAY_SIZE(divisors),
138   -};
139   -
140   -static struct clk_div4_table div4_table = {
141   - .div_mult_table = &div4_div_mult_table,
142   -};
143   -
144   -enum {
145   - DIV4_SDH, DIV4_SD0,
146   - DIV4_NR
147   -};
148   -
149   -static struct clk div4_clks[DIV4_NR] = {
150   - [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
151   - [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1df0, CLK_ENABLE_ON_INIT),
152   -};
153   -
154   -/* DIV6 clocks */
155   -enum {
156   - DIV6_SD1, DIV6_SD2,
157   - DIV6_NR
158   -};
159   -
160   -static struct clk div6_clks[DIV6_NR] = {
161   - [DIV6_SD1] = SH_CLK_DIV6(&pll1_div2_clk, SD1CKCR, 0),
162   - [DIV6_SD2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
163   -};
164   -
165   -/* MSTP */
166   -enum {
167   - MSTP1108, MSTP1107, MSTP1106,
168   - MSTP931, MSTP930, MSTP929, MSTP928, MSTP927, MSTP925,
169   - MSTP917,
170   - MSTP815, MSTP814,
171   - MSTP813,
172   - MSTP811, MSTP810, MSTP809,
173   - MSTP726, MSTP724, MSTP723, MSTP721, MSTP720,
174   - MSTP719, MSTP718, MSTP715, MSTP714,
175   - MSTP522,
176   - MSTP314, MSTP312, MSTP311,
177   - MSTP216, MSTP207, MSTP206,
178   - MSTP204, MSTP203, MSTP202,
179   - MSTP124,
180   - MSTP_NR
181   -};
182   -
183   -static struct clk mstp_clks[MSTP_NR] = {
184   - [MSTP1108] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 8, MSTPSR11, 0), /* SCIFA5 */
185   - [MSTP1107] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 7, MSTPSR11, 0), /* SCIFA4 */
186   - [MSTP1106] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 6, MSTPSR11, 0), /* SCIFA3 */
187   - [MSTP931] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */
188   - [MSTP930] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */
189   - [MSTP929] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
190   - [MSTP928] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
191   - [MSTP927] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 27, MSTPSR9, 0), /* I2C4 */
192   - [MSTP925] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 25, MSTPSR9, 0), /* I2C5 */
193   - [MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */
194   - [MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */
195   - [MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */
196   - [MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */
197   - [MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0), /* VIN0 */
198   - [MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8, 0), /* VIN1 */
199   - [MSTP809] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 9, MSTPSR8, 0), /* VIN2 */
200   - [MSTP726] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 26, MSTPSR7, 0), /* LVDS0 */
201   - [MSTP724] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 24, MSTPSR7, 0), /* DU0 */
202   - [MSTP723] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 23, MSTPSR7, 0), /* DU1 */
203   - [MSTP721] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 21, MSTPSR7, 0), /* SCIF0 */
204   - [MSTP720] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 20, MSTPSR7, 0), /* SCIF1 */
205   - [MSTP719] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 19, MSTPSR7, 0), /* SCIF2 */
206   - [MSTP718] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 18, MSTPSR7, 0), /* SCIF3 */
207   - [MSTP715] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 15, MSTPSR7, 0), /* SCIF4 */
208   - [MSTP714] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 14, MSTPSR7, 0), /* SCIF5 */
209   - [MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */
210   - [MSTP314] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD0], SMSTPCR3, 14, MSTPSR3, 0), /* SDHI0 */
211   - [MSTP312] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD1], SMSTPCR3, 12, MSTPSR3, 0), /* SDHI1 */
212   - [MSTP311] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD2], SMSTPCR3, 11, MSTPSR3, 0), /* SDHI2 */
213   - [MSTP216] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 16, MSTPSR2, 0), /* SCIFB2 */
214   - [MSTP207] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 7, MSTPSR2, 0), /* SCIFB1 */
215   - [MSTP206] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 6, MSTPSR2, 0), /* SCIFB0 */
216   - [MSTP204] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 4, MSTPSR2, 0), /* SCIFA0 */
217   - [MSTP203] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 3, MSTPSR2, 0), /* SCIFA1 */
218   - [MSTP202] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 2, MSTPSR2, 0), /* SCIFA2 */
219   - [MSTP124] = SH_CLK_MSTP32_STS(&rclk_clk, SMSTPCR1, 24, MSTPSR1, 0), /* CMT0 */
220   -};
221   -
222   -static struct clk_lookup lookups[] = {
223   -
224   - /* main clocks */
225   - CLKDEV_CON_ID("extal", &extal_clk),
226   - CLKDEV_CON_ID("extal_div2", &extal_div2_clk),
227   - CLKDEV_CON_ID("main", &main_clk),
228   - CLKDEV_CON_ID("pll1", &pll1_clk),
229   - CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk),
230   - CLKDEV_CON_ID("pll3", &pll3_clk),
231   - CLKDEV_CON_ID("zg", &zg_clk),
232   - CLKDEV_CON_ID("zs", &zs_clk),
233   - CLKDEV_CON_ID("hp", &hp_clk),
234   - CLKDEV_CON_ID("p", &p_clk),
235   - CLKDEV_CON_ID("qspi", &qspi_clk),
236   - CLKDEV_CON_ID("rclk", &rclk_clk),
237   - CLKDEV_CON_ID("mp", &mp_clk),
238   - CLKDEV_CON_ID("cp", &cp_clk),
239   - CLKDEV_CON_ID("peripheral_clk", &hp_clk),
240   -
241   - /* MSTP */
242   - CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7791", &mstp_clks[MSTP726]),
243   - CLKDEV_ICK_ID("du.0", "rcar-du-r8a7791", &mstp_clks[MSTP724]),
244   - CLKDEV_ICK_ID("du.1", "rcar-du-r8a7791", &mstp_clks[MSTP723]),
245   - CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
246   - CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
247   - CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), /* SCIFB0 */
248   - CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]), /* SCIFB1 */
249   - CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), /* SCIFB2 */
250   - CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]), /* SCIFA2 */
251   - CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]), /* SCIF0 */
252   - CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), /* SCIF1 */
253   - CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP719]), /* SCIF2 */
254   - CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP718]), /* SCIF3 */
255   - CLKDEV_DEV_ID("sh-sci.10", &mstp_clks[MSTP715]), /* SCIF4 */
256   - CLKDEV_DEV_ID("sh-sci.11", &mstp_clks[MSTP714]), /* SCIF5 */
257   - CLKDEV_DEV_ID("sh-sci.12", &mstp_clks[MSTP1106]), /* SCIFA3 */
258   - CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1107]), /* SCIFA4 */
259   - CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1108]), /* SCIFA5 */
260   - CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
261   - CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP312]),
262   - CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]),
263   - CLKDEV_ICK_ID("fck", "sh-cmt-48-gen2.0", &mstp_clks[MSTP124]),
264   - CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
265   - CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
266   - CLKDEV_DEV_ID("i2c-rcar_gen2.0", &mstp_clks[MSTP931]),
267   - CLKDEV_DEV_ID("i2c-rcar_gen2.1", &mstp_clks[MSTP930]),
268   - CLKDEV_DEV_ID("i2c-rcar_gen2.2", &mstp_clks[MSTP929]),
269   - CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]),
270   - CLKDEV_DEV_ID("i2c-rcar_gen2.4", &mstp_clks[MSTP927]),
271   - CLKDEV_DEV_ID("i2c-rcar_gen2.5", &mstp_clks[MSTP925]),
272   - CLKDEV_DEV_ID("r8a7791-ether", &mstp_clks[MSTP813]), /* Ether */
273   - CLKDEV_DEV_ID("r8a7791-vin.0", &mstp_clks[MSTP811]),
274   - CLKDEV_DEV_ID("r8a7791-vin.1", &mstp_clks[MSTP810]),
275   - CLKDEV_DEV_ID("r8a7791-vin.2", &mstp_clks[MSTP809]),
276   - CLKDEV_DEV_ID("sata-r8a7791.0", &mstp_clks[MSTP815]),
277   - CLKDEV_DEV_ID("sata-r8a7791.1", &mstp_clks[MSTP814]),
278   -};
279   -
280   -#define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
281   - extal_clk.rate = e * 1000 * 1000; \
282   - main_clk.parent = m; \
283   - SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1); \
284   - if (mode & MD(19)) \
285   - SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1); \
286   - else \
287   - SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)
288   -
289   -
290   -void __init r8a7791_clock_init(void)
291   -{
292   - u32 mode = rcar_gen2_read_mode_pins();
293   - int k, ret = 0;
294   -
295   - switch (mode & (MD(14) | MD(13))) {
296   - case 0:
297   - R8A7791_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
298   - break;
299   - case MD(13):
300   - R8A7791_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
301   - break;
302   - case MD(14):
303   - R8A7791_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102);
304   - break;
305   - case MD(13) | MD(14):
306   - R8A7791_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88);
307   - break;
308   - }
309   -
310   - if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2))
311   - SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16);
312   - else
313   - SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20);
314   -
315   - for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
316   - ret = clk_register(main_clks[k]);
317   -
318   - if (!ret)
319   - ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
320   -
321   - if (!ret)
322   - ret = sh_clk_div6_register(div6_clks, DIV6_NR);
323   -
324   - if (!ret)
325   - ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
326   -
327   - clkdev_add_table(lookups, ARRAY_SIZE(lookups));
328   -
329   - if (!ret)
330   - shmobile_clk_init();
331   - else
332   - goto epanic;
333   -
334   - return;
335   -
336   -epanic:
337   - panic("failed to setup r8a7791 clocks\n");
338   -}
arch/arm/mach-shmobile/r8a7791.h
Diff comments   View file @ 74c9170
1 1 #ifndef __ASM_R8A7791_H__
2 2 #define __ASM_R8A7791_H__
3 3  
4   -void r8a7791_add_standard_devices(void);
5   -void r8a7791_clock_init(void);
6   -void r8a7791_pinmux_init(void);
7 4 void r8a7791_pm_init(void);
8 5 extern struct smp_operations r8a7791_smp_ops;
9 6  
arch/arm/mach-shmobile/setup-r8a7791.c
Diff comments   View file @ 74c9170
... ... @@ -15,192 +15,14 @@
15 15 * GNU General Public License for more details.
16 16 */
17 17  
18   -#include <linux/irq.h>
19   -#include <linux/kernel.h>
20   -#include <linux/of_platform.h>
21   -#include <linux/platform_data/gpio-rcar.h>
22   -#include <linux/platform_data/irq-renesas-irqc.h>
23   -#include <linux/serial_sci.h>
24   -#include <linux/sh_timer.h>
  18 +#include <linux/init.h>
25 19  
26 20 #include <asm/mach/arch.h>
27 21  
28 22 #include "common.h"
29   -#include "irqs.h"
30 23 #include "r8a7791.h"
31 24 #include "rcar-gen2.h"
32 25  
33   -static const struct resource pfc_resources[] __initconst = {
34   - DEFINE_RES_MEM(0xe6060000, 0x250),
35   -};
36   -
37   -#define r8a7791_register_pfc() \
38   - platform_device_register_simple("pfc-r8a7791", -1, pfc_resources, \
39   - ARRAY_SIZE(pfc_resources))
40   -
41   -#define R8A7791_GPIO(idx, base, nr) \
42   -static const struct resource r8a7791_gpio##idx##_resources[] __initconst = { \
43   - DEFINE_RES_MEM((base), 0x50), \
44   - DEFINE_RES_IRQ(gic_spi(4 + (idx))), \
45   -}; \
46   - \
47   -static const struct gpio_rcar_config \
48   -r8a7791_gpio##idx##_platform_data __initconst = { \
49   - .gpio_base = 32 * (idx), \
50   - .irq_base = 0, \
51   - .number_of_pins = (nr), \
52   - .pctl_name = "pfc-r8a7791", \
53   - .has_both_edge_trigger = 1, \
54   -}; \
55   -
56   -R8A7791_GPIO(0, 0xe6050000, 32);
57   -R8A7791_GPIO(1, 0xe6051000, 32);
58   -R8A7791_GPIO(2, 0xe6052000, 32);
59   -R8A7791_GPIO(3, 0xe6053000, 32);
60   -R8A7791_GPIO(4, 0xe6054000, 32);
61   -R8A7791_GPIO(5, 0xe6055000, 32);
62   -R8A7791_GPIO(6, 0xe6055400, 32);
63   -R8A7791_GPIO(7, 0xe6055800, 26);
64   -
65   -#define r8a7791_register_gpio(idx) \
66   - platform_device_register_resndata(NULL, "gpio_rcar", idx, \
67   - r8a7791_gpio##idx##_resources, \
68   - ARRAY_SIZE(r8a7791_gpio##idx##_resources), \
69   - &r8a7791_gpio##idx##_platform_data, \
70   - sizeof(r8a7791_gpio##idx##_platform_data))
71   -
72   -void __init r8a7791_pinmux_init(void)
73   -{
74   - r8a7791_register_pfc();
75   - r8a7791_register_gpio(0);
76   - r8a7791_register_gpio(1);
77   - r8a7791_register_gpio(2);
78   - r8a7791_register_gpio(3);
79   - r8a7791_register_gpio(4);
80   - r8a7791_register_gpio(5);
81   - r8a7791_register_gpio(6);
82   - r8a7791_register_gpio(7);
83   -}
84   -
85   -#define __R8A7791_SCIF(scif_type, index, baseaddr, irq) \
86   -static struct plat_sci_port scif##index##_platform_data = { \
87   - .type = scif_type, \
88   - .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
89   - .scscr = SCSCR_RE | SCSCR_TE, \
90   -}; \
91   - \
92   -static struct resource scif##index##_resources[] = { \
93   - DEFINE_RES_MEM(baseaddr, 0x100), \
94   - DEFINE_RES_IRQ(irq), \
95   -}
96   -
97   -#define R8A7791_SCIF(index, baseaddr, irq) \
98   - __R8A7791_SCIF(PORT_SCIF, index, baseaddr, irq)
99   -
100   -#define R8A7791_SCIFA(index, baseaddr, irq) \
101   - __R8A7791_SCIF(PORT_SCIFA, index, baseaddr, irq)
102   -
103   -#define R8A7791_SCIFB(index, baseaddr, irq) \
104   - __R8A7791_SCIF(PORT_SCIFB, index, baseaddr, irq)
105   -
106   -R8A7791_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
107   -R8A7791_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
108   -R8A7791_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
109   -R8A7791_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
110   -R8A7791_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
111   -R8A7791_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */
112   -R8A7791_SCIF(6, 0xe6e60000, gic_spi(152)); /* SCIF0 */
113   -R8A7791_SCIF(7, 0xe6e68000, gic_spi(153)); /* SCIF1 */
114   -R8A7791_SCIF(8, 0xe6e58000, gic_spi(22)); /* SCIF2 */
115   -R8A7791_SCIF(9, 0xe6ea8000, gic_spi(23)); /* SCIF3 */
116   -R8A7791_SCIF(10, 0xe6ee0000, gic_spi(24)); /* SCIF4 */
117   -R8A7791_SCIF(11, 0xe6ee8000, gic_spi(25)); /* SCIF5 */
118   -R8A7791_SCIFA(12, 0xe6c70000, gic_spi(29)); /* SCIFA3 */
119   -R8A7791_SCIFA(13, 0xe6c78000, gic_spi(30)); /* SCIFA4 */
120   -R8A7791_SCIFA(14, 0xe6c80000, gic_spi(31)); /* SCIFA5 */
121   -
122   -#define r8a7791_register_scif(index) \
123   - platform_device_register_resndata(NULL, "sh-sci", index, \
124   - scif##index##_resources, \
125   - ARRAY_SIZE(scif##index##_resources), \
126   - &scif##index##_platform_data, \
127   - sizeof(scif##index##_platform_data))
128   -
129   -static struct sh_timer_config cmt0_platform_data = {
130   - .channels_mask = 0x60,
131   -};
132   -
133   -static struct resource cmt0_resources[] = {
134   - DEFINE_RES_MEM(0xffca0000, 0x1004),
135   - DEFINE_RES_IRQ(gic_spi(142)),
136   -};
137   -
138   -#define r8a7791_register_cmt(idx) \
139   - platform_device_register_resndata(NULL, "sh-cmt-48-gen2", \
140   - idx, cmt##idx##_resources, \
141   - ARRAY_SIZE(cmt##idx##_resources), \
142   - &cmt##idx##_platform_data, \
143   - sizeof(struct sh_timer_config))
144   -
145   -static struct renesas_irqc_config irqc0_data = {
146   - .irq_base = irq_pin(0), /* IRQ0 -> IRQ9 */
147   -};
148   -
149   -static struct resource irqc0_resources[] = {
150   - DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
151   - DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
152   - DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
153   - DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
154   - DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
155   - DEFINE_RES_IRQ(gic_spi(12)), /* IRQ4 */
156   - DEFINE_RES_IRQ(gic_spi(13)), /* IRQ5 */
157   - DEFINE_RES_IRQ(gic_spi(14)), /* IRQ6 */
158   - DEFINE_RES_IRQ(gic_spi(15)), /* IRQ7 */
159   - DEFINE_RES_IRQ(gic_spi(16)), /* IRQ8 */
160   - DEFINE_RES_IRQ(gic_spi(17)), /* IRQ9 */
161   -};
162   -
163   -#define r8a7791_register_irqc(idx) \
164   - platform_device_register_resndata(NULL, "renesas_irqc", \
165   - idx, irqc##idx##_resources, \
166   - ARRAY_SIZE(irqc##idx##_resources), \
167   - &irqc##idx##_data, \
168   - sizeof(struct renesas_irqc_config))
169   -
170   -static const struct resource thermal_resources[] __initconst = {
171   - DEFINE_RES_MEM(0xe61f0000, 0x14),
172   - DEFINE_RES_MEM(0xe61f0100, 0x38),
173   - DEFINE_RES_IRQ(gic_spi(69)),
174   -};
175   -
176   -#define r8a7791_register_thermal() \
177   - platform_device_register_simple("rcar_thermal", -1, \
178   - thermal_resources, \
179   - ARRAY_SIZE(thermal_resources))
180   -
181   -void __init r8a7791_add_standard_devices(void)
182   -{
183   - r8a7791_register_scif(0);
184   - r8a7791_register_scif(1);
185   - r8a7791_register_scif(2);
186   - r8a7791_register_scif(3);
187   - r8a7791_register_scif(4);
188   - r8a7791_register_scif(5);
189   - r8a7791_register_scif(6);
190   - r8a7791_register_scif(7);
191   - r8a7791_register_scif(8);
192   - r8a7791_register_scif(9);
193   - r8a7791_register_scif(10);
194   - r8a7791_register_scif(11);
195   - r8a7791_register_scif(12);
196   - r8a7791_register_scif(13);
197   - r8a7791_register_scif(14);
198   - r8a7791_register_cmt(0);
199   - r8a7791_register_irqc(0);
200   - r8a7791_register_thermal();
201   -}
202   -
203   -#ifdef CONFIG_USE_OF
204 26 static const char *r8a7791_boards_compat_dt[] __initdata = {
205 27 "renesas,r8a7791",
206 28 NULL,
... ... @@ -214,5 +36,4 @@
214 36 .reserve = rcar_gen2_reserve,
215 37 .dt_compat = r8a7791_boards_compat_dt,
216 38 MACHINE_END
217   -#endif /* CONFIG_USE_OF */