Eric Lee / smarc-fsl-linux-kernel

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Commit 788144656b8a862e724a1296e64ab6375eb541ed

Authored by Manuel Lauss
Committed by Ralf Baechle
1 parent 93e9cd8485
Exists in master and in 39 other branches 8mp-imx_5.4.70_2.3.0, 8qm-imx_5.4.70_2.3.0, emb_imx_lf-5.15.y, emb_lf-6.1.y, imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, imx_4.1.15_1.0.0_ga, pitx_8mp_lf-5.10.y, rt-smarc-imx_4.1.15_1.0.0_ga, rt_linux_5.15.71, smarc-8m-android-11.0.0_2.0.0, smarc-imx6_4.14.98_2.0.0_ga, smarc-imx6_4.9.88_2.0.0_ga, smarc-imx7_4.14.98_2.0.0_ga, smarc-imx7_4.9.11_1.0.0_ga, smarc-imx7_4.9.88_2.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-imx_4.1.15_1.0.0_ga, smarc-imx_4.9.11_1.0.0_ga, smarc-imx_4.9.51_imx8m_ga, smarc-imx_4.9.88_2.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_1.2.0_ga, smarc_8m_00d0_imx_4.14.98_2.0.0_ga, smarc_8m_imx_4.14.78_1.0.0_ga, smarc_8m_imx_4.14.98_2.0.0_ga, smarc_8m_imx_4.19.35_1.1.0, smarc_8mm_imx_4.14.78_1.0.0_ga, smarc_8mm_imx_4.14.98_2.0.0_ga, smarc_8mm_imx_4.19.35_1.1.0, smarc_8mm_imx_5.4.24_2.1.0, smarc_8mp_lf-5.10.y, smarc_8mq_imx_5.4.24_2.1.0, smarc_8mq_lf-5.10.y, smarc_imx_lf-5.15.y

MIPS: Alchemy: Stop IRQ name sharing 

Eliminate the sharing of IRQ names among the differenct Alchemy
variants.  IRQ numbers need no longer be hidden behind a
CONFIG_SOC_AU1XXX symbol: step 1 in my quest to make the Alchemy
code less reliant on a hardcoded subtype.

This patch also renames the GPIO irq number constants. It's really
an interrupt line, NOT a GPIO number!

Code which relied on certain irq numbers to have the same name
across all supported cpu subtypes is changed to determine current
cpu subtype at runtime; in some places this isn't possible so
a "compat" symbol is used.

Run-tested on DB1200.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Showing 19 changed files with 743 additions and 665 deletions Side-by-side Diff

arch/mips/alchemy/common/dbdma.c
Diff comments   View file @ 7881446
... ... @@ -30,6 +30,7 @@
30 30 *
31 31 */
32 32  
  33 +#include <linux/init.h>
33 34 #include <linux/kernel.h>
34 35 #include <linux/slab.h>
35 36 #include <linux/spinlock.h>
... ... @@ -58,7 +59,6 @@
58 59  
59 60 static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE;
60 61 static int dbdma_initialized;
61   -static void au1xxx_dbdma_init(void);
62 62  
63 63 static dbdev_tab_t dbdev_tab[] = {
64 64 #ifdef CONFIG_SOC_AU1550
... ... @@ -250,8 +250,7 @@
250 250 * which can't be done successfully during board set up.
251 251 */
252 252 if (!dbdma_initialized)
253   - au1xxx_dbdma_init();
254   - dbdma_initialized = 1;
  253 + return 0;
255 254  
256 255 stp = find_dbdev_id(srcid);
257 256 if (stp == NULL)
... ... @@ -871,28 +870,6 @@
871 870 return IRQ_RETVAL(1);
872 871 }
873 872  
874   -static void au1xxx_dbdma_init(void)
875   -{
876   - int irq_nr;
877   -
878   - dbdma_gptr->ddma_config = 0;
879   - dbdma_gptr->ddma_throttle = 0;
880   - dbdma_gptr->ddma_inten = 0xffff;
881   - au_sync();
882   -
883   -#if defined(CONFIG_SOC_AU1550)
884   - irq_nr = AU1550_DDMA_INT;
885   -#elif defined(CONFIG_SOC_AU1200)
886   - irq_nr = AU1200_DDMA_INT;
887   -#else
888   - #error Unknown Au1x00 SOC
889   -#endif
890   -
891   - if (request_irq(irq_nr, dbdma_interrupt, IRQF_DISABLED,
892   - "Au1xxx dbdma", (void *)dbdma_gptr))
893   - printk(KERN_ERR "Can't get 1550 dbdma irq");
894   -}
895   -
896 873 void au1xxx_dbdma_dump(u32 chanid)
897 874 {
898 875 chan_tab_t *ctp;
... ... @@ -1041,5 +1018,39 @@
1041 1018 }
1042 1019 }
1043 1020 #endif /* CONFIG_PM */
  1021 +
  1022 +static int __init au1xxx_dbdma_init(void)
  1023 +{
  1024 + int irq_nr, ret;
  1025 +
  1026 + dbdma_gptr->ddma_config = 0;
  1027 + dbdma_gptr->ddma_throttle = 0;
  1028 + dbdma_gptr->ddma_inten = 0xffff;
  1029 + au_sync();
  1030 +
  1031 + switch (alchemy_get_cputype()) {
  1032 + case ALCHEMY_CPU_AU1550:
  1033 + irq_nr = AU1550_DDMA_INT;
  1034 + break;
  1035 + case ALCHEMY_CPU_AU1200:
  1036 + irq_nr = AU1200_DDMA_INT;
  1037 + break;
  1038 + default:
  1039 + return -ENODEV;
  1040 + }
  1041 +
  1042 + ret = request_irq(irq_nr, dbdma_interrupt, IRQF_DISABLED,
  1043 + "Au1xxx dbdma", (void *)dbdma_gptr);
  1044 + if (ret)
  1045 + printk(KERN_ERR "Cannot grab DBDMA interrupt!\n");
  1046 + else {
  1047 + dbdma_initialized = 1;
  1048 + printk(KERN_INFO "Alchemy DBDMA initialized\n");
  1049 + }
  1050 +
  1051 + return ret;
  1052 +}
  1053 +subsys_initcall(au1xxx_dbdma_init);
  1054 +
1044 1055 #endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */
arch/mips/alchemy/common/dma.c
Diff comments   View file @ 7881446
... ... @@ -29,6 +29,8 @@
29 29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 30 *
31 31 */
  32 +
  33 +#include <linux/init.h>
32 34 #include <linux/module.h>
33 35 #include <linux/kernel.h>
34 36 #include <linux/errno.h>
35 37  
36 38  
... ... @@ -188,17 +190,14 @@
188 190 dev = &dma_dev_table[dev_id];
189 191  
190 192 if (irqhandler) {
191   - chan->irq = AU1000_DMA_INT_BASE + i;
192 193 chan->irq_dev = irq_dev_id;
193 194 ret = request_irq(chan->irq, irqhandler, irqflags, dev_str,
194 195 chan->irq_dev);
195 196 if (ret) {
196   - chan->irq = 0;
197 197 chan->irq_dev = NULL;
198 198 return ret;
199 199 }
200 200 } else {
201   - chan->irq = 0;
202 201 chan->irq_dev = NULL;
203 202 }
204 203  
205 204  
206 205  
... ... @@ -226,14 +225,41 @@
226 225 }
227 226  
228 227 disable_dma(dmanr);
229   - if (chan->irq)
  228 + if (chan->irq_dev)
230 229 free_irq(chan->irq, chan->irq_dev);
231 230  
232   - chan->irq = 0;
233 231 chan->irq_dev = NULL;
234 232 chan->dev_id = -1;
235 233 }
236 234 EXPORT_SYMBOL(free_au1000_dma);
  235 +
  236 +static int __init au1000_dma_init(void)
  237 +{
  238 + int base, i;
  239 +
  240 + switch (alchemy_get_cputype()) {
  241 + case ALCHEMY_CPU_AU1000:
  242 + base = AU1000_DMA_INT_BASE;
  243 + break;
  244 + case ALCHEMY_CPU_AU1500:
  245 + base = AU1500_DMA_INT_BASE;
  246 + break;
  247 + case ALCHEMY_CPU_AU1100:
  248 + base = AU1100_DMA_INT_BASE;
  249 + break;
  250 + default:
  251 + goto out;
  252 + }
  253 +
  254 + for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++)
  255 + au1000_dma_table[i].irq = base + i;
  256 +
  257 + printk(KERN_INFO "Alchemy DMA initialized\n");
  258 +
  259 +out:
  260 + return 0;
  261 +}
  262 +arch_initcall(au1000_dma_init);
237 263  
238 264 #endif /* AU1000 AU1500 AU1100 */
arch/mips/alchemy/common/irq.c
Diff comments   View file @ 7881446
... ... @@ -53,160 +53,160 @@
53 53 int im_request; /* set 1 to get higher priority */
54 54 } au1xxx_ic0_map[] __initdata = {
55 55 #if defined(CONFIG_SOC_AU1000)
56   - { AU1000_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
57   - { AU1000_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
58   - { AU1000_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
59   - { AU1000_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
60   - { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
61   - { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
62   - { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
63   - { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
64   - { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
65   - { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
66   - { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
67   - { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
68   - { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
69   - { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
70   - { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
71   - { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
72   - { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
73   - { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
74   - { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
75   - { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
76   - { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
77   - { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
78   - { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
79   - { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
80   - { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 },
  56 + { AU1000_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  57 + { AU1000_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  58 + { AU1000_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  59 + { AU1000_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  60 + { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  61 + { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  62 + { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
  63 + { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
  64 + { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
  65 + { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
  66 + { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
  67 + { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
  68 + { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
  69 + { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
  70 + { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
  71 + { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
  72 + { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
  73 + { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
  74 + { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
  75 + { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
  76 + { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
  77 + { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
  78 + { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  79 + { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  80 + { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 },
81 81 { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
82   - { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
83   - { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
84   - { AU1000_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
85   - { AU1000_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
86   - { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
  82 + { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
  83 + { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
  84 + { AU1000_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  85 + { AU1000_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  86 + { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
87 87  
88 88 #elif defined(CONFIG_SOC_AU1500)
89 89  
90   - { AU1500_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
91   - { AU1000_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 },
92   - { AU1000_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 },
93   - { AU1500_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
94   - { AU1000_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 },
95   - { AU1000_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 },
96   - { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
97   - { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
98   - { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
99   - { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
100   - { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
101   - { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
102   - { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
103   - { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
104   - { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
105   - { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
106   - { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
107   - { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
108   - { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
109   - { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
110   - { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
111   - { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
112   - { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 },
113   - { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
114   - { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
115   - { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
116   - { AU1500_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
117   - { AU1500_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
118   - { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
  90 + { AU1500_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  91 + { AU1500_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 },
  92 + { AU1500_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 },
  93 + { AU1500_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  94 + { AU1500_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 },
  95 + { AU1500_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 },
  96 + { AU1500_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
  97 + { AU1500_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
  98 + { AU1500_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
  99 + { AU1500_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
  100 + { AU1500_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
  101 + { AU1500_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
  102 + { AU1500_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
  103 + { AU1500_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
  104 + { AU1500_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
  105 + { AU1500_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
  106 + { AU1500_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
  107 + { AU1500_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
  108 + { AU1500_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
  109 + { AU1500_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
  110 + { AU1500_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
  111 + { AU1500_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
  112 + { AU1500_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 },
  113 + { AU1500_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
  114 + { AU1500_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
  115 + { AU1500_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
  116 + { AU1500_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  117 + { AU1500_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  118 + { AU1500_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
119 119  
120 120 #elif defined(CONFIG_SOC_AU1100)
121 121  
122   - { AU1100_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
123   - { AU1100_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
124   - { AU1100_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
125   - { AU1100_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
126   - { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
127   - { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
128   - { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
129   - { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
130   - { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
131   - { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
132   - { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
133   - { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
134   - { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
135   - { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
136   - { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
137   - { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
138   - { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
139   - { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
140   - { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
141   - { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
142   - { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
143   - { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
144   - { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
145   - { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
146   - { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 },
147   - { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
148   - { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
149   - { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
150   - { AU1100_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
151   - { AU1100_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
152   - { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
  122 + { AU1100_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  123 + { AU1100_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  124 + { AU1100_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  125 + { AU1100_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  126 + { AU1100_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  127 + { AU1100_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  128 + { AU1100_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
  129 + { AU1100_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
  130 + { AU1100_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
  131 + { AU1100_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
  132 + { AU1100_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
  133 + { AU1100_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
  134 + { AU1100_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
  135 + { AU1100_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
  136 + { AU1100_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
  137 + { AU1100_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
  138 + { AU1100_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
  139 + { AU1100_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
  140 + { AU1100_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
  141 + { AU1100_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
  142 + { AU1100_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
  143 + { AU1100_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
  144 + { AU1100_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  145 + { AU1100_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  146 + { AU1100_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 },
  147 + { AU1100_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
  148 + { AU1100_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
  149 + { AU1100_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
  150 + { AU1100_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  151 + { AU1100_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  152 + { AU1100_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
153 153  
154 154 #elif defined(CONFIG_SOC_AU1550)
155 155  
156   - { AU1550_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
157   - { AU1550_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 },
158   - { AU1550_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 },
159   - { AU1550_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
160   - { AU1550_CRYPTO_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
161   - { AU1550_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 },
162   - { AU1550_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 },
163   - { AU1550_PCI_RST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
164   - { AU1550_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
165   - { AU1550_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
166   - { AU1550_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
167   - { AU1550_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
168   - { AU1550_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
169   - { AU1550_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
170   - { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
171   - { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
172   - { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
173   - { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
174   - { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
175   - { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
176   - { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
177   - { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
178   - { AU1550_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 },
179   - { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 },
  156 + { AU1550_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  157 + { AU1550_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 },
  158 + { AU1550_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 },
  159 + { AU1550_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  160 + { AU1550_CRYPTO_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  161 + { AU1550_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 },
  162 + { AU1550_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 },
  163 + { AU1550_PCI_RST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
  164 + { AU1550_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  165 + { AU1550_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  166 + { AU1550_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  167 + { AU1550_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  168 + { AU1550_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  169 + { AU1550_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  170 + { AU1550_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
  171 + { AU1550_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
  172 + { AU1550_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
  173 + { AU1550_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
  174 + { AU1550_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
  175 + { AU1550_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
  176 + { AU1550_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
  177 + { AU1550_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
  178 + { AU1550_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 },
  179 + { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 },
180 180 { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
181   - { AU1550_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
182   - { AU1550_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
183   - { AU1550_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  181 + { AU1550_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
  182 + { AU1550_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  183 + { AU1550_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
184 184  
185 185 #elif defined(CONFIG_SOC_AU1200)
186 186  
187   - { AU1200_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
188   - { AU1200_SWT_INT, IRQ_TYPE_EDGE_RISING, 0 },
189   - { AU1200_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
190   - { AU1200_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
191   - { AU1200_MAE_BE_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
192   - { AU1200_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
193   - { AU1200_MAE_FE_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
194   - { AU1200_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
195   - { AU1200_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
196   - { AU1200_AES_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
197   - { AU1200_CAMERA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
198   - { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
199   - { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
200   - { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
201   - { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
202   - { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
203   - { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
204   - { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
205   - { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
206   - { AU1200_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 },
207   - { AU1200_USB_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
208   - { AU1200_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
209   - { AU1200_MAE_BOTH_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  187 + { AU1200_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  188 + { AU1200_SWT_INT, IRQ_TYPE_EDGE_RISING, 0 },
  189 + { AU1200_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  190 + { AU1200_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  191 + { AU1200_MAE_BE_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  192 + { AU1200_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  193 + { AU1200_MAE_FE_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  194 + { AU1200_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  195 + { AU1200_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  196 + { AU1200_AES_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  197 + { AU1200_CAMERA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  198 + { AU1200_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
  199 + { AU1200_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
  200 + { AU1200_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
  201 + { AU1200_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
  202 + { AU1200_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
  203 + { AU1200_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
  204 + { AU1200_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
  205 + { AU1200_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
  206 + { AU1200_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 },
  207 + { AU1200_USB_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  208 + { AU1200_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
  209 + { AU1200_MAE_BOTH_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
210 210  
211 211 #else
212 212 #error "Error: Unknown Alchemy SOC"
... ... @@ -316,7 +316,7 @@
316 316 * nowhere in the current kernel sources is it disabled. --mlau
317 317 */
318 318 #if defined(CONFIG_MIPS_PB1000)
319   - if (irq_nr == AU1000_GPIO_15)
  319 + if (irq_nr == AU1000_GPIO15_INT)
320 320 au_writel(0x4000, PB1000_MDR); /* enable int */
321 321 #endif
322 322 au_sync();
323 323  
... ... @@ -388,11 +388,13 @@
388 388  
389 389 static int au1x_ic1_setwake(unsigned int irq, unsigned int on)
390 390 {
391   - unsigned int bit = irq - AU1000_INTC1_INT_BASE;
  391 + int bit = irq - AU1000_INTC1_INT_BASE;
392 392 unsigned long wakemsk, flags;
393 393  
394   - /* only GPIO 0-7 can act as wakeup source: */
395   - if ((irq < AU1000_GPIO_0) || (irq > AU1000_GPIO_7))
  394 + /* only GPIO 0-7 can act as wakeup source. Fortunately these
  395 + * are wired up identically on all supported variants.
  396 + */
  397 + if ((bit < 0) || (bit > 7))
396 398 return -EINVAL;
397 399  
398 400 local_irq_save(flags);
arch/mips/alchemy/common/platform.c
Diff comments   View file @ 7881446
... ... @@ -73,8 +73,8 @@
73 73 .flags = IORESOURCE_MEM,
74 74 },
75 75 [1] = {
76   - .start = AU1000_USB_HOST_INT,
77   - .end = AU1000_USB_HOST_INT,
  76 + .start = FOR_PLATFORM_C_USB_HOST_INT,
  77 + .end = FOR_PLATFORM_C_USB_HOST_INT,
78 78 .flags = IORESOURCE_IRQ,
79 79 },
80 80 };
... ... @@ -132,8 +132,8 @@
132 132 .flags = IORESOURCE_MEM,
133 133 },
134 134 [1] = {
135   - .start = AU1000_USB_HOST_INT,
136   - .end = AU1000_USB_HOST_INT,
  135 + .start = AU1200_USB_INT,
  136 + .end = AU1200_USB_INT,
137 137 .flags = IORESOURCE_IRQ,
138 138 },
139 139 };
arch/mips/alchemy/common/time.c
Diff comments   View file @ 7881446
1 1 /*
2   - * Copyright (C) 2008 Manuel Lauss <mano@roarinelk.homelinux.net>
  2 + * Copyright (C) 2008-2009 Manuel Lauss <manuel.lauss@gmail.com>
3 3 *
4 4 * Previous incarnations were:
5 5 * Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com>
... ... @@ -85,7 +85,6 @@
85 85 .name = "rtcmatch2",
86 86 .features = CLOCK_EVT_FEAT_ONESHOT,
87 87 .rating = 100,
88   - .irq = AU1000_RTC_MATCH2_INT,
89 88 .set_next_event = au1x_rtcmatch2_set_next_event,
90 89 .set_mode = au1x_rtcmatch2_set_mode,
91 90 .cpumask = cpu_all_mask,
92 91  
... ... @@ -98,11 +97,13 @@
98 97 .dev_id = &au1x_rtcmatch2_clockdev,
99 98 };
100 99  
101   -void __init plat_time_init(void)
  100 +static int __init alchemy_time_init(unsigned int m2int)
102 101 {
103 102 struct clock_event_device *cd = &au1x_rtcmatch2_clockdev;
104 103 unsigned long t;
105 104  
  105 + au1x_rtcmatch2_clockdev.irq = m2int;
  106 +
106 107 /* Check if firmware (YAMON, ...) has enabled 32kHz and clock
107 108 * has been detected. If so install the rtcmatch2 clocksource,
108 109 * otherwise don't bother. Note that both bits being set is by
109 110  
110 111  
... ... @@ -148,13 +149,18 @@
148 149 cd->max_delta_ns = clockevent_delta2ns(0xffffffff, cd);
149 150 cd->min_delta_ns = clockevent_delta2ns(8, cd); /* ~0.25ms */
150 151 clockevents_register_device(cd);
151   - setup_irq(AU1000_RTC_MATCH2_INT, &au1x_rtcmatch2_irqaction);
  152 + setup_irq(m2int, &au1x_rtcmatch2_irqaction);
152 153  
153 154 printk(KERN_INFO "Alchemy clocksource installed\n");
154 155  
155   - return;
  156 + return 0;
156 157  
157 158 cntr_err:
  159 + return -1;
  160 +}
  161 +
  162 +static void __init alchemy_setup_c0timer(void)
  163 +{
158 164 /*
159 165 * MIPS kernel assigns 'au1k_wait' to 'cpu_wait' before this
160 166 * function is called. Because the Alchemy counters are unusable
... ... @@ -165,5 +171,24 @@
165 171 cpu_wait = NULL;
166 172 r4k_clockevent_init();
167 173 init_r4k_clocksource();
  174 +}
  175 +
  176 +static int alchemy_m2inttab[] __initdata = {
  177 + AU1000_RTC_MATCH2_INT,
  178 + AU1500_RTC_MATCH2_INT,
  179 + AU1100_RTC_MATCH2_INT,
  180 + AU1550_RTC_MATCH2_INT,
  181 + AU1200_RTC_MATCH2_INT,
  182 +};
  183 +
  184 +void __init plat_time_init(void)
  185 +{
  186 + int t;
  187 +
  188 + t = alchemy_get_cputype();
  189 + if (t == ALCHEMY_CPU_UNKNOWN)
  190 + alchemy_setup_c0timer();
  191 + else if (alchemy_time_init(alchemy_m2inttab[t]))
  192 + alchemy_setup_c0timer();
168 193 }
arch/mips/alchemy/devboards/db1x00/board_setup.c
Diff comments   View file @ 7881446
... ... @@ -39,32 +39,32 @@
39 39  
40 40 #ifdef CONFIG_MIPS_DB1500
41 41 char irq_tab_alchemy[][5] __initdata = {
42   - [12] = { -1, INTA, INTX, INTX, INTX }, /* IDSEL 12 - HPT371 */
43   - [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot */
  42 + [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT371 */
  43 + [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
44 44 };
45 45 #endif
46 46  
47 47 #ifdef CONFIG_MIPS_BOSPORUS
48 48 char irq_tab_alchemy[][5] __initdata = {
49   - [11] = { -1, INTA, INTB, INTX, INTX }, /* IDSEL 11 - miniPCI */
50   - [12] = { -1, INTA, INTX, INTX, INTX }, /* IDSEL 12 - SN1741 */
51   - [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot */
  49 + [11] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 11 - miniPCI */
  50 + [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - SN1741 */
  51 + [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
52 52 };
53 53 #endif
54 54  
55 55 #ifdef CONFIG_MIPS_MIRAGE
56 56 char irq_tab_alchemy[][5] __initdata = {
57   - [11] = { -1, INTD, INTX, INTX, INTX }, /* IDSEL 11 - SMI VGX */
58   - [12] = { -1, INTX, INTX, INTC, INTX }, /* IDSEL 12 - PNX1300 */
59   - [13] = { -1, INTA, INTB, INTX, INTX }, /* IDSEL 13 - miniPCI */
  57 + [11] = { -1, AU1500_PCI_INTD, 0xff, 0xff, 0xff }, /* IDSEL 11 - SMI VGX */
  58 + [12] = { -1, 0xff, 0xff, AU1500_PCI_INTC, 0xff }, /* IDSEL 12 - PNX1300 */
  59 + [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 13 - miniPCI */
60 60 };
61 61 #endif
62 62  
63 63 #ifdef CONFIG_MIPS_DB1550
64 64 char irq_tab_alchemy[][5] __initdata = {
65   - [11] = { -1, INTC, INTX, INTX, INTX }, /* IDSEL 11 - on-board HPT371 */
66   - [12] = { -1, INTB, INTC, INTD, INTA }, /* IDSEL 12 - PCI slot 2 (left) */
67   - [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot 1 (right) */
  65 + [11] = { -1, AU1550_PCI_INTC, 0xff, 0xff, 0xff }, /* IDSEL 11 - on-board HPT371 */
  66 + [12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */
  67 + [13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */
68 68 };
69 69 #endif
70 70  
71 71  
... ... @@ -185,21 +185,35 @@
185 185 static int __init db1x00_init_irq(void)
186 186 {
187 187 #if defined(CONFIG_MIPS_MIRAGE)
188   - set_irq_type(AU1000_GPIO_7, IRQF_TRIGGER_RISING); /* TS pendown */
  188 + set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */
189 189 #elif defined(CONFIG_MIPS_DB1550)
190   - set_irq_type(AU1000_GPIO_0, IRQF_TRIGGER_LOW); /* CD0# */
191   - set_irq_type(AU1000_GPIO_1, IRQF_TRIGGER_LOW); /* CD1# */
192   - set_irq_type(AU1000_GPIO_3, IRQF_TRIGGER_LOW); /* CARD0# */
193   - set_irq_type(AU1000_GPIO_5, IRQF_TRIGGER_LOW); /* CARD1# */
194   - set_irq_type(AU1000_GPIO_21, IRQF_TRIGGER_LOW); /* STSCHG0# */
195   - set_irq_type(AU1000_GPIO_22, IRQF_TRIGGER_LOW); /* STSCHG1# */
196   -#else
197   - set_irq_type(AU1000_GPIO_0, IRQF_TRIGGER_LOW); /* CD0# */
198   - set_irq_type(AU1000_GPIO_3, IRQF_TRIGGER_LOW); /* CD1# */
199   - set_irq_type(AU1000_GPIO_2, IRQF_TRIGGER_LOW); /* CARD0# */
200   - set_irq_type(AU1000_GPIO_5, IRQF_TRIGGER_LOW); /* CARD1# */
201   - set_irq_type(AU1000_GPIO_1, IRQF_TRIGGER_LOW); /* STSCHG0# */
202   - set_irq_type(AU1000_GPIO_4, IRQF_TRIGGER_LOW); /* STSCHG1# */
  190 + set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
  191 + set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); /* CD1# */
  192 + set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW); /* CARD0# */
  193 + set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
  194 + set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
  195 + set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
  196 +#elif defined(CONFIG_MIPS_DB1500)
  197 + set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
  198 + set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
  199 + set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
  200 + set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
  201 + set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
  202 + set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
  203 +#elif defined(CONFIG_MIPS_DB1100)
  204 + set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
  205 + set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
  206 + set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
  207 + set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
  208 + set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
  209 + set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
  210 +#elif defined(CONFIG_MIPS_DB1000)
  211 + set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
  212 + set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
  213 + set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
  214 + set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
  215 + set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
  216 + set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
203 217 #endif
204 218 return 0;
205 219 }
arch/mips/alchemy/devboards/db1x00/platform.c
Diff comments   View file @ 7881446
... ... @@ -24,32 +24,46 @@
24 24 #include <asm/mach-au1x00/au1xxx.h>
25 25 #include "../platform.h"
26 26  
27   -#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || \
28   - defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550)
29   -#define DB1XXX_HAS_PCMCIA
30   -#endif
31   -
32 27 /* DB1xxx PCMCIA interrupt sources:
33 28 * CD0/1 GPIO0/3
34 29 * STSCHG0/1 GPIO1/4
35 30 * CARD0/1 GPIO2/5
36 31 * Db1550: 0/1, 21/22, 3/5
37 32 */
38   -#ifndef CONFIG_MIPS_DB1550
39   -/* Db1000, Db1100, Db1500 */
40   -#define DB1XXX_PCMCIA_CD0 AU1000_GPIO_0
41   -#define DB1XXX_PCMCIA_STSCHG0 AU1000_GPIO_1
42   -#define DB1XXX_PCMCIA_CARD0 AU1000_GPIO_2
43   -#define DB1XXX_PCMCIA_CD1 AU1000_GPIO_3
44   -#define DB1XXX_PCMCIA_STSCHG1 AU1000_GPIO_4
45   -#define DB1XXX_PCMCIA_CARD1 AU1000_GPIO_5
  33 +
  34 +#define DB1XXX_HAS_PCMCIA
  35 +
  36 +#if defined(CONFIG_MIPS_DB1000)
  37 +#define DB1XXX_PCMCIA_CD0 AU1000_GPIO0_INT
  38 +#define DB1XXX_PCMCIA_STSCHG0 AU1000_GPIO1_INT
  39 +#define DB1XXX_PCMCIA_CARD0 AU1000_GPIO2_INT
  40 +#define DB1XXX_PCMCIA_CD1 AU1000_GPIO3_INT
  41 +#define DB1XXX_PCMCIA_STSCHG1 AU1000_GPIO4_INT
  42 +#define DB1XXX_PCMCIA_CARD1 AU1000_GPIO5_INT
  43 +#elif defined(CONFIG_MIPS_DB1100)
  44 +#define DB1XXX_PCMCIA_CD0 AU1100_GPIO0_INT
  45 +#define DB1XXX_PCMCIA_STSCHG0 AU1100_GPIO1_INT
  46 +#define DB1XXX_PCMCIA_CARD0 AU1100_GPIO2_INT
  47 +#define DB1XXX_PCMCIA_CD1 AU1100_GPIO3_INT
  48 +#define DB1XXX_PCMCIA_STSCHG1 AU1100_GPIO4_INT
  49 +#define DB1XXX_PCMCIA_CARD1 AU1100_GPIO5_INT
  50 +#elif defined(CONFIG_MIPS_DB1500)
  51 +#define DB1XXX_PCMCIA_CD0 AU1500_GPIO0_INT
  52 +#define DB1XXX_PCMCIA_STSCHG0 AU1500_GPIO1_INT
  53 +#define DB1XXX_PCMCIA_CARD0 AU1500_GPIO2_INT
  54 +#define DB1XXX_PCMCIA_CD1 AU1500_GPIO3_INT
  55 +#define DB1XXX_PCMCIA_STSCHG1 AU1500_GPIO4_INT
  56 +#define DB1XXX_PCMCIA_CARD1 AU1500_GPIO5_INT
  57 +#elif defined(CONFIG_MIPS_DB1550)
  58 +#define DB1XXX_PCMCIA_CD0 AU1550_GPIO0_INT
  59 +#define DB1XXX_PCMCIA_STSCHG0 AU1550_GPIO21_INT
  60 +#define DB1XXX_PCMCIA_CARD0 AU1550_GPIO3_INT
  61 +#define DB1XXX_PCMCIA_CD1 AU1550_GPIO1_INT
  62 +#define DB1XXX_PCMCIA_STSCHG1 AU1550_GPIO22_INT
  63 +#define DB1XXX_PCMCIA_CARD1 AU1550_GPIO5_INT
46 64 #else
47   -#define DB1XXX_PCMCIA_CD0 AU1000_GPIO_0
48   -#define DB1XXX_PCMCIA_STSCHG0 AU1500_GPIO_21
49   -#define DB1XXX_PCMCIA_CARD0 AU1000_GPIO_3
50   -#define DB1XXX_PCMCIA_CD1 AU1000_GPIO_1
51   -#define DB1XXX_PCMCIA_STSCHG1 AU1500_GPIO_22
52   -#define DB1XXX_PCMCIA_CARD1 AU1000_GPIO_5
  65 +/* other board: no PCMCIA */
  66 +#undef DB1XXX_HAS_PCMCIA
53 67 #endif
54 68  
55 69 static int __init db1xxx_dev_init(void)
arch/mips/alchemy/devboards/pb1000/board_setup.c
Diff comments   View file @ 7881446
... ... @@ -186,7 +186,7 @@
186 186  
187 187 static int __init pb1000_init_irq(void)
188 188 {
189   - set_irq_type(AU1000_GPIO_15, IRQF_TRIGGER_LOW);
  189 + set_irq_type(AU1000_GPIO15_INT, IRQF_TRIGGER_LOW);
190 190 return 0;
191 191 }
192 192 arch_initcall(pb1000_init_irq);
arch/mips/alchemy/devboards/pb1100/board_setup.c
Diff comments   View file @ 7881446
... ... @@ -147,10 +147,10 @@
147 147  
148 148 static int __init pb1100_init_irq(void)
149 149 {
150   - set_irq_type(AU1000_GPIO_9, IRQF_TRIGGER_LOW); /* PCCD# */
151   - set_irq_type(AU1000_GPIO_10, IRQF_TRIGGER_LOW); /* PCSTSCHG# */
152   - set_irq_type(AU1000_GPIO_11, IRQF_TRIGGER_LOW); /* PCCard# */
153   - set_irq_type(AU1000_GPIO_13, IRQF_TRIGGER_LOW); /* DC_IRQ# */
  150 + set_irq_type(AU1100_GPIO9_INT, IRQF_TRIGGER_LOW); /* PCCD# */
  151 + set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */
  152 + set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */
  153 + set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */
154 154  
155 155 return 0;
156 156 }
arch/mips/alchemy/devboards/pb1100/platform.c
Diff comments   View file @ 7881446
... ... @@ -33,9 +33,9 @@
33 33 PCMCIA_MEM_PSEUDO_PHYS + 0x00040000 - 1,
34 34 PCMCIA_IO_PSEUDO_PHYS,
35 35 PCMCIA_IO_PSEUDO_PHYS + 0x00001000 - 1,
36   - AU1000_GPIO_11, /* card */
37   - AU1000_GPIO_9, /* insert */
38   - /*AU1000_GPIO_10*/0, /* stschg */
  36 + AU1100_GPIO11_INT, /* card */
  37 + AU1100_GPIO9_INT, /* insert */
  38 + /*AU1100_GPIO10_INT*/0, /* stschg */
39 39 0, /* eject */
40 40 0); /* id */
41 41 return 0;
arch/mips/alchemy/devboards/pb1200/board_setup.c
Diff comments   View file @ 7881446
... ... @@ -171,8 +171,8 @@
171 171 }
172 172 #endif
173 173  
174   - set_irq_type(AU1000_GPIO_7, IRQF_TRIGGER_LOW);
175   - bcsr_init_irq(PB1200_INT_BEGIN, PB1200_INT_END, AU1000_GPIO_7);
  174 + set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
  175 + bcsr_init_irq(PB1200_INT_BEGIN, PB1200_INT_END, AU1200_GPIO7_INT);
176 176  
177 177 return 0;
178 178 }
arch/mips/alchemy/devboards/pb1500/board_setup.c
Diff comments   View file @ 7881446
... ... @@ -35,8 +35,8 @@
35 35  
36 36  
37 37 char irq_tab_alchemy[][5] __initdata = {
38   - [12] = { -1, INTA, INTX, INTX, INTX }, /* IDSEL 12 - HPT370 */
39   - [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot */
  38 + [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT370 */
  39 + [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
40 40 };
41 41  
42 42  
... ... @@ -155,14 +155,14 @@
155 155  
156 156 static int __init pb1500_init_irq(void)
157 157 {
158   - set_irq_type(AU1000_GPIO_9, IRQF_TRIGGER_LOW); /* CD0# */
159   - set_irq_type(AU1000_GPIO_10, IRQF_TRIGGER_LOW); /* CARD0 */
160   - set_irq_type(AU1000_GPIO_11, IRQF_TRIGGER_LOW); /* STSCHG0# */
161   - set_irq_type(AU1500_GPIO_204, IRQF_TRIGGER_HIGH);
162   - set_irq_type(AU1500_GPIO_201, IRQF_TRIGGER_LOW);
163   - set_irq_type(AU1500_GPIO_202, IRQF_TRIGGER_LOW);
164   - set_irq_type(AU1500_GPIO_203, IRQF_TRIGGER_LOW);
165   - set_irq_type(AU1500_GPIO_205, IRQF_TRIGGER_LOW);
  158 + set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW); /* CD0# */
  159 + set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW); /* CARD0 */
  160 + set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
  161 + set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
  162 + set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
  163 + set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
  164 + set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
  165 + set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
166 166  
167 167 return 0;
168 168 }
arch/mips/alchemy/devboards/pb1500/platform.c
Diff comments   View file @ 7881446
... ... @@ -32,9 +32,9 @@
32 32 PCMCIA_MEM_PSEUDO_PHYS + 0x00040000 - 1,
33 33 PCMCIA_IO_PSEUDO_PHYS,
34 34 PCMCIA_IO_PSEUDO_PHYS + 0x00001000 - 1,
35   - AU1000_GPIO_11, /* card */
36   - AU1000_GPIO_9, /* insert */
37   - /*AU1000_GPIO_10*/0, /* stschg */
  35 + AU1500_GPIO11_INT, /* card */
  36 + AU1500_GPIO9_INT, /* insert */
  37 + /*AU1500_GPIO10_INT*/0, /* stschg */
38 38 0, /* eject */
39 39 0); /* id */
40 40 return 0;
arch/mips/alchemy/devboards/pb1550/board_setup.c
Diff comments   View file @ 7881446
... ... @@ -39,8 +39,8 @@
39 39  
40 40  
41 41 char irq_tab_alchemy[][5] __initdata = {
42   - [12] = { -1, INTB, INTC, INTD, INTA }, /* IDSEL 12 - PCI slot 2 (left) */
43   - [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot 1 (right) */
  42 + [12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */
  43 + [13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */
44 44 };
45 45  
46 46 const char *get_system_type(void)
... ... @@ -89,9 +89,9 @@
89 89  
90 90 static int __init pb1550_init_irq(void)
91 91 {
92   - set_irq_type(AU1000_GPIO_0, IRQF_TRIGGER_LOW);
93   - set_irq_type(AU1000_GPIO_1, IRQF_TRIGGER_LOW);
94   - set_irq_type(AU1500_GPIO_201_205, IRQF_TRIGGER_HIGH);
  92 + set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW);
  93 + set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW);
  94 + set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH);
95 95  
96 96 /* enable both PCMCIA card irqs in the shared line */
97 97 alchemy_gpio2_enable_int(201);
arch/mips/alchemy/devboards/pb1550/platform.c
Diff comments   View file @ 7881446
... ... @@ -40,8 +40,8 @@
40 40 PCMCIA_MEM_PSEUDO_PHYS + 0x00040000 - 1,
41 41 PCMCIA_IO_PSEUDO_PHYS,
42 42 PCMCIA_IO_PSEUDO_PHYS + 0x00001000 - 1,
43   - AU1500_GPIO_201_205,
44   - AU1000_GPIO_0,
  43 + AU1550_GPIO201_205_INT,
  44 + AU1550_GPIO0_INT,
45 45 0,
46 46 0,
47 47 0);
... ... @@ -52,8 +52,8 @@
52 52 PCMCIA_MEM_PSEUDO_PHYS + 0x00840000 - 1,
53 53 PCMCIA_IO_PSEUDO_PHYS + 0x00800000,
54 54 PCMCIA_IO_PSEUDO_PHYS + 0x00801000 - 1,
55   - AU1500_GPIO_201_205,
56   - AU1000_GPIO_1,
  55 + AU1550_GPIO201_205_INT,
  56 + AU1550_GPIO1_INT,
57 57 0,
58 58 0,
59 59 1);
arch/mips/alchemy/mtx-1/board_setup.c
Diff comments   View file @ 7881446
... ... @@ -37,14 +37,14 @@
37 37 #include <prom.h>
38 38  
39 39 char irq_tab_alchemy[][5] __initdata = {
40   - [0] = { -1, INTA, INTA, INTX, INTX }, /* IDSEL 00 - AdapterA-Slot0 (top) */
41   - [1] = { -1, INTB, INTA, INTX, INTX }, /* IDSEL 01 - AdapterA-Slot1 (bottom) */
42   - [2] = { -1, INTC, INTD, INTX, INTX }, /* IDSEL 02 - AdapterB-Slot0 (top) */
43   - [3] = { -1, INTD, INTC, INTX, INTX }, /* IDSEL 03 - AdapterB-Slot1 (bottom) */
44   - [4] = { -1, INTA, INTB, INTX, INTX }, /* IDSEL 04 - AdapterC-Slot0 (top) */
45   - [5] = { -1, INTB, INTA, INTX, INTX }, /* IDSEL 05 - AdapterC-Slot1 (bottom) */
46   - [6] = { -1, INTC, INTD, INTX, INTX }, /* IDSEL 06 - AdapterD-Slot0 (top) */
47   - [7] = { -1, INTD, INTC, INTX, INTX }, /* IDSEL 07 - AdapterD-Slot1 (bottom) */
  40 + [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 00 - AdapterA-Slot0 (top) */
  41 + [1] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 01 - AdapterA-Slot1 (bottom) */
  42 + [2] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 02 - AdapterB-Slot0 (top) */
  43 + [3] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 03 - AdapterB-Slot1 (bottom) */
  44 + [4] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 04 - AdapterC-Slot0 (top) */
  45 + [5] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 05 - AdapterC-Slot1 (bottom) */
  46 + [6] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 06 - AdapterD-Slot0 (top) */
  47 + [7] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 07 - AdapterD-Slot1 (bottom) */
48 48 };
49 49  
50 50 extern int (*board_pci_idsel)(unsigned int devsel, int assert);
... ... @@ -124,11 +124,11 @@
124 124  
125 125 static int __init mtx1_init_irq(void)
126 126 {
127   - set_irq_type(AU1500_GPIO_204, IRQF_TRIGGER_HIGH);
128   - set_irq_type(AU1500_GPIO_201, IRQF_TRIGGER_LOW);
129   - set_irq_type(AU1500_GPIO_202, IRQF_TRIGGER_LOW);
130   - set_irq_type(AU1500_GPIO_203, IRQF_TRIGGER_LOW);
131   - set_irq_type(AU1500_GPIO_205, IRQF_TRIGGER_LOW);
  127 + set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
  128 + set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
  129 + set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
  130 + set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
  131 + set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
132 132  
133 133 return 0;
134 134 }
arch/mips/alchemy/xxs1500/board_setup.c
Diff comments   View file @ 7881446
... ... @@ -80,19 +80,19 @@
80 80  
81 81 static int __init xxs1500_init_irq(void)
82 82 {
83   - set_irq_type(AU1500_GPIO_204, IRQF_TRIGGER_HIGH);
84   - set_irq_type(AU1500_GPIO_201, IRQF_TRIGGER_LOW);
85   - set_irq_type(AU1500_GPIO_202, IRQF_TRIGGER_LOW);
86   - set_irq_type(AU1500_GPIO_203, IRQF_TRIGGER_LOW);
87   - set_irq_type(AU1500_GPIO_205, IRQF_TRIGGER_LOW);
88   - set_irq_type(AU1500_GPIO_207, IRQF_TRIGGER_LOW);
  83 + set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
  84 + set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
  85 + set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
  86 + set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
  87 + set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
  88 + set_irq_type(AU1500_GPIO207_INT, IRQF_TRIGGER_LOW);
89 89  
90   - set_irq_type(AU1000_GPIO_0, IRQF_TRIGGER_LOW);
91   - set_irq_type(AU1000_GPIO_1, IRQF_TRIGGER_LOW);
92   - set_irq_type(AU1000_GPIO_2, IRQF_TRIGGER_LOW);
93   - set_irq_type(AU1000_GPIO_3, IRQF_TRIGGER_LOW);
94   - set_irq_type(AU1000_GPIO_4, IRQF_TRIGGER_LOW); /* CF interrupt */
95   - set_irq_type(AU1000_GPIO_5, IRQF_TRIGGER_LOW);
  90 + set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW);
  91 + set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW);
  92 + set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW);
  93 + set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW);
  94 + set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* CF irq */
  95 + set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW);
96 96  
97 97 return 0;
98 98 }
arch/mips/include/asm/mach-au1x00/au1000.h
Diff comments   View file @ 7881446
... ... @@ -174,6 +174,333 @@
174 174 void save_au1xxx_intctl(void);
175 175 void restore_au1xxx_intctl(void);
176 176  
  177 +
  178 +/* SOC Interrupt numbers */
  179 +
  180 +#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
  181 +#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
  182 +#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1)
  183 +#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
  184 +#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
  185 +
  186 +enum soc_au1000_ints {
  187 + AU1000_FIRST_INT = AU1000_INTC0_INT_BASE,
  188 + AU1000_UART0_INT = AU1000_FIRST_INT,
  189 + AU1000_UART1_INT,
  190 + AU1000_UART2_INT,
  191 + AU1000_UART3_INT,
  192 + AU1000_SSI0_INT,
  193 + AU1000_SSI1_INT,
  194 + AU1000_DMA_INT_BASE,
  195 +
  196 + AU1000_TOY_INT = AU1000_FIRST_INT + 14,
  197 + AU1000_TOY_MATCH0_INT,
  198 + AU1000_TOY_MATCH1_INT,
  199 + AU1000_TOY_MATCH2_INT,
  200 + AU1000_RTC_INT,
  201 + AU1000_RTC_MATCH0_INT,
  202 + AU1000_RTC_MATCH1_INT,
  203 + AU1000_RTC_MATCH2_INT,
  204 + AU1000_IRDA_TX_INT,
  205 + AU1000_IRDA_RX_INT,
  206 + AU1000_USB_DEV_REQ_INT,
  207 + AU1000_USB_DEV_SUS_INT,
  208 + AU1000_USB_HOST_INT,
  209 + AU1000_ACSYNC_INT,
  210 + AU1000_MAC0_DMA_INT,
  211 + AU1000_MAC1_DMA_INT,
  212 + AU1000_I2S_UO_INT,
  213 + AU1000_AC97C_INT,
  214 + AU1000_GPIO0_INT,
  215 + AU1000_GPIO1_INT,
  216 + AU1000_GPIO2_INT,
  217 + AU1000_GPIO3_INT,
  218 + AU1000_GPIO4_INT,
  219 + AU1000_GPIO5_INT,
  220 + AU1000_GPIO6_INT,
  221 + AU1000_GPIO7_INT,
  222 + AU1000_GPIO8_INT,
  223 + AU1000_GPIO9_INT,
  224 + AU1000_GPIO10_INT,
  225 + AU1000_GPIO11_INT,
  226 + AU1000_GPIO12_INT,
  227 + AU1000_GPIO13_INT,
  228 + AU1000_GPIO14_INT,
  229 + AU1000_GPIO15_INT,
  230 + AU1000_GPIO16_INT,
  231 + AU1000_GPIO17_INT,
  232 + AU1000_GPIO18_INT,
  233 + AU1000_GPIO19_INT,
  234 + AU1000_GPIO20_INT,
  235 + AU1000_GPIO21_INT,
  236 + AU1000_GPIO22_INT,
  237 + AU1000_GPIO23_INT,
  238 + AU1000_GPIO24_INT,
  239 + AU1000_GPIO25_INT,
  240 + AU1000_GPIO26_INT,
  241 + AU1000_GPIO27_INT,
  242 + AU1000_GPIO28_INT,
  243 + AU1000_GPIO29_INT,
  244 + AU1000_GPIO30_INT,
  245 + AU1000_GPIO31_INT,
  246 +};
  247 +
  248 +enum soc_au1100_ints {
  249 + AU1100_FIRST_INT = AU1000_INTC0_INT_BASE,
  250 + AU1100_UART0_INT = AU1100_FIRST_INT,
  251 + AU1100_UART1_INT,
  252 + AU1100_SD_INT,
  253 + AU1100_UART3_INT,
  254 + AU1100_SSI0_INT,
  255 + AU1100_SSI1_INT,
  256 + AU1100_DMA_INT_BASE,
  257 +
  258 + AU1100_TOY_INT = AU1100_FIRST_INT + 14,
  259 + AU1100_TOY_MATCH0_INT,
  260 + AU1100_TOY_MATCH1_INT,
  261 + AU1100_TOY_MATCH2_INT,
  262 + AU1100_RTC_INT,
  263 + AU1100_RTC_MATCH0_INT,
  264 + AU1100_RTC_MATCH1_INT,
  265 + AU1100_RTC_MATCH2_INT,
  266 + AU1100_IRDA_TX_INT,
  267 + AU1100_IRDA_RX_INT,
  268 + AU1100_USB_DEV_REQ_INT,
  269 + AU1100_USB_DEV_SUS_INT,
  270 + AU1100_USB_HOST_INT,
  271 + AU1100_ACSYNC_INT,
  272 + AU1100_MAC0_DMA_INT,
  273 + AU1100_GPIO208_215_INT,
  274 + AU1100_LCD_INT,
  275 + AU1100_AC97C_INT,
  276 + AU1100_GPIO0_INT,
  277 + AU1100_GPIO1_INT,
  278 + AU1100_GPIO2_INT,
  279 + AU1100_GPIO3_INT,
  280 + AU1100_GPIO4_INT,
  281 + AU1100_GPIO5_INT,
  282 + AU1100_GPIO6_INT,
  283 + AU1100_GPIO7_INT,
  284 + AU1100_GPIO8_INT,
  285 + AU1100_GPIO9_INT,
  286 + AU1100_GPIO10_INT,
  287 + AU1100_GPIO11_INT,
  288 + AU1100_GPIO12_INT,
  289 + AU1100_GPIO13_INT,
  290 + AU1100_GPIO14_INT,
  291 + AU1100_GPIO15_INT,
  292 + AU1100_GPIO16_INT,
  293 + AU1100_GPIO17_INT,
  294 + AU1100_GPIO18_INT,
  295 + AU1100_GPIO19_INT,
  296 + AU1100_GPIO20_INT,
  297 + AU1100_GPIO21_INT,
  298 + AU1100_GPIO22_INT,
  299 + AU1100_GPIO23_INT,
  300 + AU1100_GPIO24_INT,
  301 + AU1100_GPIO25_INT,
  302 + AU1100_GPIO26_INT,
  303 + AU1100_GPIO27_INT,
  304 + AU1100_GPIO28_INT,
  305 + AU1100_GPIO29_INT,
  306 + AU1100_GPIO30_INT,
  307 + AU1100_GPIO31_INT,
  308 +};
  309 +
  310 +enum soc_au1500_ints {
  311 + AU1500_FIRST_INT = AU1000_INTC0_INT_BASE,
  312 + AU1500_UART0_INT = AU1500_FIRST_INT,
  313 + AU1500_PCI_INTA,
  314 + AU1500_PCI_INTB,
  315 + AU1500_UART3_INT,
  316 + AU1500_PCI_INTC,
  317 + AU1500_PCI_INTD,
  318 + AU1500_DMA_INT_BASE,
  319 +
  320 + AU1500_TOY_INT = AU1500_FIRST_INT + 14,
  321 + AU1500_TOY_MATCH0_INT,
  322 + AU1500_TOY_MATCH1_INT,
  323 + AU1500_TOY_MATCH2_INT,
  324 + AU1500_RTC_INT,
  325 + AU1500_RTC_MATCH0_INT,
  326 + AU1500_RTC_MATCH1_INT,
  327 + AU1500_RTC_MATCH2_INT,
  328 + AU1500_PCI_ERR_INT,
  329 + AU1500_RESERVED_INT,
  330 + AU1500_USB_DEV_REQ_INT,
  331 + AU1500_USB_DEV_SUS_INT,
  332 + AU1500_USB_HOST_INT,
  333 + AU1500_ACSYNC_INT,
  334 + AU1500_MAC0_DMA_INT,
  335 + AU1500_MAC1_DMA_INT,
  336 + AU1500_AC97C_INT = AU1500_FIRST_INT + 31,
  337 + AU1500_GPIO0_INT,
  338 + AU1500_GPIO1_INT,
  339 + AU1500_GPIO2_INT,
  340 + AU1500_GPIO3_INT,
  341 + AU1500_GPIO4_INT,
  342 + AU1500_GPIO5_INT,
  343 + AU1500_GPIO6_INT,
  344 + AU1500_GPIO7_INT,
  345 + AU1500_GPIO8_INT,
  346 + AU1500_GPIO9_INT,
  347 + AU1500_GPIO10_INT,
  348 + AU1500_GPIO11_INT,
  349 + AU1500_GPIO12_INT,
  350 + AU1500_GPIO13_INT,
  351 + AU1500_GPIO14_INT,
  352 + AU1500_GPIO15_INT,
  353 + AU1500_GPIO200_INT,
  354 + AU1500_GPIO201_INT,
  355 + AU1500_GPIO202_INT,
  356 + AU1500_GPIO203_INT,
  357 + AU1500_GPIO20_INT,
  358 + AU1500_GPIO204_INT,
  359 + AU1500_GPIO205_INT,
  360 + AU1500_GPIO23_INT,
  361 + AU1500_GPIO24_INT,
  362 + AU1500_GPIO25_INT,
  363 + AU1500_GPIO26_INT,
  364 + AU1500_GPIO27_INT,
  365 + AU1500_GPIO28_INT,
  366 + AU1500_GPIO206_INT,
  367 + AU1500_GPIO207_INT,
  368 + AU1500_GPIO208_215_INT,
  369 +};
  370 +
  371 +enum soc_au1550_ints {
  372 + AU1550_FIRST_INT = AU1000_INTC0_INT_BASE,
  373 + AU1550_UART0_INT = AU1550_FIRST_INT,
  374 + AU1550_PCI_INTA,
  375 + AU1550_PCI_INTB,
  376 + AU1550_DDMA_INT,
  377 + AU1550_CRYPTO_INT,
  378 + AU1550_PCI_INTC,
  379 + AU1550_PCI_INTD,
  380 + AU1550_PCI_RST_INT,
  381 + AU1550_UART1_INT,
  382 + AU1550_UART3_INT,
  383 + AU1550_PSC0_INT,
  384 + AU1550_PSC1_INT,
  385 + AU1550_PSC2_INT,
  386 + AU1550_PSC3_INT,
  387 + AU1550_TOY_INT,
  388 + AU1550_TOY_MATCH0_INT,
  389 + AU1550_TOY_MATCH1_INT,
  390 + AU1550_TOY_MATCH2_INT,
  391 + AU1550_RTC_INT,
  392 + AU1550_RTC_MATCH0_INT,
  393 + AU1550_RTC_MATCH1_INT,
  394 + AU1550_RTC_MATCH2_INT,
  395 +
  396 + AU1550_NAND_INT = AU1550_FIRST_INT + 23,
  397 + AU1550_USB_DEV_REQ_INT,
  398 + AU1550_USB_DEV_SUS_INT,
  399 + AU1550_USB_HOST_INT,
  400 + AU1550_MAC0_DMA_INT,
  401 + AU1550_MAC1_DMA_INT,
  402 + AU1550_GPIO0_INT = AU1550_FIRST_INT + 32,
  403 + AU1550_GPIO1_INT,
  404 + AU1550_GPIO2_INT,
  405 + AU1550_GPIO3_INT,
  406 + AU1550_GPIO4_INT,
  407 + AU1550_GPIO5_INT,
  408 + AU1550_GPIO6_INT,
  409 + AU1550_GPIO7_INT,
  410 + AU1550_GPIO8_INT,
  411 + AU1550_GPIO9_INT,
  412 + AU1550_GPIO10_INT,
  413 + AU1550_GPIO11_INT,
  414 + AU1550_GPIO12_INT,
  415 + AU1550_GPIO13_INT,
  416 + AU1550_GPIO14_INT,
  417 + AU1550_GPIO15_INT,
  418 + AU1550_GPIO200_INT,
  419 + AU1550_GPIO201_205_INT, /* Logical or of GPIO201:205 */
  420 + AU1550_GPIO16_INT,
  421 + AU1550_GPIO17_INT,
  422 + AU1550_GPIO20_INT,
  423 + AU1550_GPIO21_INT,
  424 + AU1550_GPIO22_INT,
  425 + AU1550_GPIO23_INT,
  426 + AU1550_GPIO24_INT,
  427 + AU1550_GPIO25_INT,
  428 + AU1550_GPIO26_INT,
  429 + AU1550_GPIO27_INT,
  430 + AU1550_GPIO28_INT,
  431 + AU1550_GPIO206_INT,
  432 + AU1550_GPIO207_INT,
  433 + AU1550_GPIO208_215_INT, /* Logical or of GPIO208:215 */
  434 +};
  435 +
  436 +enum soc_au1200_ints {
  437 + AU1200_FIRST_INT = AU1000_INTC0_INT_BASE,
  438 + AU1200_UART0_INT = AU1200_FIRST_INT,
  439 + AU1200_SWT_INT,
  440 + AU1200_SD_INT,
  441 + AU1200_DDMA_INT,
  442 + AU1200_MAE_BE_INT,
  443 + AU1200_GPIO200_INT,
  444 + AU1200_GPIO201_INT,
  445 + AU1200_GPIO202_INT,
  446 + AU1200_UART1_INT,
  447 + AU1200_MAE_FE_INT,
  448 + AU1200_PSC0_INT,
  449 + AU1200_PSC1_INT,
  450 + AU1200_AES_INT,
  451 + AU1200_CAMERA_INT,
  452 + AU1200_TOY_INT,
  453 + AU1200_TOY_MATCH0_INT,
  454 + AU1200_TOY_MATCH1_INT,
  455 + AU1200_TOY_MATCH2_INT,
  456 + AU1200_RTC_INT,
  457 + AU1200_RTC_MATCH0_INT,
  458 + AU1200_RTC_MATCH1_INT,
  459 + AU1200_RTC_MATCH2_INT,
  460 + AU1200_GPIO203_INT,
  461 + AU1200_NAND_INT,
  462 + AU1200_GPIO204_INT,
  463 + AU1200_GPIO205_INT,
  464 + AU1200_GPIO206_INT,
  465 + AU1200_GPIO207_INT,
  466 + AU1200_GPIO208_215_INT, /* Logical OR of 208:215 */
  467 + AU1200_USB_INT,
  468 + AU1200_LCD_INT,
  469 + AU1200_MAE_BOTH_INT,
  470 + AU1200_GPIO0_INT,
  471 + AU1200_GPIO1_INT,
  472 + AU1200_GPIO2_INT,
  473 + AU1200_GPIO3_INT,
  474 + AU1200_GPIO4_INT,
  475 + AU1200_GPIO5_INT,
  476 + AU1200_GPIO6_INT,
  477 + AU1200_GPIO7_INT,
  478 + AU1200_GPIO8_INT,
  479 + AU1200_GPIO9_INT,
  480 + AU1200_GPIO10_INT,
  481 + AU1200_GPIO11_INT,
  482 + AU1200_GPIO12_INT,
  483 + AU1200_GPIO13_INT,
  484 + AU1200_GPIO14_INT,
  485 + AU1200_GPIO15_INT,
  486 + AU1200_GPIO16_INT,
  487 + AU1200_GPIO17_INT,
  488 + AU1200_GPIO18_INT,
  489 + AU1200_GPIO19_INT,
  490 + AU1200_GPIO20_INT,
  491 + AU1200_GPIO21_INT,
  492 + AU1200_GPIO22_INT,
  493 + AU1200_GPIO23_INT,
  494 + AU1200_GPIO24_INT,
  495 + AU1200_GPIO25_INT,
  496 + AU1200_GPIO26_INT,
  497 + AU1200_GPIO27_INT,
  498 + AU1200_GPIO28_INT,
  499 + AU1200_GPIO29_INT,
  500 + AU1200_GPIO30_INT,
  501 + AU1200_GPIO31_INT,
  502 +};
  503 +
177 504 #endif /* !defined (_LANGUAGE_ASSEMBLY) */
178 505  
179 506 /*
180 507  
181 508  
... ... @@ -565,71 +892,10 @@
565 892  
566 893 #define IC1_TESTBIT 0xB1800080
567 894  
568   -/* Interrupt Numbers */
  895 +
569 896 /* Au1000 */
570 897 #ifdef CONFIG_SOC_AU1000
571   -enum soc_au1000_ints {
572   - AU1000_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
573   - AU1000_UART0_INT = AU1000_FIRST_INT,
574   - AU1000_UART1_INT, /* au1000 */
575   - AU1000_UART2_INT, /* au1000 */
576   - AU1000_UART3_INT,
577   - AU1000_SSI0_INT, /* au1000 */
578   - AU1000_SSI1_INT, /* au1000 */
579   - AU1000_DMA_INT_BASE,
580 898  
581   - AU1000_TOY_INT = AU1000_FIRST_INT + 14,
582   - AU1000_TOY_MATCH0_INT,
583   - AU1000_TOY_MATCH1_INT,
584   - AU1000_TOY_MATCH2_INT,
585   - AU1000_RTC_INT,
586   - AU1000_RTC_MATCH0_INT,
587   - AU1000_RTC_MATCH1_INT,
588   - AU1000_RTC_MATCH2_INT,
589   - AU1000_IRDA_TX_INT, /* au1000 */
590   - AU1000_IRDA_RX_INT, /* au1000 */
591   - AU1000_USB_DEV_REQ_INT,
592   - AU1000_USB_DEV_SUS_INT,
593   - AU1000_USB_HOST_INT,
594   - AU1000_ACSYNC_INT,
595   - AU1000_MAC0_DMA_INT,
596   - AU1000_MAC1_DMA_INT,
597   - AU1000_I2S_UO_INT, /* au1000 */
598   - AU1000_AC97C_INT,
599   - AU1000_GPIO_0,
600   - AU1000_GPIO_1,
601   - AU1000_GPIO_2,
602   - AU1000_GPIO_3,
603   - AU1000_GPIO_4,
604   - AU1000_GPIO_5,
605   - AU1000_GPIO_6,
606   - AU1000_GPIO_7,
607   - AU1000_GPIO_8,
608   - AU1000_GPIO_9,
609   - AU1000_GPIO_10,
610   - AU1000_GPIO_11,
611   - AU1000_GPIO_12,
612   - AU1000_GPIO_13,
613   - AU1000_GPIO_14,
614   - AU1000_GPIO_15,
615   - AU1000_GPIO_16,
616   - AU1000_GPIO_17,
617   - AU1000_GPIO_18,
618   - AU1000_GPIO_19,
619   - AU1000_GPIO_20,
620   - AU1000_GPIO_21,
621   - AU1000_GPIO_22,
622   - AU1000_GPIO_23,
623   - AU1000_GPIO_24,
624   - AU1000_GPIO_25,
625   - AU1000_GPIO_26,
626   - AU1000_GPIO_27,
627   - AU1000_GPIO_28,
628   - AU1000_GPIO_29,
629   - AU1000_GPIO_30,
630   - AU1000_GPIO_31,
631   -};
632   -
633 899 #define UART0_ADDR 0xB1100000
634 900 #define UART1_ADDR 0xB1200000
635 901 #define UART2_ADDR 0xB1300000
... ... @@ -637,6 +903,7 @@
637 903  
638 904 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
639 905 #define USB_HOST_CONFIG 0xB017FFFC
  906 +#define FOR_PLATFORM_C_USB_HOST_INT AU1000_USB_HOST_INT
640 907  
641 908 #define AU1000_ETH0_BASE 0xB0500000
642 909 #define AU1000_ETH1_BASE 0xB0510000
643 910  
644 911  
... ... @@ -647,78 +914,13 @@
647 914  
648 915 /* Au1500 */
649 916 #ifdef CONFIG_SOC_AU1500
650   -enum soc_au1500_ints {
651   - AU1500_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
652   - AU1500_UART0_INT = AU1500_FIRST_INT,
653   - AU1000_PCI_INTA, /* au1500 */
654   - AU1000_PCI_INTB, /* au1500 */
655   - AU1500_UART3_INT,
656   - AU1000_PCI_INTC, /* au1500 */
657   - AU1000_PCI_INTD, /* au1500 */
658   - AU1000_DMA_INT_BASE,
659 917  
660   - AU1000_TOY_INT = AU1500_FIRST_INT + 14,
661   - AU1000_TOY_MATCH0_INT,
662   - AU1000_TOY_MATCH1_INT,
663   - AU1000_TOY_MATCH2_INT,
664   - AU1000_RTC_INT,
665   - AU1000_RTC_MATCH0_INT,
666   - AU1000_RTC_MATCH1_INT,
667   - AU1000_RTC_MATCH2_INT,
668   - AU1500_PCI_ERR_INT,
669   - AU1500_RESERVED_INT,
670   - AU1000_USB_DEV_REQ_INT,
671   - AU1000_USB_DEV_SUS_INT,
672   - AU1000_USB_HOST_INT,
673   - AU1000_ACSYNC_INT,
674   - AU1500_MAC0_DMA_INT,
675   - AU1500_MAC1_DMA_INT,
676   - AU1000_AC97C_INT = AU1500_FIRST_INT + 31,
677   - AU1000_GPIO_0,
678   - AU1000_GPIO_1,
679   - AU1000_GPIO_2,
680   - AU1000_GPIO_3,
681   - AU1000_GPIO_4,
682   - AU1000_GPIO_5,
683   - AU1000_GPIO_6,
684   - AU1000_GPIO_7,
685   - AU1000_GPIO_8,
686   - AU1000_GPIO_9,
687   - AU1000_GPIO_10,
688   - AU1000_GPIO_11,
689   - AU1000_GPIO_12,
690   - AU1000_GPIO_13,
691   - AU1000_GPIO_14,
692   - AU1000_GPIO_15,
693   - AU1500_GPIO_200,
694   - AU1500_GPIO_201,
695   - AU1500_GPIO_202,
696   - AU1500_GPIO_203,
697   - AU1500_GPIO_20,
698   - AU1500_GPIO_204,
699   - AU1500_GPIO_205,
700   - AU1500_GPIO_23,
701   - AU1500_GPIO_24,
702   - AU1500_GPIO_25,
703   - AU1500_GPIO_26,
704   - AU1500_GPIO_27,
705   - AU1500_GPIO_28,
706   - AU1500_GPIO_206,
707   - AU1500_GPIO_207,
708   - AU1500_GPIO_208_215,
709   -};
710   -
711   -/* shortcuts */
712   -#define INTA AU1000_PCI_INTA
713   -#define INTB AU1000_PCI_INTB
714   -#define INTC AU1000_PCI_INTC
715   -#define INTD AU1000_PCI_INTD
716   -
717 918 #define UART0_ADDR 0xB1100000
718 919 #define UART3_ADDR 0xB1400000
719 920  
720 921 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
721 922 #define USB_HOST_CONFIG 0xB017fffc
  923 +#define FOR_PLATFORM_C_USB_HOST_INT AU1500_USB_HOST_INT
722 924  
723 925 #define AU1500_ETH0_BASE 0xB1500000
724 926 #define AU1500_ETH1_BASE 0xB1510000
725 927  
726 928  
... ... @@ -729,74 +931,14 @@
729 931  
730 932 /* Au1100 */
731 933 #ifdef CONFIG_SOC_AU1100
732   -enum soc_au1100_ints {
733   - AU1100_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
734   - AU1100_UART0_INT = AU1100_FIRST_INT,
735   - AU1100_UART1_INT,
736   - AU1100_SD_INT,
737   - AU1100_UART3_INT,
738   - AU1000_SSI0_INT,
739   - AU1000_SSI1_INT,
740   - AU1000_DMA_INT_BASE,
741 934  
742   - AU1000_TOY_INT = AU1100_FIRST_INT + 14,
743   - AU1000_TOY_MATCH0_INT,
744   - AU1000_TOY_MATCH1_INT,
745   - AU1000_TOY_MATCH2_INT,
746   - AU1000_RTC_INT,
747   - AU1000_RTC_MATCH0_INT,
748   - AU1000_RTC_MATCH1_INT,
749   - AU1000_RTC_MATCH2_INT,
750   - AU1000_IRDA_TX_INT,
751   - AU1000_IRDA_RX_INT,
752   - AU1000_USB_DEV_REQ_INT,
753   - AU1000_USB_DEV_SUS_INT,
754   - AU1000_USB_HOST_INT,
755   - AU1000_ACSYNC_INT,
756   - AU1100_MAC0_DMA_INT,
757   - AU1100_GPIO_208_215,
758   - AU1100_LCD_INT,
759   - AU1000_AC97C_INT,
760   - AU1000_GPIO_0,
761   - AU1000_GPIO_1,
762   - AU1000_GPIO_2,
763   - AU1000_GPIO_3,
764   - AU1000_GPIO_4,
765   - AU1000_GPIO_5,
766   - AU1000_GPIO_6,
767   - AU1000_GPIO_7,
768   - AU1000_GPIO_8,
769   - AU1000_GPIO_9,
770   - AU1000_GPIO_10,
771   - AU1000_GPIO_11,
772   - AU1000_GPIO_12,
773   - AU1000_GPIO_13,
774   - AU1000_GPIO_14,
775   - AU1000_GPIO_15,
776   - AU1000_GPIO_16,
777   - AU1000_GPIO_17,
778   - AU1000_GPIO_18,
779   - AU1000_GPIO_19,
780   - AU1000_GPIO_20,
781   - AU1000_GPIO_21,
782   - AU1000_GPIO_22,
783   - AU1000_GPIO_23,
784   - AU1000_GPIO_24,
785   - AU1000_GPIO_25,
786   - AU1000_GPIO_26,
787   - AU1000_GPIO_27,
788   - AU1000_GPIO_28,
789   - AU1000_GPIO_29,
790   - AU1000_GPIO_30,
791   - AU1000_GPIO_31,
792   -};
793   -
794 935 #define UART0_ADDR 0xB1100000
795 936 #define UART1_ADDR 0xB1200000
796 937 #define UART3_ADDR 0xB1400000
797 938  
798 939 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
799 940 #define USB_HOST_CONFIG 0xB017FFFC
  941 +#define FOR_PLATFORM_C_USB_HOST_INT AU1100_USB_HOST_INT
800 942  
801 943 #define AU1100_ETH0_BASE 0xB0500000
802 944 #define AU1100_MAC0_ENABLE 0xB0520000
... ... @@ -804,80 +946,6 @@
804 946 #endif /* CONFIG_SOC_AU1100 */
805 947  
806 948 #ifdef CONFIG_SOC_AU1550
807   -enum soc_au1550_ints {
808   - AU1550_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
809   - AU1550_UART0_INT = AU1550_FIRST_INT,
810   - AU1550_PCI_INTA,
811   - AU1550_PCI_INTB,
812   - AU1550_DDMA_INT,
813   - AU1550_CRYPTO_INT,
814   - AU1550_PCI_INTC,
815   - AU1550_PCI_INTD,
816   - AU1550_PCI_RST_INT,
817   - AU1550_UART1_INT,
818   - AU1550_UART3_INT,
819   - AU1550_PSC0_INT,
820   - AU1550_PSC1_INT,
821   - AU1550_PSC2_INT,
822   - AU1550_PSC3_INT,
823   - AU1000_TOY_INT,
824   - AU1000_TOY_MATCH0_INT,
825   - AU1000_TOY_MATCH1_INT,
826   - AU1000_TOY_MATCH2_INT,
827   - AU1000_RTC_INT,
828   - AU1000_RTC_MATCH0_INT,
829   - AU1000_RTC_MATCH1_INT,
830   - AU1000_RTC_MATCH2_INT,
831   -
832   - AU1550_NAND_INT = AU1550_FIRST_INT + 23,
833   - AU1550_USB_DEV_REQ_INT,
834   - AU1000_USB_DEV_REQ_INT = AU1550_USB_DEV_REQ_INT,
835   - AU1550_USB_DEV_SUS_INT,
836   - AU1000_USB_DEV_SUS_INT = AU1550_USB_DEV_SUS_INT,
837   - AU1550_USB_HOST_INT,
838   - AU1000_USB_HOST_INT = AU1550_USB_HOST_INT,
839   - AU1550_MAC0_DMA_INT,
840   - AU1550_MAC1_DMA_INT,
841   - AU1000_GPIO_0 = AU1550_FIRST_INT + 32,
842   - AU1000_GPIO_1,
843   - AU1000_GPIO_2,
844   - AU1000_GPIO_3,
845   - AU1000_GPIO_4,
846   - AU1000_GPIO_5,
847   - AU1000_GPIO_6,
848   - AU1000_GPIO_7,
849   - AU1000_GPIO_8,
850   - AU1000_GPIO_9,
851   - AU1000_GPIO_10,
852   - AU1000_GPIO_11,
853   - AU1000_GPIO_12,
854   - AU1000_GPIO_13,
855   - AU1000_GPIO_14,
856   - AU1000_GPIO_15,
857   - AU1550_GPIO_200,
858   - AU1500_GPIO_201_205, /* Logical or of GPIO201:205 */
859   - AU1500_GPIO_16,
860   - AU1500_GPIO_17,
861   - AU1500_GPIO_20,
862   - AU1500_GPIO_21,
863   - AU1500_GPIO_22,
864   - AU1500_GPIO_23,
865   - AU1500_GPIO_24,
866   - AU1500_GPIO_25,
867   - AU1500_GPIO_26,
868   - AU1500_GPIO_27,
869   - AU1500_GPIO_28,
870   - AU1500_GPIO_206,
871   - AU1500_GPIO_207,
872   - AU1500_GPIO_208_218, /* Logical or of GPIO208:218 */
873   -};
874   -
875   -/* shortcuts */
876   -#define INTA AU1550_PCI_INTA
877   -#define INTB AU1550_PCI_INTB
878   -#define INTC AU1550_PCI_INTC
879   -#define INTD AU1550_PCI_INTD
880   -
881 949 #define UART0_ADDR 0xB1100000
882 950 #define UART1_ADDR 0xB1200000
883 951 #define UART3_ADDR 0xB1400000
... ... @@ -885,6 +953,7 @@
885 953 #define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */
886 954 #define USB_OHCI_LEN 0x00060000
887 955 #define USB_HOST_CONFIG 0xB4027ffc
  956 +#define FOR_PLATFORM_C_USB_HOST_INT AU1550_USB_HOST_INT
888 957  
889 958 #define AU1550_ETH0_BASE 0xB0500000
890 959 #define AU1550_ETH1_BASE 0xB0510000
891 960  
... ... @@ -893,75 +962,8 @@
893 962 #define NUM_ETH_INTERFACES 2
894 963 #endif /* CONFIG_SOC_AU1550 */
895 964  
  965 +
896 966 #ifdef CONFIG_SOC_AU1200
897   -enum soc_au1200_ints {
898   - AU1200_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
899   - AU1200_UART0_INT = AU1200_FIRST_INT,
900   - AU1200_SWT_INT,
901   - AU1200_SD_INT,
902   - AU1200_DDMA_INT,
903   - AU1200_MAE_BE_INT,
904   - AU1200_GPIO_200,
905   - AU1200_GPIO_201,
906   - AU1200_GPIO_202,
907   - AU1200_UART1_INT,
908   - AU1200_MAE_FE_INT,
909   - AU1200_PSC0_INT,
910   - AU1200_PSC1_INT,
911   - AU1200_AES_INT,
912   - AU1200_CAMERA_INT,
913   - AU1000_TOY_INT,
914   - AU1000_TOY_MATCH0_INT,
915   - AU1000_TOY_MATCH1_INT,
916   - AU1000_TOY_MATCH2_INT,
917   - AU1000_RTC_INT,
918   - AU1000_RTC_MATCH0_INT,
919   - AU1000_RTC_MATCH1_INT,
920   - AU1000_RTC_MATCH2_INT,
921   - AU1200_GPIO_203,
922   - AU1200_NAND_INT,
923   - AU1200_GPIO_204,
924   - AU1200_GPIO_205,
925   - AU1200_GPIO_206,
926   - AU1200_GPIO_207,
927   - AU1200_GPIO_208_215, /* Logical OR of 208:215 */
928   - AU1200_USB_INT,
929   - AU1000_USB_HOST_INT = AU1200_USB_INT,
930   - AU1200_LCD_INT,
931   - AU1200_MAE_BOTH_INT,
932   - AU1000_GPIO_0,
933   - AU1000_GPIO_1,
934   - AU1000_GPIO_2,
935   - AU1000_GPIO_3,
936   - AU1000_GPIO_4,
937   - AU1000_GPIO_5,
938   - AU1000_GPIO_6,
939   - AU1000_GPIO_7,
940   - AU1000_GPIO_8,
941   - AU1000_GPIO_9,
942   - AU1000_GPIO_10,
943   - AU1000_GPIO_11,
944   - AU1000_GPIO_12,
945   - AU1000_GPIO_13,
946   - AU1000_GPIO_14,
947   - AU1000_GPIO_15,
948   - AU1000_GPIO_16,
949   - AU1000_GPIO_17,
950   - AU1000_GPIO_18,
951   - AU1000_GPIO_19,
952   - AU1000_GPIO_20,
953   - AU1000_GPIO_21,
954   - AU1000_GPIO_22,
955   - AU1000_GPIO_23,
956   - AU1000_GPIO_24,
957   - AU1000_GPIO_25,
958   - AU1000_GPIO_26,
959   - AU1000_GPIO_27,
960   - AU1000_GPIO_28,
961   - AU1000_GPIO_29,
962   - AU1000_GPIO_30,
963   - AU1000_GPIO_31,
964   -};
965 967  
966 968 #define UART0_ADDR 0xB1100000
967 969 #define UART1_ADDR 0xB1200000
968 970  
... ... @@ -990,15 +992,9 @@
990 992 #define USBMSRMCFG_RDCOMB 30
991 993 #define USBMSRMCFG_PFEN 31
992 994  
993   -#endif /* CONFIG_SOC_AU1200 */
  995 +#define FOR_PLATFORM_C_USB_HOST_INT AU1200_USB_INT
994 996  
995   -#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
996   -#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
997   -#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_BASE + 32)
998   -#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
999   -
1000   -#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
1001   -#define INTX 0xFF /* not valid */
  997 +#endif /* CONFIG_SOC_AU1200 */
1002 998  
1003 999 /* Programmable Counters 0 and 1 */
1004 1000 #define SYS_BASE 0xB1900000
arch/mips/include/asm/mach-au1x00/gpio-au1000.h
Diff comments   View file @ 7881446
... ... @@ -35,15 +35,13 @@
35 35 return -ENXIO;
36 36 }
37 37  
38   -#ifdef CONFIG_SOC_AU1000
39 38 static inline int au1000_irq_to_gpio(int irq)
40 39 {
41   - if ((irq >= AU1000_GPIO_0) && (irq <= AU1000_GPIO_31))
42   - return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
  40 + if ((irq >= AU1000_GPIO0_INT) && (irq <= AU1000_GPIO31_INT))
  41 + return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO0_INT) + 0;
43 42  
44 43 return -ENXIO;
45 44 }
46   -#endif
47 45  
48 46 static inline int au1500_gpio1_to_irq(int gpio)
49 47 {
50 48  
51 49  
... ... @@ -71,27 +69,25 @@
71 69 return -ENXIO;
72 70 }
73 71  
74   -#ifdef CONFIG_SOC_AU1500
75 72 static inline int au1500_irq_to_gpio(int irq)
76 73 {
77 74 switch (irq) {
78   - case AU1000_GPIO_0 ... AU1000_GPIO_15:
79   - case AU1500_GPIO_20:
80   - case AU1500_GPIO_23 ... AU1500_GPIO_28:
81   - return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
82   - case AU1500_GPIO_200 ... AU1500_GPIO_203:
83   - return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_200) + 0;
84   - case AU1500_GPIO_204 ... AU1500_GPIO_205:
85   - return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_204) + 4;
86   - case AU1500_GPIO_206 ... AU1500_GPIO_207:
87   - return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_206) + 6;
88   - case AU1500_GPIO_208_215:
  75 + case AU1500_GPIO0_INT ... AU1500_GPIO15_INT:
  76 + case AU1500_GPIO20_INT:
  77 + case AU1500_GPIO23_INT ... AU1500_GPIO28_INT:
  78 + return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO0_INT) + 0;
  79 + case AU1500_GPIO200_INT ... AU1500_GPIO203_INT:
  80 + return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO200_INT) + 0;
  81 + case AU1500_GPIO204_INT ... AU1500_GPIO205_INT:
  82 + return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO204_INT) + 4;
  83 + case AU1500_GPIO206_INT ... AU1500_GPIO207_INT:
  84 + return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO206_INT) + 6;
  85 + case AU1500_GPIO208_215_INT:
89 86 return ALCHEMY_GPIO2_BASE + 8;
90 87 }
91 88  
92 89 return -ENXIO;
93 90 }
94   -#endif
95 91  
96 92 static inline int au1100_gpio1_to_irq(int gpio)
97 93 {
98 94  
99 95  
... ... @@ -108,19 +104,17 @@
108 104 return -ENXIO;
109 105 }
110 106  
111   -#ifdef CONFIG_SOC_AU1100
112 107 static inline int au1100_irq_to_gpio(int irq)
113 108 {
114 109 switch (irq) {
115   - case AU1000_GPIO_0 ... AU1000_GPIO_31:
116   - return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
117   - case AU1100_GPIO_208_215:
  110 + case AU1100_GPIO0_INT ... AU1100_GPIO31_INT:
  111 + return ALCHEMY_GPIO1_BASE + (irq - AU1100_GPIO0_INT) + 0;
  112 + case AU1100_GPIO208_215_INT:
118 113 return ALCHEMY_GPIO2_BASE + 8;
119 114 }
120 115  
121 116 return -ENXIO;
122 117 }
123   -#endif
124 118  
125 119 static inline int au1550_gpio1_to_irq(int gpio)
126 120 {
127 121  
128 122  
... ... @@ -149,24 +143,22 @@
149 143 return -ENXIO;
150 144 }
151 145  
152   -#ifdef CONFIG_SOC_AU1550
153 146 static inline int au1550_irq_to_gpio(int irq)
154 147 {
155 148 switch (irq) {
156   - case AU1000_GPIO_0 ... AU1000_GPIO_15:
157   - return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
158   - case AU1550_GPIO_200:
159   - case AU1500_GPIO_201_205:
160   - return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO_200) + 0;
161   - case AU1500_GPIO_16 ... AU1500_GPIO_28:
162   - return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO_16) + 16;
163   - case AU1500_GPIO_206 ... AU1500_GPIO_208_218:
164   - return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_206) + 6;
  149 + case AU1550_GPIO0_INT ... AU1550_GPIO15_INT:
  150 + return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO0_INT) + 0;
  151 + case AU1550_GPIO200_INT:
  152 + case AU1550_GPIO201_205_INT:
  153 + return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO200_INT) + 0;
  154 + case AU1550_GPIO16_INT ... AU1550_GPIO28_INT:
  155 + return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO16_INT) + 16;
  156 + case AU1550_GPIO206_INT ... AU1550_GPIO208_215_INT:
  157 + return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO206_INT) + 6;
165 158 }
166 159  
167 160 return -ENXIO;
168 161 }
169   -#endif
170 162  
171 163 static inline int au1200_gpio1_to_irq(int gpio)
172 164 {
173 165  
174 166  
175 167  
... ... @@ -187,23 +179,21 @@
187 179 return -ENXIO;
188 180 }
189 181  
190   -#ifdef CONFIG_SOC_AU1200
191 182 static inline int au1200_irq_to_gpio(int irq)
192 183 {
193 184 switch (irq) {
194   - case AU1000_GPIO_0 ... AU1000_GPIO_31:
195   - return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
196   - case AU1200_GPIO_200 ... AU1200_GPIO_202:
197   - return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO_200) + 0;
198   - case AU1200_GPIO_203:
  185 + case AU1200_GPIO0_INT ... AU1200_GPIO31_INT:
  186 + return ALCHEMY_GPIO1_BASE + (irq - AU1200_GPIO0_INT) + 0;
  187 + case AU1200_GPIO200_INT ... AU1200_GPIO202_INT:
  188 + return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO200_INT) + 0;
  189 + case AU1200_GPIO203_INT:
199 190 return ALCHEMY_GPIO2_BASE + 3;
200   - case AU1200_GPIO_204 ... AU1200_GPIO_208_215:
201   - return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO_204) + 4;
  191 + case AU1200_GPIO204_INT ... AU1200_GPIO208_215_INT:
  192 + return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO204_INT) + 4;
202 193 }
203 194  
204 195 return -ENXIO;
205 196 }
206   -#endif
207 197  
208 198 /*
209 199 * GPIO1 block macros for common linux gpio functions.