watchdog: w83627hf: Add support for W83697HF and W83697UG

Major difference is that the watchdog control and counter registers are different on both chips. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>

watchdog: w83627hf: Add support for W83697HF and W83697UG
Major difference is that the watchdog control and counter registers are different on both chips. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
Guenter Roeck · Wim Van Sebroeck
1 parent 962c04f54e
Showing 2 changed files with 51 additions and 13 deletions Side-by-side Diff
drivers/watchdog/Kconfig
drivers/watchdog/w83627hf_wdt.c
@@ -902,6 +902,8 @@
 		W83637HF
 		W83667HG/HG-B
 		W83687THF
+		W83697HF
+		W83697UG
 		NCT6775
 		NCT6776
 		NCT6779
@@ -45,10 +45,12 @@
 #define WATCHDOG_TIMEOUT 60		/* 60 sec default timeout */
  
 static int wdt_io;
+static int cr_wdt_timeout;	/* WDT timeout register */
+static int cr_wdt_control;	/* WDT control register */
  
-enum chips { w83627hf, w83627s, w83637hf, w83627thf, w83687thf,
-	     w83627ehf, w83627dhg, w83627uhg, w83667hg, w83627dhg_p, w83667hg_b,
-	     nct6775, nct6776, nct6779 };
+enum chips { w83627hf, w83627s, w83697hf, w83697ug, w83637hf, w83627thf,
+	     w83687thf, w83627ehf, w83627dhg, w83627uhg, w83667hg, w83627dhg_p,
+	     w83667hg_b, nct6775, nct6776, nct6779 };
  
 static int timeout;			/* in seconds */
 module_param(timeout, int, 0);
@@ -75,6 +77,8 @@
  
 #define W83627HF_ID		0x52
 #define W83627S_ID		0x59
+#define W83697HF_ID		0x60
+#define W83697UG_ID		0x68
 #define W83637HF_ID		0x70
 #define W83627THF_ID		0x82
 #define W83687THF_ID		0x85
@@ -88,6 +92,12 @@
 #define NCT6776_ID		0xc3
 #define NCT6779_ID		0xc5
  
+#define W83627HF_WDT_TIMEOUT	0xf6
+#define W83697HF_WDT_TIMEOUT	0xf4
+
+#define W83627HF_WDT_CONTROL	0xf5
+#define W83697HF_WDT_CONTROL	0xf3
+
 static void superio_outb(int reg, int val)
 {
 	outb(reg, WDT_EFER);
@@ -144,6 +154,17 @@
 		t = superio_inb(0x2B) & ~0x10;
 		superio_outb(0x2B, t); /* set GPIO24 to WDT0 */
 		break;
+	case w83697hf:
+		/* Set pin 119 to WDTO# mode (= CR29, WDT0) */
+		t = superio_inb(0x29) & ~0x60;
+		t |= 0x20;
+		superio_outb(0x29, t);
+		break;
+	case w83697ug:
+		/* Set pin 118 to WDTO# mode */
+		t = superio_inb(0x2b) & ~0x04;
+		superio_outb(0x2b, t);
+		break;
 	case w83627thf:
 		t = (superio_inb(0x2B) & ~0x08) | 0x04;
 		superio_outb(0x2B, t); /* set GPIO3 to WDT0 */
  
@@ -152,10 +173,10 @@
 	case w83627dhg_p:
 		t = superio_inb(0x2D) & ~0x01; /* PIN77 -> WDT0# */
 		superio_outb(0x2D, t); /* set GPIO5 to WDT0 */
-		t = superio_inb(0xF5);
+		t = superio_inb(cr_wdt_control);
 		t |= 0x02;	/* enable the WDTO# output low pulse
 				 * to the KBRST# pin */
-		superio_outb(0xF5, t);
+		superio_outb(cr_wdt_control, t);
 		break;
 	case w83637hf:
 		break;
  
  
  
  
@@ -176,25 +197,25 @@
 		 * Don't touch its configuration, and hope the BIOS
 		 * does the right thing.
 		 */
-		t = superio_inb(0xF5);
+		t = superio_inb(cr_wdt_control);
 		t |= 0x02;	/* enable the WDTO# output low pulse
 				 * to the KBRST# pin */
-		superio_outb(0xF5, t);
+		superio_outb(cr_wdt_control, t);
 		break;
 	default:
 		break;
 	}
  
-	t = superio_inb(0xF6);
+	t = superio_inb(cr_wdt_timeout);
 	if (t != 0) {
 		pr_info("Watchdog already running. Resetting timeout to %d sec\n",
 			wdog->timeout);
-		superio_outb(0xF6, wdog->timeout);
+		superio_outb(cr_wdt_timeout, wdog->timeout);
 	}
  
 	/* set second mode & disable keyboard turning off watchdog */
-	t = superio_inb(0xF5) & ~0x0C;
-	superio_outb(0xF5, t);
+	t = superio_inb(cr_wdt_control) & ~0x0C;
+	superio_outb(cr_wdt_control, t);
  
 	/* disable keyboard & mouse turning off watchdog */
 	t = superio_inb(0xF7) & ~0xC0;
@@ -214,7 +235,7 @@
 		return ret;
  
 	superio_select(W83627HF_LD_WDT);
-	superio_outb(0xF6, timeout);
+	superio_outb(cr_wdt_timeout, timeout);
 	superio_exit();
  
 	return 0;
@@ -247,7 +268,7 @@
 		return 0;
  
 	superio_select(W83627HF_LD_WDT);
-	timeleft = superio_inb(0xF6);
+	timeleft = superio_inb(cr_wdt_timeout);
 	superio_exit();
  
 	return timeleft;
@@ -304,6 +325,9 @@
 	u8 val;
 	int ret;
  
+	cr_wdt_timeout = W83627HF_WDT_TIMEOUT;
+	cr_wdt_control = W83627HF_WDT_CONTROL;
+
 	ret = superio_enter();
 	if (ret)
 		return ret;
@@ -316,6 +340,16 @@
 	case W83627S_ID:
 		ret = w83627s;
 		break;
+	case W83697HF_ID:
+		ret = w83697hf;
+		cr_wdt_timeout = W83697HF_WDT_TIMEOUT;
+		cr_wdt_control = W83697HF_WDT_CONTROL;
+		break;
+	case W83697UG_ID:
+		ret = w83697ug;
+		cr_wdt_timeout = W83697HF_WDT_TIMEOUT;
+		cr_wdt_control = W83697HF_WDT_CONTROL;
+		break;
 	case W83637HF_ID:
 		ret = w83637hf;
 		break;
@@ -371,6 +405,8 @@
 	const char * const chip_name[] = {
 		"W83627HF",
 		"W83627S",
+		"W83697HF",
+		"W83697UG",
 		"W83637HF",
 		"W83627THF",
 		"W83687THF",
...	...	@@ -902,6 +902,8 @@
902	902	W83637HF
903	903	W83667HG/HG-B
904	904	W83687THF
	905	+ W83697HF
	906	+ W83697UG
905	907	NCT6775
906	908	NCT6776
907	909	NCT6779
...	...	@@ -45,10 +45,12 @@
45	45	#define WATCHDOG_TIMEOUT 60 /* 60 sec default timeout */
46	46
47	47	static int wdt_io;
	48	+static int cr_wdt_timeout; /* WDT timeout register */
	49	+static int cr_wdt_control; /* WDT control register */
48	50
49		-enum chips { w83627hf, w83627s, w83637hf, w83627thf, w83687thf,
50		- w83627ehf, w83627dhg, w83627uhg, w83667hg, w83627dhg_p, w83667hg_b,
51		- nct6775, nct6776, nct6779 };
	51	+enum chips { w83627hf, w83627s, w83697hf, w83697ug, w83637hf, w83627thf,
	52	+ w83687thf, w83627ehf, w83627dhg, w83627uhg, w83667hg, w83627dhg_p,
	53	+ w83667hg_b, nct6775, nct6776, nct6779 };
52	54
53	55	static int timeout; /* in seconds */
54	56	module_param(timeout, int, 0);
...	...	@@ -75,6 +77,8 @@
75	77
76	78	#define W83627HF_ID 0x52
77	79	#define W83627S_ID 0x59
	80	+#define W83697HF_ID 0x60
	81	+#define W83697UG_ID 0x68
78	82	#define W83637HF_ID 0x70
79	83	#define W83627THF_ID 0x82
80	84	#define W83687THF_ID 0x85
...	...	@@ -88,6 +92,12 @@
88	92	#define NCT6776_ID 0xc3
89	93	#define NCT6779_ID 0xc5
90	94
	95	+#define W83627HF_WDT_TIMEOUT 0xf6
	96	+#define W83697HF_WDT_TIMEOUT 0xf4
	97	+
	98	+#define W83627HF_WDT_CONTROL 0xf5
	99	+#define W83697HF_WDT_CONTROL 0xf3
	100	+
91	101	static void superio_outb(int reg, int val)
92	102	{
93	103	outb(reg, WDT_EFER);
...	...	@@ -144,6 +154,17 @@
144	154	t = superio_inb(0x2B) & ~0x10;
145	155	superio_outb(0x2B, t); /* set GPIO24 to WDT0 */
146	156	break;
	157	+ case w83697hf:
	158	+ /* Set pin 119 to WDTO# mode (= CR29, WDT0) */
	159	+ t = superio_inb(0x29) & ~0x60;
	160	+ t \|= 0x20;
	161	+ superio_outb(0x29, t);
	162	+ break;
	163	+ case w83697ug:
	164	+ /* Set pin 118 to WDTO# mode */
	165	+ t = superio_inb(0x2b) & ~0x04;
	166	+ superio_outb(0x2b, t);
	167	+ break;
147	168	case w83627thf:
148	169	t = (superio_inb(0x2B) & ~0x08) \| 0x04;
149	170	superio_outb(0x2B, t); /* set GPIO3 to WDT0 */
150	171
...	...	@@ -152,10 +173,10 @@
152	173	case w83627dhg_p:
153	174	t = superio_inb(0x2D) & ~0x01; /* PIN77 -> WDT0# */
154	175	superio_outb(0x2D, t); /* set GPIO5 to WDT0 */
155		- t = superio_inb(0xF5);
	176	+ t = superio_inb(cr_wdt_control);
156	177	t \|= 0x02; /* enable the WDTO# output low pulse
157	178	* to the KBRST# pin */
158		- superio_outb(0xF5, t);
	179	+ superio_outb(cr_wdt_control, t);
159	180	break;
160	181	case w83637hf:
161	182	break;
162	183
163	184
164	185
165	186
...	...	@@ -176,25 +197,25 @@
176	197	* Don't touch its configuration, and hope the BIOS
177	198	* does the right thing.
178	199	*/
179		- t = superio_inb(0xF5);
	200	+ t = superio_inb(cr_wdt_control);
180	201	t \|= 0x02; /* enable the WDTO# output low pulse
181	202	* to the KBRST# pin */
182		- superio_outb(0xF5, t);
	203	+ superio_outb(cr_wdt_control, t);
183	204	break;
184	205	default:
185	206	break;
186	207	}
187	208
188		- t = superio_inb(0xF6);
	209	+ t = superio_inb(cr_wdt_timeout);
189	210	if (t != 0) {
190	211	pr_info("Watchdog already running. Resetting timeout to %d sec\n",
191	212	wdog->timeout);
192		- superio_outb(0xF6, wdog->timeout);
	213	+ superio_outb(cr_wdt_timeout, wdog->timeout);
193	214	}
194	215
195	216	/* set second mode & disable keyboard turning off watchdog */
196		- t = superio_inb(0xF5) & ~0x0C;
197		- superio_outb(0xF5, t);
	217	+ t = superio_inb(cr_wdt_control) & ~0x0C;
	218	+ superio_outb(cr_wdt_control, t);
198	219
199	220	/* disable keyboard & mouse turning off watchdog */
200	221	t = superio_inb(0xF7) & ~0xC0;
...	...	@@ -214,7 +235,7 @@
214	235	return ret;
215	236
216	237	superio_select(W83627HF_LD_WDT);
217		- superio_outb(0xF6, timeout);
	238	+ superio_outb(cr_wdt_timeout, timeout);
218	239	superio_exit();
219	240
220	241	return 0;
...	...	@@ -247,7 +268,7 @@
247	268	return 0;
248	269
249	270	superio_select(W83627HF_LD_WDT);
250		- timeleft = superio_inb(0xF6);
	271	+ timeleft = superio_inb(cr_wdt_timeout);
251	272	superio_exit();
252	273
253	274	return timeleft;
...	...	@@ -304,6 +325,9 @@
304	325	u8 val;
305	326	int ret;
306	327
	328	+ cr_wdt_timeout = W83627HF_WDT_TIMEOUT;
	329	+ cr_wdt_control = W83627HF_WDT_CONTROL;
	330	+
307	331	ret = superio_enter();
308	332	if (ret)
309	333	return ret;
...	...	@@ -316,6 +340,16 @@
316	340	case W83627S_ID:
317	341	ret = w83627s;
318	342	break;
	343	+ case W83697HF_ID:
	344	+ ret = w83697hf;
	345	+ cr_wdt_timeout = W83697HF_WDT_TIMEOUT;
	346	+ cr_wdt_control = W83697HF_WDT_CONTROL;
	347	+ break;
	348	+ case W83697UG_ID:
	349	+ ret = w83697ug;
	350	+ cr_wdt_timeout = W83697HF_WDT_TIMEOUT;
	351	+ cr_wdt_control = W83697HF_WDT_CONTROL;
	352	+ break;
319	353	case W83637HF_ID:
320	354	ret = w83637hf;
321	355	break;
...	...	@@ -371,6 +405,8 @@
371	405	const char * const chip_name[] = {
372	406	"W83627HF",
373	407	"W83627S",
	408	+ "W83697HF",
	409	+ "W83697UG",
374	410	"W83637HF",
375	411	"W83627THF",
376	412	"W83687THF",