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Commit 8fcc774fc72910fa26767ae8ca2da3d64ae80a01

Authored by Bartlomiej Zolnierkiewicz
Committed by Kukjin Kim
1 parent c645a598f9

ARM: EXYNOS: add exynos3250 PMU support 

This patch prepares the PMU code for the future:
- suspend/resume (S2R) support
- cpuidle AFTR/W-AFTR modes support
on Exynos3250.

Cc: Vikas Sajjan <vikas.sajjan@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
[kgene.kim@samsung.com: fixed coding style]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

Showing 2 changed files with 295 additions and 0 deletions Side-by-side Diff

arch/arm/mach-exynos/pmu.c
Diff comments   View file @ 8fcc774
... ... @@ -31,6 +31,7 @@
31 31  
32 32 void (*pmu_init)(void);
33 33 void (*powerdown_conf)(enum sys_powerdown);
  34 + void (*powerdown_conf_extra)(enum sys_powerdown);
34 35 };
35 36  
36 37 struct exynos_pmu_context {
... ... @@ -51,6 +52,92 @@
51 52 return readl_relaxed(pmu_base_addr + offset);
52 53 }
53 54  
  55 +static struct exynos_pmu_conf exynos3250_pmu_config[] = {
  56 + /* { .offset = offset, .val = { AFTR, W-AFTR, SLEEP } */
  57 + { EXYNOS3_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
  58 + { EXYNOS3_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
  59 + { EXYNOS3_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
  60 + { EXYNOS3_ARM_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
  61 + { EXYNOS3_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
  62 + { EXYNOS3_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
  63 + { EXYNOS3_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
  64 + { EXYNOS3_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
  65 + { EXYNOS3_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
  66 + { EXYNOS3_ARM_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
  67 + { EXYNOS3_ARM_L2_SYS_PWR_REG, { 0x0, 0x0, 0x3} },
  68 + { EXYNOS3_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
  69 + { EXYNOS3_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
  70 + { EXYNOS3_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
  71 + { EXYNOS3_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
  72 + { EXYNOS3_DDRPHY_DLLOFF_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
  73 + { EXYNOS3_LPDDR_PHY_DLL_LOCK_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
  74 + { EXYNOS3_CMU_ACLKSTOP_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
  75 + { EXYNOS3_CMU_SCLKSTOP_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
  76 + { EXYNOS3_CMU_RESET_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
  77 + { EXYNOS3_APLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
  78 + { EXYNOS3_MPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
  79 + { EXYNOS3_BPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
  80 + { EXYNOS3_VPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
  81 + { EXYNOS3_EPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
  82 + { EXYNOS3_UPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
  83 + { EXYNOS3_EPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
  84 + { EXYNOS3_MPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
  85 + { EXYNOS3_BPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
  86 + { EXYNOS3_CMU_CLKSTOP_CAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
  87 + { EXYNOS3_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
  88 + { EXYNOS3_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
  89 + { EXYNOS3_CMU_CLKSTOP_LCD0_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
  90 + { EXYNOS3_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
  91 + { EXYNOS3_CMU_CLKSTOP_MAUDIO_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
  92 + { EXYNOS3_CMU_RESET_CAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
  93 + { EXYNOS3_CMU_RESET_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
  94 + { EXYNOS3_CMU_RESET_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
  95 + { EXYNOS3_CMU_RESET_LCD0_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
  96 + { EXYNOS3_CMU_RESET_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
  97 + { EXYNOS3_CMU_RESET_MAUDIO_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
  98 + { EXYNOS3_TOP_BUS_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
  99 + { EXYNOS3_TOP_RETENTION_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
  100 + { EXYNOS3_TOP_PWR_SYS_PWR_REG, { 0x3, 0x3, 0x3} },
  101 + { EXYNOS3_TOP_BUS_COREBLK_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
  102 + { EXYNOS3_TOP_RETENTION_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
  103 + { EXYNOS3_TOP_PWR_COREBLK_SYS_PWR_REG, { 0x3, 0x3, 0x3} },
  104 + { EXYNOS3_LOGIC_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
  105 + { EXYNOS3_OSCCLK_GATE_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
  106 + { EXYNOS3_LOGIC_RESET_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
  107 + { EXYNOS3_OSCCLK_GATE_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
  108 + { EXYNOS3_PAD_RETENTION_DRAM_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
  109 + { EXYNOS3_PAD_RETENTION_MAUDIO_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
  110 + { EXYNOS3_PAD_RETENTION_GPIO_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
  111 + { EXYNOS3_PAD_RETENTION_UART_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
  112 + { EXYNOS3_PAD_RETENTION_MMC0_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
  113 + { EXYNOS3_PAD_RETENTION_MMC1_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
  114 + { EXYNOS3_PAD_RETENTION_MMC2_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
  115 + { EXYNOS3_PAD_RETENTION_SPI_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
  116 + { EXYNOS3_PAD_RETENTION_EBIA_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
  117 + { EXYNOS3_PAD_RETENTION_EBIB_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
  118 + { EXYNOS3_PAD_RETENTION_JTAG_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
  119 + { EXYNOS3_PAD_ISOLATION_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
  120 + { EXYNOS3_PAD_ALV_SEL_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
  121 + { EXYNOS3_XUSBXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
  122 + { EXYNOS3_XXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
  123 + { EXYNOS3_EXT_REGULATOR_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
  124 + { EXYNOS3_EXT_REGULATOR_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
  125 + { EXYNOS3_GPIO_MODE_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
  126 + { EXYNOS3_GPIO_MODE_MAUDIO_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
  127 + { EXYNOS3_TOP_ASB_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
  128 + { EXYNOS3_TOP_ASB_ISOLATION_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
  129 + { EXYNOS3_TOP_ASB_RESET_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
  130 + { EXYNOS3_TOP_ASB_ISOLATION_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
  131 + { EXYNOS3_CAM_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
  132 + { EXYNOS3_MFC_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
  133 + { EXYNOS3_G3D_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
  134 + { EXYNOS3_LCD0_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
  135 + { EXYNOS3_ISP_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
  136 + { EXYNOS3_MAUDIO_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
  137 + { EXYNOS3_CMU_SYSCLK_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
  138 + { PMU_TABLE_END,},
  139 +};
  140 +
54 141 static const struct exynos_pmu_conf exynos4210_pmu_config[] = {
55 142 /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
56 143 { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
... ... @@ -495,6 +582,44 @@
495 582 { PMU_TABLE_END,},
496 583 };
497 584  
  585 +static unsigned int const exynos3250_list_feed[] = {
  586 + EXYNOS3_ARM_CORE_OPTION(0),
  587 + EXYNOS3_ARM_CORE_OPTION(1),
  588 + EXYNOS3_ARM_CORE_OPTION(2),
  589 + EXYNOS3_ARM_CORE_OPTION(3),
  590 + EXYNOS3_ARM_COMMON_OPTION,
  591 + EXYNOS3_TOP_PWR_OPTION,
  592 + EXYNOS3_CORE_TOP_PWR_OPTION,
  593 + S5P_CAM_OPTION,
  594 + S5P_MFC_OPTION,
  595 + S5P_G3D_OPTION,
  596 + S5P_LCD0_OPTION,
  597 + S5P_ISP_OPTION,
  598 +};
  599 +
  600 +static void exynos3250_powerdown_conf_extra(enum sys_powerdown mode)
  601 +{
  602 + unsigned int i;
  603 + unsigned int tmp;
  604 +
  605 + /* Enable only SC_FEEDBACK */
  606 + for (i = 0; i < ARRAY_SIZE(exynos3250_list_feed); i++) {
  607 + tmp = pmu_raw_readl(exynos3250_list_feed[i]);
  608 + tmp &= ~(EXYNOS3_OPTION_USE_SC_COUNTER);
  609 + tmp |= EXYNOS3_OPTION_USE_SC_FEEDBACK;
  610 + pmu_raw_writel(tmp, exynos3250_list_feed[i]);
  611 + }
  612 +
  613 + if (mode != SYS_SLEEP)
  614 + return;
  615 +
  616 + pmu_raw_writel(XUSBXTI_DURATION, EXYNOS3_XUSBXTI_DURATION);
  617 + pmu_raw_writel(XXTI_DURATION, EXYNOS3_XXTI_DURATION);
  618 + pmu_raw_writel(EXT_REGULATOR_DURATION, EXYNOS3_EXT_REGULATOR_DURATION);
  619 + pmu_raw_writel(EXT_REGULATOR_COREBLK_DURATION,
  620 + EXYNOS3_EXT_REGULATOR_COREBLK_DURATION);
  621 +}
  622 +
498 623 static unsigned int const exynos5_list_both_cnt_feed[] = {
499 624 EXYNOS5_ARM_CORE0_OPTION,
500 625 EXYNOS5_ARM_CORE1_OPTION,
... ... @@ -632,6 +757,9 @@
632 757 pmu_data->pmu_config[i].offset);
633 758 }
634 759  
  760 + if (pmu_data->powerdown_conf_extra)
  761 + pmu_data->powerdown_conf_extra(mode);
  762 +
635 763 if (pmu_data->pmu_config_extra) {
636 764 for (i = 0; pmu_data->pmu_config_extra[i].offset != PMU_TABLE_END; i++)
637 765 pmu_raw_writel(pmu_data->pmu_config_extra[i].val[mode],
... ... @@ -639,6 +767,36 @@
639 767 }
640 768 }
641 769  
  770 +static void exynos3250_pmu_init(void)
  771 +{
  772 + unsigned int value;
  773 +
  774 + /*
  775 + * To prevent from issuing new bus request form L2 memory system
  776 + * If core status is power down, should be set '1' to L2 power down
  777 + */
  778 + value = pmu_raw_readl(EXYNOS3_ARM_COMMON_OPTION);
  779 + value |= EXYNOS3_OPTION_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
  780 + pmu_raw_writel(value, EXYNOS3_ARM_COMMON_OPTION);
  781 +
  782 + /* Enable USE_STANDBY_WFI for all CORE */
  783 + pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
  784 +
  785 + /*
  786 + * Set PSHOLD port for output high
  787 + */
  788 + value = pmu_raw_readl(S5P_PS_HOLD_CONTROL);
  789 + value |= S5P_PS_HOLD_OUTPUT_HIGH;
  790 + pmu_raw_writel(value, S5P_PS_HOLD_CONTROL);
  791 +
  792 + /*
  793 + * Enable signal for PSHOLD port
  794 + */
  795 + value = pmu_raw_readl(S5P_PS_HOLD_CONTROL);
  796 + value |= S5P_PS_HOLD_EN;
  797 + pmu_raw_writel(value, S5P_PS_HOLD_CONTROL);
  798 +}
  799 +
642 800 static void exynos5250_pmu_init(void)
643 801 {
644 802 unsigned int value;
... ... @@ -717,6 +875,12 @@
717 875 }
718 876  
719 877  
  878 +static const struct exynos_pmu_data exynos3250_pmu_data = {
  879 + .pmu_config = exynos3250_pmu_config,
  880 + .pmu_init = exynos3250_pmu_init,
  881 + .powerdown_conf_extra = exynos3250_powerdown_conf_extra,
  882 +};
  883 +
720 884 static const struct exynos_pmu_data exynos4210_pmu_data = {
721 885 .pmu_config = exynos4210_pmu_config,
722 886 };
... ... @@ -747,6 +911,9 @@
747 911 */
748 912 static const struct of_device_id exynos_pmu_of_device_ids[] = {
749 913 {
  914 + .compatible = "samsung,exynos3250-pmu",
  915 + .data = &exynos3250_pmu_data,
  916 + }, {
750 917 .compatible = "samsung,exynos4210-pmu",
751 918 .data = &exynos4210_pmu_data,
752 919 }, {
arch/arm/mach-exynos/regs-pmu.h
Diff comments   View file @ 8fcc774
... ... @@ -19,7 +19,20 @@
19 19 #define S5P_CENTRAL_SEQ_OPTION 0x0208
20 20  
21 21 #define S5P_USE_STANDBY_WFI0 (1 << 16)
  22 +#define S5P_USE_STANDBY_WFI1 (1 << 17)
  23 +#define S5P_USE_STANDBY_WFI2 (1 << 19)
  24 +#define S5P_USE_STANDBY_WFI3 (1 << 20)
22 25 #define S5P_USE_STANDBY_WFE0 (1 << 24)
  26 +#define S5P_USE_STANDBY_WFE1 (1 << 25)
  27 +#define S5P_USE_STANDBY_WFE2 (1 << 27)
  28 +#define S5P_USE_STANDBY_WFE3 (1 << 28)
  29 +
  30 +#define S5P_USE_STANDBY_WFI_ALL \
  31 + (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFI1 | \
  32 + S5P_USE_STANDBY_WFI2 | S5P_USE_STANDBY_WFI3 | \
  33 + S5P_USE_STANDBY_WFE0 | S5P_USE_STANDBY_WFE1 | \
  34 + S5P_USE_STANDBY_WFE2 | S5P_USE_STANDBY_WFE3)
  35 +
23 36 #define S5P_USE_DELAYED_RESET_ASSERTION BIT(12)
24 37  
25 38 #define EXYNOS_CORE_PO_RESET(n) ((1 << 4) << n)
... ... @@ -154,6 +167,17 @@
154 167 #define S5P_PAD_RET_EBIA_OPTION 0x3188
155 168 #define S5P_PAD_RET_EBIB_OPTION 0x31A8
156 169  
  170 +#define S5P_PS_HOLD_CONTROL 0x330C
  171 +#define S5P_PS_HOLD_EN (1 << 31)
  172 +#define S5P_PS_HOLD_OUTPUT_HIGH (3 << 8)
  173 +
  174 +#define S5P_CAM_OPTION 0x3C08
  175 +#define S5P_MFC_OPTION 0x3C48
  176 +#define S5P_G3D_OPTION 0x3C68
  177 +#define S5P_LCD0_OPTION 0x3C88
  178 +#define S5P_LCD1_OPTION 0x3CA8
  179 +#define S5P_ISP_OPTION S5P_LCD1_OPTION
  180 +
157 181 #define S5P_CORE_LOCAL_PWR_EN 0x3
158 182 #define S5P_CORE_WAKEUP_FROM_LOCAL_CFG (0x3 << 8)
159 183  
... ... @@ -213,6 +237,110 @@
213 237 #define S5P_ARM_CORE3_LOWPWR 0x1030
214 238 #define S5P_DIS_IRQ_CORE3 0x1034
215 239 #define S5P_DIS_IRQ_CENTRAL3 0x1038
  240 +
  241 +/* Only for EXYNOS3XXX */
  242 +#define EXYNOS3_ARM_CORE0_SYS_PWR_REG 0x1000
  243 +#define EXYNOS3_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG 0x1004
  244 +#define EXYNOS3_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG 0x1008
  245 +#define EXYNOS3_ARM_CORE1_SYS_PWR_REG 0x1010
  246 +#define EXYNOS3_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG 0x1014
  247 +#define EXYNOS3_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG 0x1018
  248 +#define EXYNOS3_ISP_ARM_SYS_PWR_REG 0x1050
  249 +#define EXYNOS3_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG 0x1054
  250 +#define EXYNOS3_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG 0x1058
  251 +#define EXYNOS3_ARM_COMMON_SYS_PWR_REG 0x1080
  252 +#define EXYNOS3_ARM_L2_SYS_PWR_REG 0x10C0
  253 +#define EXYNOS3_CMU_ACLKSTOP_SYS_PWR_REG 0x1100
  254 +#define EXYNOS3_CMU_SCLKSTOP_SYS_PWR_REG 0x1104
  255 +#define EXYNOS3_CMU_RESET_SYS_PWR_REG 0x110C
  256 +#define EXYNOS3_CMU_ACLKSTOP_COREBLK_SYS_PWR_REG 0x1110
  257 +#define EXYNOS3_CMU_SCLKSTOP_COREBLK_SYS_PWR_REG 0x1114
  258 +#define EXYNOS3_CMU_RESET_COREBLK_SYS_PWR_REG 0x111C
  259 +#define EXYNOS3_APLL_SYSCLK_SYS_PWR_REG 0x1120
  260 +#define EXYNOS3_MPLL_SYSCLK_SYS_PWR_REG 0x1124
  261 +#define EXYNOS3_VPLL_SYSCLK_SYS_PWR_REG 0x1128
  262 +#define EXYNOS3_EPLL_SYSCLK_SYS_PWR_REG 0x112C
  263 +#define EXYNOS3_MPLLUSER_SYSCLK_SYS_PWR_REG 0x1130
  264 +#define EXYNOS3_BPLLUSER_SYSCLK_SYS_PWR_REG 0x1134
  265 +#define EXYNOS3_EPLLUSER_SYSCLK_SYS_PWR_REG 0x1138
  266 +#define EXYNOS3_CMU_CLKSTOP_CAM_SYS_PWR_REG 0x1140
  267 +#define EXYNOS3_CMU_CLKSTOP_MFC_SYS_PWR_REG 0x1148
  268 +#define EXYNOS3_CMU_CLKSTOP_G3D_SYS_PWR_REG 0x114C
  269 +#define EXYNOS3_CMU_CLKSTOP_LCD0_SYS_PWR_REG 0x1150
  270 +#define EXYNOS3_CMU_CLKSTOP_ISP_SYS_PWR_REG 0x1154
  271 +#define EXYNOS3_CMU_CLKSTOP_MAUDIO_SYS_PWR_REG 0x1158
  272 +#define EXYNOS3_CMU_RESET_CAM_SYS_PWR_REG 0x1160
  273 +#define EXYNOS3_CMU_RESET_MFC_SYS_PWR_REG 0x1168
  274 +#define EXYNOS3_CMU_RESET_G3D_SYS_PWR_REG 0x116C
  275 +#define EXYNOS3_CMU_RESET_LCD0_SYS_PWR_REG 0x1170
  276 +#define EXYNOS3_CMU_RESET_ISP_SYS_PWR_REG 0x1174
  277 +#define EXYNOS3_CMU_RESET_MAUDIO_SYS_PWR_REG 0x1178
  278 +#define EXYNOS3_TOP_BUS_SYS_PWR_REG 0x1180
  279 +#define EXYNOS3_TOP_RETENTION_SYS_PWR_REG 0x1184
  280 +#define EXYNOS3_TOP_PWR_SYS_PWR_REG 0x1188
  281 +#define EXYNOS3_TOP_BUS_COREBLK_SYS_PWR_REG 0x1190
  282 +#define EXYNOS3_TOP_RETENTION_COREBLK_SYS_PWR_REG 0x1194
  283 +#define EXYNOS3_TOP_PWR_COREBLK_SYS_PWR_REG 0x1198
  284 +#define EXYNOS3_LOGIC_RESET_SYS_PWR_REG 0x11A0
  285 +#define EXYNOS3_OSCCLK_GATE_SYS_PWR_REG 0x11A4
  286 +#define EXYNOS3_LOGIC_RESET_COREBLK_SYS_PWR_REG 0x11B0
  287 +#define EXYNOS3_OSCCLK_GATE_COREBLK_SYS_PWR_REG 0x11B4
  288 +#define EXYNOS3_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1200
  289 +#define EXYNOS3_PAD_RETENTION_MAUDIO_SYS_PWR_REG 0x1204
  290 +#define EXYNOS3_PAD_RETENTION_SPI_SYS_PWR_REG 0x1208
  291 +#define EXYNOS3_PAD_RETENTION_MMC2_SYS_PWR_REG 0x1218
  292 +#define EXYNOS3_PAD_RETENTION_GPIO_SYS_PWR_REG 0x1220
  293 +#define EXYNOS3_PAD_RETENTION_UART_SYS_PWR_REG 0x1224
  294 +#define EXYNOS3_PAD_RETENTION_MMC0_SYS_PWR_REG 0x1228
  295 +#define EXYNOS3_PAD_RETENTION_MMC1_SYS_PWR_REG 0x122C
  296 +#define EXYNOS3_PAD_RETENTION_EBIA_SYS_PWR_REG 0x1230
  297 +#define EXYNOS3_PAD_RETENTION_EBIB_SYS_PWR_REG 0x1234
  298 +#define EXYNOS3_PAD_RETENTION_JTAG_SYS_PWR_REG 0x1238
  299 +#define EXYNOS3_PAD_ISOLATION_SYS_PWR_REG 0x1240
  300 +#define EXYNOS3_PAD_ALV_SEL_SYS_PWR_REG 0x1260
  301 +#define EXYNOS3_XUSBXTI_SYS_PWR_REG 0x1280
  302 +#define EXYNOS3_XXTI_SYS_PWR_REG 0x1284
  303 +#define EXYNOS3_EXT_REGULATOR_SYS_PWR_REG 0x12C0
  304 +#define EXYNOS3_EXT_REGULATOR_COREBLK_SYS_PWR_REG 0x12C4
  305 +#define EXYNOS3_GPIO_MODE_SYS_PWR_REG 0x1300
  306 +#define EXYNOS3_GPIO_MODE_MAUDIO_SYS_PWR_REG 0x1340
  307 +#define EXYNOS3_TOP_ASB_RESET_SYS_PWR_REG 0x1344
  308 +#define EXYNOS3_TOP_ASB_ISOLATION_SYS_PWR_REG 0x1348
  309 +#define EXYNOS3_TOP_ASB_RESET_COREBLK_SYS_PWR_REG 0x1350
  310 +#define EXYNOS3_TOP_ASB_ISOLATION_COREBLK_SYS_PWR_REG 0x1354
  311 +#define EXYNOS3_CAM_SYS_PWR_REG 0x1380
  312 +#define EXYNOS3_MFC_SYS_PWR_REG 0x1388
  313 +#define EXYNOS3_G3D_SYS_PWR_REG 0x138C
  314 +#define EXYNOS3_LCD0_SYS_PWR_REG 0x1390
  315 +#define EXYNOS3_ISP_SYS_PWR_REG 0x1394
  316 +#define EXYNOS3_MAUDIO_SYS_PWR_REG 0x1398
  317 +#define EXYNOS3_DRAM_FREQ_DOWN_SYS_PWR_REG 0x13B0
  318 +#define EXYNOS3_DDRPHY_DLLOFF_SYS_PWR_REG 0x13B4
  319 +#define EXYNOS3_CMU_SYSCLK_ISP_SYS_PWR_REG 0x13B8
  320 +#define EXYNOS3_LPDDR_PHY_DLL_LOCK_SYS_PWR_REG 0x13C0
  321 +#define EXYNOS3_BPLL_SYSCLK_SYS_PWR_REG 0x13C4
  322 +#define EXYNOS3_UPLL_SYSCLK_SYS_PWR_REG 0x13C8
  323 +
  324 +#define EXYNOS3_ARM_CORE0_OPTION 0x2008
  325 +#define EXYNOS3_ARM_CORE_OPTION(_nr) \
  326 + (EXYNOS3_ARM_CORE0_OPTION + ((_nr) * 0x80))
  327 +
  328 +#define EXYNOS3_ARM_COMMON_OPTION 0x2408
  329 +#define EXYNOS3_TOP_PWR_OPTION 0x2C48
  330 +#define EXYNOS3_CORE_TOP_PWR_OPTION 0x2CA8
  331 +#define EXYNOS3_XUSBXTI_DURATION 0x341C
  332 +#define EXYNOS3_XXTI_DURATION 0x343C
  333 +#define EXYNOS3_EXT_REGULATOR_DURATION 0x361C
  334 +#define EXYNOS3_EXT_REGULATOR_COREBLK_DURATION 0x363C
  335 +#define XUSBXTI_DURATION 0x00000BB8
  336 +#define XXTI_DURATION XUSBXTI_DURATION
  337 +#define EXT_REGULATOR_DURATION 0x00001D4C
  338 +#define EXT_REGULATOR_COREBLK_DURATION EXT_REGULATOR_DURATION
  339 +
  340 +/* for XXX_OPTION */
  341 +#define EXYNOS3_OPTION_USE_SC_COUNTER (1 << 0)
  342 +#define EXYNOS3_OPTION_USE_SC_FEEDBACK (1 << 1)
  343 +#define EXYNOS3_OPTION_SKIP_DEACTIVATE_ACEACP_IN_PWDN (1 << 7)
216 344  
217 345 /* For EXYNOS5 */
218 346