Eric Lee / smarc-fsl-linux-kernel

Commit 948c66df0d5e23dbcb84bee39a11b56c8a0d3e41

Authored by Sekhar Nori 16 years ago

Committed by Kevin Hilman 15 years ago

Exists in master and in 39 other branches

davinci: cpuidle: move mapping of DDR2 controller registers out of driver

When suspend is supported, both cpuidle and suspend code
need to work on DDR2 registers. Instead of mapping the
DDR2 registers twice, do it once outside of cpuidle
driver and let cpuidle driver get the virtual base address
of DDR2 registers.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>

Showing 4 changed files with 21 additions and 30 deletions Inline Diff

arch/arm/mach-davinci/cpuidle.c
arch/arm/mach-davinci/devices-da8xx.c
arch/arm/mach-davinci/include/mach/cpuidle.h
arch/arm/mach-davinci/include/mach/da8xx.h

arch/arm/mach-davinci/cpuidle.c

Diff comments View file @ 948c66d

 /*
  * CPU idle for DaVinci SoCs
  *
  * Copyright (C) 2009 Texas Instruments Incorporated. http://www.ti.com/
  *
  * Derived from Marvell Kirkwood CPU idle code
  * (arch/arm/mach-kirkwood/cpuidle.c)
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/cpuidle.h>
 #include <linux/io.h>
 #include <asm/proc-fns.h>
 #include <mach/cpuidle.h>
 #include <mach/memory.h>
 #define DAVINCI_CPUIDLE_MAX_STATES	2
 struct davinci_ops {
 	void (*enter) (u32 flags);
 	void (*exit) (u32 flags);
 	u32 flags;
 };
 /* fields in davinci_ops.flags */
 #define DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN	BIT(0)
 static struct cpuidle_driver davinci_idle_driver = {
 	.name	= "cpuidle-davinci",
 	.owner	= THIS_MODULE,
 };
 static DEFINE_PER_CPU(struct cpuidle_device, davinci_cpuidle_device);
 static void __iomem *ddr2_reg_base;
 static void davinci_save_ddr_power(int enter, bool pdown)
 {
 	u32 val;
 	val = __raw_readl(ddr2_reg_base + DDR2_SDRCR_OFFSET);
 	if (enter) {
 		if (pdown)
 			val |= DDR2_SRPD_BIT;
 		else
 			val &= ~DDR2_SRPD_BIT;
 		val |= DDR2_LPMODEN_BIT;
 	} else {
 		val &= ~(DDR2_SRPD_BIT | DDR2_LPMODEN_BIT);
 	}
 	__raw_writel(val, ddr2_reg_base + DDR2_SDRCR_OFFSET);
 }
 static void davinci_c2state_enter(u32 flags)
 {
 	davinci_save_ddr_power(1, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN));
 }
 static void davinci_c2state_exit(u32 flags)
 {
 	davinci_save_ddr_power(0, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN));
 }
 static struct davinci_ops davinci_states[DAVINCI_CPUIDLE_MAX_STATES] = {
 	[1] = {
 		.enter	= davinci_c2state_enter,
 		.exit	= davinci_c2state_exit,
 	},
 };
 /* Actual code that puts the SoC in different idle states */
 static int davinci_enter_idle(struct cpuidle_device *dev,
 						struct cpuidle_state *state)
 {
 	struct davinci_ops *ops = cpuidle_get_statedata(state);
 	struct timeval before, after;
 	int idle_time;
 	local_irq_disable();
 	do_gettimeofday(&before);
 	if (ops && ops->enter)
 		ops->enter(ops->flags);
 	/* Wait for interrupt state */
 	cpu_do_idle();
 	if (ops && ops->exit)
 		ops->exit(ops->flags);
 	do_gettimeofday(&after);
 	local_irq_enable();
 	idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
 			(after.tv_usec - before.tv_usec);
 	return idle_time;
 }
 static int __init davinci_cpuidle_probe(struct platform_device *pdev)
 {
 	int ret;
 	struct cpuidle_device *device;
 	struct davinci_cpuidle_config *pdata = pdev->dev.platform_data;
-	struct resource *ddr2_regs;
-	resource_size_t len;
 	device = &per_cpu(davinci_cpuidle_device, smp_processor_id());
 	if (!pdata) {
 		dev_err(&pdev->dev, "cannot get platform data\n");
 		return -ENOENT;
 	}
-	ddr2_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	ddr2_reg_base = pdata->ddr2_ctlr_base;
-	if (!ddr2_regs) {
-		dev_err(&pdev->dev, "cannot get DDR2 controller register base");
-		return -ENODEV;
-	}
-	len = resource_size(ddr2_regs);
-	ddr2_regs = request_mem_region(ddr2_regs->start, len, ddr2_regs->name);
-	if (!ddr2_regs)
-		return -EBUSY;
-	ddr2_reg_base = ioremap(ddr2_regs->start, len);
-	if (!ddr2_reg_base) {
-		ret = -ENOMEM;
-		goto ioremap_fail;
-	}
 	ret = cpuidle_register_driver(&davinci_idle_driver);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to register driver\n");
-		goto driver_register_fail;
+		return ret;
 	}
 	/* Wait for interrupt state */
 	device->states[0].enter = davinci_enter_idle;
 	device->states[0].exit_latency = 1;
 	device->states[0].target_residency = 10000;
 	device->states[0].flags = CPUIDLE_FLAG_TIME_VALID;
 	strcpy(device->states[0].name, "WFI");
 	strcpy(device->states[0].desc, "Wait for interrupt");
 	/* Wait for interrupt and DDR self refresh state */
 	device->states[1].enter = davinci_enter_idle;
 	device->states[1].exit_latency = 10;
 	device->states[1].target_residency = 10000;
 	device->states[1].flags = CPUIDLE_FLAG_TIME_VALID;
 	strcpy(device->states[1].name, "DDR SR");
 	strcpy(device->states[1].desc, "WFI and DDR Self Refresh");
 	if (pdata->ddr2_pdown)
 		davinci_states[1].flags |= DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN;
 	cpuidle_set_statedata(&device->states[1], &davinci_states[1]);
 	device->state_count = DAVINCI_CPUIDLE_MAX_STATES;
 	ret = cpuidle_register_device(device);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to register device\n");
-		goto device_register_fail;
+		cpuidle_unregister_driver(&davinci_idle_driver);
+		return ret;
 	}
 	return 0;
-device_register_fail:
-	cpuidle_unregister_driver(&davinci_idle_driver);
-driver_register_fail:
-	iounmap(ddr2_reg_base);
-ioremap_fail:
-	release_mem_region(ddr2_regs->start, len);
-	return ret;
 }
 static struct platform_driver davinci_cpuidle_driver = {
 	.driver = {
 		.name	= "cpuidle-davinci",
 		.owner	= THIS_MODULE,
 	},
 };
 static int __init davinci_cpuidle_init(void)
 {
 	return platform_driver_probe(&davinci_cpuidle_driver,
 						davinci_cpuidle_probe);
 }
 device_initcall(davinci_cpuidle_init);

arch/arm/mach-davinci/devices-da8xx.c

Diff comments View file @ 948c66d

 /*
  * DA8XX/OMAP L1XX platform device data
  *
  * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
  * Derived from code that was:
  *	Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  */
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/serial_8250.h>
 #include <mach/cputype.h>
 #include <mach/common.h>
 #include <mach/time.h>
 #include <mach/da8xx.h>
 #include <mach/cpuidle.h>
 #include "clock.h"
 #define DA8XX_TPCC_BASE			0x01c00000
 #define DA8XX_TPTC0_BASE		0x01c08000
 #define DA8XX_TPTC1_BASE		0x01c08400
 #define DA8XX_WDOG_BASE			0x01c21000 /* DA8XX_TIMER64P1_BASE */
 #define DA8XX_I2C0_BASE			0x01c22000
 #define DA8XX_RTC_BASE			0x01C23000
 #define DA8XX_EMAC_CPPI_PORT_BASE	0x01e20000
 #define DA8XX_EMAC_CPGMACSS_BASE	0x01e22000
 #define DA8XX_EMAC_CPGMAC_BASE		0x01e23000
 #define DA8XX_EMAC_MDIO_BASE		0x01e24000
 #define DA8XX_GPIO_BASE			0x01e26000
 #define DA8XX_I2C1_BASE			0x01e28000
 #define DA8XX_EMAC_CTRL_REG_OFFSET	0x3000
 #define DA8XX_EMAC_MOD_REG_OFFSET	0x2000
 #define DA8XX_EMAC_RAM_OFFSET		0x0000
 #define DA8XX_MDIO_REG_OFFSET		0x4000
 #define DA8XX_EMAC_CTRL_RAM_SIZE	SZ_8K
 void __iomem *da8xx_syscfg0_base;
 void __iomem *da8xx_syscfg1_base;
 static struct plat_serial8250_port da8xx_serial_pdata[] = {
 	{
 		.mapbase	= DA8XX_UART0_BASE,
 		.irq		= IRQ_DA8XX_UARTINT0,
 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 					UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 2,
 	},
 	{
 		.mapbase	= DA8XX_UART1_BASE,
 		.irq		= IRQ_DA8XX_UARTINT1,
 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 					UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 2,
 	},
 	{
 		.mapbase	= DA8XX_UART2_BASE,
 		.irq		= IRQ_DA8XX_UARTINT2,
 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 					UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 2,
 	},
 	{
 		.flags	= 0,
 	},
 };
 struct platform_device da8xx_serial_device = {
 	.name	= "serial8250",
 	.id	= PLAT8250_DEV_PLATFORM,
 	.dev	= {
 		.platform_data	= da8xx_serial_pdata,
 	},
 };
 static const s8 da8xx_dma_chan_no_event[] = {
 	20, 21,
 	-1
 };
 static const s8 da8xx_queue_tc_mapping[][2] = {
 	/* {event queue no, TC no} */
 	{0, 0},
 	{1, 1},
 	{-1, -1}
 };
 static const s8 da8xx_queue_priority_mapping[][2] = {
 	/* {event queue no, Priority} */
 	{0, 3},
 	{1, 7},
 	{-1, -1}
 };
 static struct edma_soc_info da8xx_edma_info[] = {
 	{
 		.n_channel		= 32,
 		.n_region		= 4,
 		.n_slot			= 128,
 		.n_tc			= 2,
 		.n_cc			= 1,
 		.noevent		= da8xx_dma_chan_no_event,
 		.queue_tc_mapping	= da8xx_queue_tc_mapping,
 		.queue_priority_mapping	= da8xx_queue_priority_mapping,
 	},
 };
 static struct resource da8xx_edma_resources[] = {
 	{
 		.name	= "edma_cc0",
 		.start	= DA8XX_TPCC_BASE,
 		.end	= DA8XX_TPCC_BASE + SZ_32K - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	{
 		.name	= "edma_tc0",
 		.start	= DA8XX_TPTC0_BASE,
 		.end	= DA8XX_TPTC0_BASE + SZ_1K - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	{
 		.name	= "edma_tc1",
 		.start	= DA8XX_TPTC1_BASE,
 		.end	= DA8XX_TPTC1_BASE + SZ_1K - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	{
 		.name	= "edma0",
 		.start	= IRQ_DA8XX_CCINT0,
 		.flags	= IORESOURCE_IRQ,
 	},
 	{
 		.name	= "edma0_err",
 		.start	= IRQ_DA8XX_CCERRINT,
 		.flags	= IORESOURCE_IRQ,
 	},
 };
 static struct platform_device da8xx_edma_device = {
 	.name		= "edma",
 	.id		= -1,
 	.dev = {
 		.platform_data	= da8xx_edma_info,
 	},
 	.num_resources	= ARRAY_SIZE(da8xx_edma_resources),
 	.resource	= da8xx_edma_resources,
 };
 int __init da8xx_register_edma(void)
 {
 	return platform_device_register(&da8xx_edma_device);
 }
 static struct resource da8xx_i2c_resources0[] = {
 	{
 		.start	= DA8XX_I2C0_BASE,
 		.end	= DA8XX_I2C0_BASE + SZ_4K - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	{
 		.start	= IRQ_DA8XX_I2CINT0,
 		.end	= IRQ_DA8XX_I2CINT0,
 		.flags	= IORESOURCE_IRQ,
 	},
 };
 static struct platform_device da8xx_i2c_device0 = {
 	.name		= "i2c_davinci",
 	.id		= 1,
 	.num_resources	= ARRAY_SIZE(da8xx_i2c_resources0),
 	.resource	= da8xx_i2c_resources0,
 };
 static struct resource da8xx_i2c_resources1[] = {
 	{
 		.start	= DA8XX_I2C1_BASE,
 		.end	= DA8XX_I2C1_BASE + SZ_4K - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	{
 		.start	= IRQ_DA8XX_I2CINT1,
 		.end	= IRQ_DA8XX_I2CINT1,
 		.flags	= IORESOURCE_IRQ,
 	},
 };
 static struct platform_device da8xx_i2c_device1 = {
 	.name		= "i2c_davinci",
 	.id		= 2,
 	.num_resources	= ARRAY_SIZE(da8xx_i2c_resources1),
 	.resource	= da8xx_i2c_resources1,
 };
 int __init da8xx_register_i2c(int instance,
 		struct davinci_i2c_platform_data *pdata)
 {
 	struct platform_device *pdev;
 	if (instance == 0)
 		pdev = &da8xx_i2c_device0;
 	else if (instance == 1)
 		pdev = &da8xx_i2c_device1;
 	else
 		return -EINVAL;
 	pdev->dev.platform_data = pdata;
 	return platform_device_register(pdev);
 }
 static struct resource da8xx_watchdog_resources[] = {
 	{
 		.start	= DA8XX_WDOG_BASE,
 		.end	= DA8XX_WDOG_BASE + SZ_4K - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 };
 struct platform_device davinci_wdt_device = {
 	.name		= "watchdog",
 	.id		= -1,
 	.num_resources	= ARRAY_SIZE(da8xx_watchdog_resources),
 	.resource	= da8xx_watchdog_resources,
 };
 int __init da8xx_register_watchdog(void)
 {
 	return platform_device_register(&davinci_wdt_device);
 }
 static struct resource da8xx_emac_resources[] = {
 	{
 		.start	= DA8XX_EMAC_CPPI_PORT_BASE,
 		.end	= DA8XX_EMAC_CPPI_PORT_BASE + 0x5000 - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	{
 		.start	= IRQ_DA8XX_C0_RX_THRESH_PULSE,
 		.end	= IRQ_DA8XX_C0_RX_THRESH_PULSE,
 		.flags	= IORESOURCE_IRQ,
 	},
 	{
 		.start	= IRQ_DA8XX_C0_RX_PULSE,
 		.end	= IRQ_DA8XX_C0_RX_PULSE,
 		.flags	= IORESOURCE_IRQ,
 	},
 	{
 		.start	= IRQ_DA8XX_C0_TX_PULSE,
 		.end	= IRQ_DA8XX_C0_TX_PULSE,
 		.flags	= IORESOURCE_IRQ,
 	},
 	{
 		.start	= IRQ_DA8XX_C0_MISC_PULSE,
 		.end	= IRQ_DA8XX_C0_MISC_PULSE,
 		.flags	= IORESOURCE_IRQ,
 	},
 };
 struct emac_platform_data da8xx_emac_pdata = {
 	.ctrl_reg_offset	= DA8XX_EMAC_CTRL_REG_OFFSET,
 	.ctrl_mod_reg_offset	= DA8XX_EMAC_MOD_REG_OFFSET,
 	.ctrl_ram_offset	= DA8XX_EMAC_RAM_OFFSET,
 	.mdio_reg_offset	= DA8XX_MDIO_REG_OFFSET,
 	.ctrl_ram_size		= DA8XX_EMAC_CTRL_RAM_SIZE,
 	.version		= EMAC_VERSION_2,
 };
 static struct platform_device da8xx_emac_device = {
 	.name		= "davinci_emac",
 	.id		= 1,
 	.dev = {
 		.platform_data	= &da8xx_emac_pdata,
 	},
 	.num_resources	= ARRAY_SIZE(da8xx_emac_resources),
 	.resource	= da8xx_emac_resources,
 };
 int __init da8xx_register_emac(void)
 {
 	return platform_device_register(&da8xx_emac_device);
 }
 static struct resource da830_mcasp1_resources[] = {
 	{
 		.name	= "mcasp1",
 		.start	= DAVINCI_DA830_MCASP1_REG_BASE,
 		.end	= DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	/* TX event */
 	{
 		.start	= DAVINCI_DA830_DMA_MCASP1_AXEVT,
 		.end	= DAVINCI_DA830_DMA_MCASP1_AXEVT,
 		.flags	= IORESOURCE_DMA,
 	},
 	/* RX event */
 	{
 		.start	= DAVINCI_DA830_DMA_MCASP1_AREVT,
 		.end	= DAVINCI_DA830_DMA_MCASP1_AREVT,
 		.flags	= IORESOURCE_DMA,
 	},
 };
 static struct platform_device da830_mcasp1_device = {
 	.name		= "davinci-mcasp",
 	.id		= 1,
 	.num_resources	= ARRAY_SIZE(da830_mcasp1_resources),
 	.resource	= da830_mcasp1_resources,
 };
 static struct resource da850_mcasp_resources[] = {
 	{
 		.name	= "mcasp",
 		.start	= DAVINCI_DA8XX_MCASP0_REG_BASE,
 		.end	= DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	/* TX event */
 	{
 		.start	= DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
 		.end	= DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
 		.flags	= IORESOURCE_DMA,
 	},
 	/* RX event */
 	{
 		.start	= DAVINCI_DA8XX_DMA_MCASP0_AREVT,
 		.end	= DAVINCI_DA8XX_DMA_MCASP0_AREVT,
 		.flags	= IORESOURCE_DMA,
 	},
 };
 static struct platform_device da850_mcasp_device = {
 	.name		= "davinci-mcasp",
 	.id		= 0,
 	.num_resources	= ARRAY_SIZE(da850_mcasp_resources),
 	.resource	= da850_mcasp_resources,
 };
 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
 {
 	/* DA830/OMAP-L137 has 3 instances of McASP */
 	if (cpu_is_davinci_da830() && id == 1) {
 		da830_mcasp1_device.dev.platform_data = pdata;
 		platform_device_register(&da830_mcasp1_device);
 	} else if (cpu_is_davinci_da850()) {
 		da850_mcasp_device.dev.platform_data = pdata;
 		platform_device_register(&da850_mcasp_device);
 	}
 }
 static const struct display_panel disp_panel = {
 	QVGA,
 	16,
 	16,
 	COLOR_ACTIVE,
 };
 static struct lcd_ctrl_config lcd_cfg = {
 	&disp_panel,
 	.ac_bias		= 255,
 	.ac_bias_intrpt		= 0,
 	.dma_burst_sz		= 16,
 	.bpp			= 16,
 	.fdd			= 255,
 	.tft_alt_mode		= 0,
 	.stn_565_mode		= 0,
 	.mono_8bit_mode		= 0,
 	.invert_line_clock	= 1,
 	.invert_frm_clock	= 1,
 	.sync_edge		= 0,
 	.sync_ctrl		= 1,
 	.raster_order		= 0,
 };
 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
 	.manu_name		= "sharp",
 	.controller_data	= &lcd_cfg,
 	.type			= "Sharp_LCD035Q3DG01",
 };
 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
 	.manu_name		= "sharp",
 	.controller_data	= &lcd_cfg,
 	.type			= "Sharp_LK043T1DG01",
 };
 static struct resource da8xx_lcdc_resources[] = {
 	[0] = { /* registers */
 		.start  = DA8XX_LCD_CNTRL_BASE,
 		.end    = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
 		.flags  = IORESOURCE_MEM,
 	},
 	[1] = { /* interrupt */
 		.start  = IRQ_DA8XX_LCDINT,
 		.end    = IRQ_DA8XX_LCDINT,
 		.flags  = IORESOURCE_IRQ,
 	},
 };
 static struct platform_device da8xx_lcdc_device = {
 	.name		= "da8xx_lcdc",
 	.id		= 0,
 	.num_resources	= ARRAY_SIZE(da8xx_lcdc_resources),
 	.resource	= da8xx_lcdc_resources,
 };
 int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
 {
 	da8xx_lcdc_device.dev.platform_data = pdata;
 	return platform_device_register(&da8xx_lcdc_device);
 }
 static struct resource da8xx_mmcsd0_resources[] = {
 	{		/* registers */
 		.start	= DA8XX_MMCSD0_BASE,
 		.end	= DA8XX_MMCSD0_BASE + SZ_4K - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	{		/* interrupt */
 		.start	= IRQ_DA8XX_MMCSDINT0,
 		.end	= IRQ_DA8XX_MMCSDINT0,
 		.flags	= IORESOURCE_IRQ,
 	},
 	{		/* DMA RX */
 		.start	= EDMA_CTLR_CHAN(0, 16),
 		.end	= EDMA_CTLR_CHAN(0, 16),
 		.flags	= IORESOURCE_DMA,
 	},
 	{		/* DMA TX */
 		.start	= EDMA_CTLR_CHAN(0, 17),
 		.end	= EDMA_CTLR_CHAN(0, 17),
 		.flags	= IORESOURCE_DMA,
 	},
 };
 static struct platform_device da8xx_mmcsd0_device = {
 	.name		= "davinci_mmc",
 	.id		= 0,
 	.num_resources	= ARRAY_SIZE(da8xx_mmcsd0_resources),
 	.resource	= da8xx_mmcsd0_resources,
 };
 int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
 {
 	da8xx_mmcsd0_device.dev.platform_data = config;
 	return platform_device_register(&da8xx_mmcsd0_device);
 }
 static struct resource da8xx_rtc_resources[] = {
 	{
 		.start		= DA8XX_RTC_BASE,
 		.end		= DA8XX_RTC_BASE + SZ_4K - 1,
 		.flags		= IORESOURCE_MEM,
 	},
 	{ /* timer irq */
 		.start		= IRQ_DA8XX_RTC,
 		.end		= IRQ_DA8XX_RTC,
 		.flags		= IORESOURCE_IRQ,
 	},
 	{ /* alarm irq */
 		.start		= IRQ_DA8XX_RTC,
 		.end		= IRQ_DA8XX_RTC,
 		.flags		= IORESOURCE_IRQ,
 	},
 };
 static struct platform_device da8xx_rtc_device = {
 	.name           = "omap_rtc",
 	.id             = -1,
 	.num_resources	= ARRAY_SIZE(da8xx_rtc_resources),
 	.resource	= da8xx_rtc_resources,
 };
 int da8xx_register_rtc(void)
 {
 	int ret;
 	/* Unlock the rtc's registers */
 	__raw_writel(0x83e70b13, IO_ADDRESS(DA8XX_RTC_BASE + 0x6c));
 	__raw_writel(0x95a4f1e0, IO_ADDRESS(DA8XX_RTC_BASE + 0x70));
 	ret = platform_device_register(&da8xx_rtc_device);
 	if (!ret)
 		/* Atleast on DA850, RTC is a wakeup source */
 		device_init_wakeup(&da8xx_rtc_device.dev, true);
 	return ret;
 }
+static void __iomem *da8xx_ddr2_ctlr_base;
+void __iomem * __init da8xx_get_mem_ctlr(void)
+{
+	if (da8xx_ddr2_ctlr_base)
+		return da8xx_ddr2_ctlr_base;
+	da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
+	if (!da8xx_ddr2_ctlr_base)
+		pr_warning("%s: Unable to map DDR2 controller",	__func__);
+	return da8xx_ddr2_ctlr_base;
+}
 static struct resource da8xx_cpuidle_resources[] = {
 	{
 		.start		= DA8XX_DDR2_CTL_BASE,
 		.end		= DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
 		.flags		= IORESOURCE_MEM,
 	},
 };
 /* DA8XX devices support DDR2 power down */
 static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
 	.ddr2_pdown	= 1,
 };
 static struct platform_device da8xx_cpuidle_device = {
 	.name			= "cpuidle-davinci",
 	.num_resources		= ARRAY_SIZE(da8xx_cpuidle_resources),
 	.resource		= da8xx_cpuidle_resources,
 	.dev = {
 		.platform_data	= &da8xx_cpuidle_pdata,
 	},
 };
 int __init da8xx_register_cpuidle(void)
 {
+	da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
 	return platform_device_register(&da8xx_cpuidle_device);
 }

arch/arm/mach-davinci/include/mach/cpuidle.h

Diff comments View file @ 948c66d

 /*
  * TI DaVinci cpuidle platform support
  *
  * 2009 (C) Texas Instruments, Inc. http://www.ti.com/
  *
  * This file is licensed under the terms of the GNU General Public License
  * version 2. This program is licensed "as is" without any warranty of any
  * kind, whether express or implied.
  */
 #ifndef _MACH_DAVINCI_CPUIDLE_H
 #define _MACH_DAVINCI_CPUIDLE_H
 struct davinci_cpuidle_config {
 	u32 ddr2_pdown;
+	void __iomem *ddr2_ctlr_base;
 };
 #endif

arch/arm/mach-davinci/include/mach/da8xx.h

Diff comments View file @ 948c66d

 /*
  * Chip specific defines for DA8XX/OMAP L1XX SoC
  *
  * Author: Mark A. Greer <mgreer@mvista.com>
  *
  * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under
  * the terms of the GNU General Public License version 2. This program
  * is licensed "as is" without any warranty of any kind, whether express
  * or implied.
  */
 #ifndef __ASM_ARCH_DAVINCI_DA8XX_H
 #define __ASM_ARCH_DAVINCI_DA8XX_H
 #include <video/da8xx-fb.h>
 #include <mach/serial.h>
 #include <mach/edma.h>
 #include <mach/i2c.h>
 #include <mach/emac.h>
 #include <mach/asp.h>
 #include <mach/mmc.h>
 #include <mach/usb.h>
 extern void __iomem *da8xx_syscfg0_base;
 extern void __iomem *da8xx_syscfg1_base;
 /*
  * The cp_intc interrupt controller for the da8xx isn't in the same
  * chunk of physical memory space as the other registers (like it is
  * on the davincis) so it needs to be mapped separately.  It will be
  * mapped early on when the I/O space is mapped and we'll put it just
  * before the I/O space in the processor's virtual memory space.
  */
 #define DA8XX_CP_INTC_BASE	0xfffee000
 #define DA8XX_CP_INTC_SIZE	SZ_8K
 #define DA8XX_CP_INTC_VIRT	(IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K)
 #define DA8XX_SYSCFG0_BASE	(IO_PHYS + 0x14000)
 #define DA8XX_SYSCFG0_VIRT(x)	(da8xx_syscfg0_base + (x))
 #define DA8XX_JTAG_ID_REG	0x18
 #define DA8XX_CFGCHIP0_REG	0x17c
 #define DA8XX_CFGCHIP2_REG	0x184
 #define DA8XX_CFGCHIP3_REG	0x188
 #define DA8XX_SYSCFG1_BASE	(IO_PHYS + 0x22C000)
 #define DA8XX_SYSCFG1_VIRT(x)	(da8xx_syscfg1_base + (x))
 #define DA8XX_PSC0_BASE		0x01c10000
 #define DA8XX_PLL0_BASE		0x01c11000
 #define DA8XX_TIMER64P0_BASE	0x01c20000
 #define DA8XX_TIMER64P1_BASE	0x01c21000
 #define DA8XX_GPIO_BASE		0x01e26000
 #define DA8XX_PSC1_BASE		0x01e27000
 #define DA8XX_LCD_CNTRL_BASE	0x01e13000
 #define DA8XX_MMCSD0_BASE	0x01c40000
 #define DA8XX_AEMIF_CS2_BASE	0x60000000
 #define DA8XX_AEMIF_CS3_BASE	0x62000000
 #define DA8XX_AEMIF_CTL_BASE	0x68000000
 #define DA8XX_DDR2_CTL_BASE	0xb0000000
 #define PINMUX0			0x00
 #define PINMUX1			0x04
 #define PINMUX2			0x08
 #define PINMUX3			0x0c
 #define PINMUX4			0x10
 #define PINMUX5			0x14
 #define PINMUX6			0x18
 #define PINMUX7			0x1c
 #define PINMUX8			0x20
 #define PINMUX9			0x24
 #define PINMUX10		0x28
 #define PINMUX11		0x2c
 #define PINMUX12		0x30
 #define PINMUX13		0x34
 #define PINMUX14		0x38
 #define PINMUX15		0x3c
 #define PINMUX16		0x40
 #define PINMUX17		0x44
 #define PINMUX18		0x48
 #define PINMUX19		0x4c
 void __init da830_init(void);
 void __init da850_init(void);
 int da8xx_register_edma(void);
 int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata);
 int da8xx_register_watchdog(void);
 int da8xx_register_usb20(unsigned mA, unsigned potpgt);
 int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata);
 int da8xx_register_emac(void);
 int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata);
 int da8xx_register_mmcsd0(struct davinci_mmc_config *config);
 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata);
 int da8xx_register_rtc(void);
 int da850_register_cpufreq(void);
 int da8xx_register_cpuidle(void);
+void __iomem * __init da8xx_get_mem_ctlr(void);
 extern struct platform_device da8xx_serial_device;
 extern struct emac_platform_data da8xx_emac_pdata;
 extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata;
 extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata;
 extern const short da830_emif25_pins[];
 extern const short da830_spi0_pins[];
 extern const short da830_spi1_pins[];
 extern const short da830_mmc_sd_pins[];
 extern const short da830_uart0_pins[];
 extern const short da830_uart1_pins[];
 extern const short da830_uart2_pins[];
 extern const short da830_usb20_pins[];
 extern const short da830_usb11_pins[];
 extern const short da830_uhpi_pins[];
 extern const short da830_cpgmac_pins[];
 extern const short da830_emif3c_pins[];
 extern const short da830_mcasp0_pins[];
 extern const short da830_mcasp1_pins[];
 extern const short da830_mcasp2_pins[];
 extern const short da830_i2c0_pins[];
 extern const short da830_i2c1_pins[];
 extern const short da830_lcdcntl_pins[];
 extern const short da830_pwm_pins[];
 extern const short da830_ecap0_pins[];
 extern const short da830_ecap1_pins[];
 extern const short da830_ecap2_pins[];
 extern const short da830_eqep0_pins[];
 extern const short da830_eqep1_pins[];
 extern const short da850_uart0_pins[];
 extern const short da850_uart1_pins[];
 extern const short da850_uart2_pins[];
 extern const short da850_i2c0_pins[];
 extern const short da850_i2c1_pins[];
 extern const short da850_cpgmac_pins[];
 extern const short da850_rmii_pins[];
 extern const short da850_mcasp_pins[];
 extern const short da850_lcdcntl_pins[];
 extern const short da850_mmcsd0_pins[];
 extern const short da850_nand_pins[];
 extern const short da850_nor_pins[];
 int da8xx_pinmux_setup(const short pins[]);
 #endif /* __ASM_ARCH_DAVINCI_DA8XX_H */