Eric Lee / smarc-fsl-linux-kernel

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Commit 95f3be798472f63b495ca4712af005ea5ac7aa47

Authored by Kan Liang
Committed by Ingo Molnar
1 parent 10e9e7bd59

perf/x86/intel/uncore: Add enable_box for client MSR uncore 

There are bug reports about miscounting uncore counters on some
client machines like Sandybridge, Broadwell and Skylake. It is
very likely to be observed on idle systems.

This issue is caused by a hardware issue. PERF_GLOBAL_CTL could be
cleared after Package C7, and nothing will be count.
The related errata (HSD 158) could be found in:

  www.intel.com/content/dam/www/public/us/en/documents/specification-updates/4th-gen-core-family-desktop-specification-update.pdf

This patch tries to work around this issue by re-enabling PERF_GLOBAL_CTL
in ->enable_box(). The workaround does not cover all cases. It helps for new
events after returning from C7. But it cannot prevent C7, it will still
miscount if a counter is already active.

There is no drawback in leaving it enabled, so it does not need
disable_box() here.

Signed-off-by: Kan Liang <kan.liang@intel.com>
Cc: <stable@vger.kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Link: http://lkml.kernel.org/r/1470925874-59943-1-git-send-email-kan.liang@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>

Showing 1 changed file with 14 additions and 0 deletions Side-by-side Diff

arch/x86/events/intel/uncore_snb.c
Diff comments   View file @ 95f3be7
... ... @@ -100,6 +100,12 @@
100 100 }
101 101 }
102 102  
  103 +static void snb_uncore_msr_enable_box(struct intel_uncore_box *box)
  104 +{
  105 + wrmsrl(SNB_UNC_PERF_GLOBAL_CTL,
  106 + SNB_UNC_GLOBAL_CTL_EN | SNB_UNC_GLOBAL_CTL_CORE_ALL);
  107 +}
  108 +
103 109 static void snb_uncore_msr_exit_box(struct intel_uncore_box *box)
104 110 {
105 111 if (box->pmu->pmu_idx == 0)
... ... @@ -127,6 +133,7 @@
127 133  
128 134 static struct intel_uncore_ops snb_uncore_msr_ops = {
129 135 .init_box = snb_uncore_msr_init_box,
  136 + .enable_box = snb_uncore_msr_enable_box,
130 137 .exit_box = snb_uncore_msr_exit_box,
131 138 .disable_event = snb_uncore_msr_disable_event,
132 139 .enable_event = snb_uncore_msr_enable_event,
... ... @@ -192,6 +199,12 @@
192 199 }
193 200 }
194 201  
  202 +static void skl_uncore_msr_enable_box(struct intel_uncore_box *box)
  203 +{
  204 + wrmsrl(SKL_UNC_PERF_GLOBAL_CTL,
  205 + SNB_UNC_GLOBAL_CTL_EN | SKL_UNC_GLOBAL_CTL_CORE_ALL);
  206 +}
  207 +
195 208 static void skl_uncore_msr_exit_box(struct intel_uncore_box *box)
196 209 {
197 210 if (box->pmu->pmu_idx == 0)
... ... @@ -200,6 +213,7 @@
200 213  
201 214 static struct intel_uncore_ops skl_uncore_msr_ops = {
202 215 .init_box = skl_uncore_msr_init_box,
  216 + .enable_box = skl_uncore_msr_enable_box,
203 217 .exit_box = skl_uncore_msr_exit_box,
204 218 .disable_event = snb_uncore_msr_disable_event,
205 219 .enable_event = snb_uncore_msr_enable_event,