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Commit 97b09da4ee36ec4bd0f6e16b84b4bb6fa05db110

Authored by Arnd Bergmann
Committed by Eric Miao
1 parent 7272889d3f
Exists in master and in 38 other branches 8mp-imx_5.4.70_2.3.0, 8qm-imx_5.4.70_2.3.0, emb_imx_lf-5.15.y, emb_lf-6.1.y, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, imx_4.1.15_1.0.0_ga, pitx_8mp_lf-5.10.y, rt-smarc-imx_4.1.15_1.0.0_ga, rt_linux_5.15.71, smarc-8m-android-11.0.0_2.0.0, smarc-imx6_4.14.98_2.0.0_ga, smarc-imx6_4.9.88_2.0.0_ga, smarc-imx7_4.14.98_2.0.0_ga, smarc-imx7_4.9.11_1.0.0_ga, smarc-imx7_4.9.88_2.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-imx_4.1.15_1.0.0_ga, smarc-imx_4.9.11_1.0.0_ga, smarc-imx_4.9.51_imx8m_ga, smarc-imx_4.9.88_2.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_1.2.0_ga, smarc_8m_00d0_imx_4.14.98_2.0.0_ga, smarc_8m_imx_4.14.78_1.0.0_ga, smarc_8m_imx_4.14.98_2.0.0_ga, smarc_8m_imx_4.19.35_1.1.0, smarc_8mm_imx_4.14.78_1.0.0_ga, smarc_8mm_imx_4.14.98_2.0.0_ga, smarc_8mm_imx_4.19.35_1.1.0, smarc_8mm_imx_5.4.24_2.1.0, smarc_8mp_lf-5.10.y, smarc_8mq_imx_5.4.24_2.1.0, smarc_8mq_lf-5.10.y, smarc_imx_lf-5.15.y

ARM: pxa: use correct __iomem annotations 

This tries to clear up the confusion between integers and iomem pointers
in the marvell pxa platform. MMIO addresses are supposed to be __iomem*
values, in order to let the Linux type checking work correctly. This
patch moves the cast to __iomem as far back as possible, to the place
where the MMIO virtual address windows are defined.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>

Showing 28 changed files with 65 additions and 58 deletions Side-by-side Diff

arch/arm/include/asm/hardware/it8152.h
Diff comments   View file @ 97b09da
... ... @@ -9,7 +9,7 @@
9 9  
10 10 #ifndef __ASM_HARDWARE_IT8152_H
11 11 #define __ASM_HARDWARE_IT8152_H
12   -extern unsigned long it8152_base_address;
  12 +extern void __iomem *it8152_base_address;
13 13  
14 14 #define IT8152_IO_BASE (it8152_base_address + 0x03e00000)
15 15 #define IT8152_CFGREG_BASE (it8152_base_address + 0x03f00000)
arch/arm/mach-mmp/clock.h
Diff comments   View file @ 97b09da
... ... @@ -30,7 +30,7 @@
30 30  
31 31 #define APBC_CLK(_name, _reg, _fnclksel, _rate) \
32 32 struct clk clk_##_name = { \
33   - .clk_rst = (void __iomem *)APBC_##_reg, \
  33 + .clk_rst = APBC_##_reg, \
34 34 .fnclksel = _fnclksel, \
35 35 .rate = _rate, \
36 36 .ops = &apbc_clk_ops, \
... ... @@ -38,7 +38,7 @@
38 38  
39 39 #define APBC_CLK_OPS(_name, _reg, _fnclksel, _rate, _ops) \
40 40 struct clk clk_##_name = { \
41   - .clk_rst = (void __iomem *)APBC_##_reg, \
  41 + .clk_rst = APBC_##_reg, \
42 42 .fnclksel = _fnclksel, \
43 43 .rate = _rate, \
44 44 .ops = _ops, \
... ... @@ -46,7 +46,7 @@
46 46  
47 47 #define APMU_CLK(_name, _reg, _eval, _rate) \
48 48 struct clk clk_##_name = { \
49   - .clk_rst = (void __iomem *)APMU_##_reg, \
  49 + .clk_rst = APMU_##_reg, \
50 50 .enable_val = _eval, \
51 51 .rate = _rate, \
52 52 .ops = &apmu_clk_ops, \
... ... @@ -54,7 +54,7 @@
54 54  
55 55 #define APMU_CLK_OPS(_name, _reg, _eval, _rate, _ops) \
56 56 struct clk clk_##_name = { \
57   - .clk_rst = (void __iomem *)APMU_##_reg, \
  57 + .clk_rst = APMU_##_reg, \
58 58 .enable_val = _eval, \
59 59 .rate = _rate, \
60 60 .ops = _ops, \
arch/arm/mach-mmp/common.c
Diff comments   View file @ 97b09da
... ... @@ -27,12 +27,12 @@
27 27 static struct map_desc standard_io_desc[] __initdata = {
28 28 {
29 29 .pfn = __phys_to_pfn(APB_PHYS_BASE),
30   - .virtual = APB_VIRT_BASE,
  30 + .virtual = (unsigned long)APB_VIRT_BASE,
31 31 .length = APB_PHYS_SIZE,
32 32 .type = MT_DEVICE,
33 33 }, {
34 34 .pfn = __phys_to_pfn(AXI_PHYS_BASE),
35   - .virtual = AXI_VIRT_BASE,
  35 + .virtual = (unsigned long)AXI_VIRT_BASE,
36 36 .length = AXI_PHYS_SIZE,
37 37 .type = MT_DEVICE,
38 38 },
arch/arm/mach-mmp/include/mach/addr-map.h
Diff comments   View file @ 97b09da
... ... @@ -11,6 +11,12 @@
11 11 #ifndef __ASM_MACH_ADDR_MAP_H
12 12 #define __ASM_MACH_ADDR_MAP_H
13 13  
  14 +#ifndef __ASSEMBLER__
  15 +#define IOMEM(x) ((void __iomem *)(x))
  16 +#else
  17 +#define IOMEM(x) (x)
  18 +#endif
  19 +
14 20 /* APB - Application Subsystem Peripheral Bus
15 21 *
16 22 * NOTE: the DMA controller registers are actually on the AXI fabric #1
17 23  
... ... @@ -18,11 +24,11 @@
18 24 * peripherals on APB, let's count it into the ABP mapping area.
19 25 */
20 26 #define APB_PHYS_BASE 0xd4000000
21   -#define APB_VIRT_BASE 0xfe000000
  27 +#define APB_VIRT_BASE IOMEM(0xfe000000)
22 28 #define APB_PHYS_SIZE 0x00200000
23 29  
24 30 #define AXI_PHYS_BASE 0xd4200000
25   -#define AXI_VIRT_BASE 0xfe200000
  31 +#define AXI_VIRT_BASE IOMEM(0xfe200000)
26 32 #define AXI_PHYS_SIZE 0x00200000
27 33  
28 34 /* Static Memory Controller - Chip Select 0 and 1 */
arch/arm/mach-mmp/mmp2.c
Diff comments   View file @ 97b09da
... ... @@ -87,7 +87,8 @@
87 87  
88 88 void mmp2_clear_pmic_int(void)
89 89 {
90   - unsigned long mfpr_pmic, data;
  90 + void __iomem *mfpr_pmic;
  91 + unsigned long data;
91 92  
92 93 mfpr_pmic = APB_VIRT_BASE + 0x1e000 + 0x2c4;
93 94 data = __raw_readl(mfpr_pmic);
arch/arm/mach-pxa/balloon3.c
Diff comments   View file @ 97b09da
... ... @@ -591,7 +591,7 @@
591 591 BALLOON3_NAND_CONTROL_REG);
592 592 if (balloon3_ctl_set)
593 593 __raw_writel(balloon3_ctl_set,
594   - BALLOON3_NAND_CONTROL_REG |
  594 + BALLOON3_NAND_CONTROL_REG +
595 595 BALLOON3_FPGA_SETnCLR);
596 596 }
597 597  
... ... @@ -608,7 +608,7 @@
608 608 __raw_writew(
609 609 BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 |
610 610 BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3,
611   - BALLOON3_NAND_CONTROL_REG | BALLOON3_FPGA_SETnCLR);
  611 + BALLOON3_NAND_CONTROL_REG + BALLOON3_FPGA_SETnCLR);
612 612  
613 613 /* Deassert correct nCE line */
614 614 __raw_writew(BALLOON3_NAND_CONTROL_FLCE0 << chip,
... ... @@ -626,7 +626,7 @@
626 626 int ret;
627 627  
628 628 __raw_writew(BALLOON3_NAND_CONTROL2_16BIT,
629   - BALLOON3_NAND_CONTROL2_REG | BALLOON3_FPGA_SETnCLR);
  629 + BALLOON3_NAND_CONTROL2_REG + BALLOON3_FPGA_SETnCLR);
630 630  
631 631 ver = __raw_readw(BALLOON3_FPGA_VER);
632 632 if (ver < 0x4f08)
... ... @@ -649,7 +649,7 @@
649 649 BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 |
650 650 BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3 |
651 651 BALLOON3_NAND_CONTROL_FLWP,
652   - BALLOON3_NAND_CONTROL_REG | BALLOON3_FPGA_SETnCLR);
  652 + BALLOON3_NAND_CONTROL_REG + BALLOON3_FPGA_SETnCLR);
653 653 return 0;
654 654  
655 655 err2:
... ... @@ -807,7 +807,7 @@
807 807  
808 808 static struct map_desc balloon3_io_desc[] __initdata = {
809 809 { /* CPLD/FPGA */
810   - .virtual = BALLOON3_FPGA_VIRT,
  810 + .virtual = (unsigned long)BALLOON3_FPGA_VIRT,
811 811 .pfn = __phys_to_pfn(BALLOON3_FPGA_PHYS),
812 812 .length = BALLOON3_FPGA_LENGTH,
813 813 .type = MT_DEVICE,
arch/arm/mach-pxa/cm-x2xx-pci.c
Diff comments   View file @ 97b09da
... ... @@ -26,7 +26,7 @@
26 26  
27 27 #include <asm/hardware/it8152.h>
28 28  
29   -unsigned long it8152_base_address;
  29 +void __iomem *it8152_base_address;
30 30 static int cmx2xx_it8152_irq_gpio;
31 31  
32 32 static void cmx2xx_it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
arch/arm/mach-pxa/cm-x2xx.c
Diff comments   View file @ 97b09da
... ... @@ -39,7 +39,7 @@
39 39 #define CMX2XX_NR_IRQS (IRQ_BOARD_START + 40)
40 40  
41 41 /* virtual addresses for statically mapped regions */
42   -#define CMX2XX_VIRT_BASE (0xe8000000)
  42 +#define CMX2XX_VIRT_BASE (void __iomem *)(0xe8000000)
43 43 #define CMX2XX_IT8152_VIRT (CMX2XX_VIRT_BASE)
44 44  
45 45 /* physical address if local-bus attached devices */
... ... @@ -482,7 +482,7 @@
482 482 /* Map PCI companion statically */
483 483 static struct map_desc cmx2xx_io_desc[] __initdata = {
484 484 [0] = { /* PCI bridge */
485   - .virtual = CMX2XX_IT8152_VIRT,
  485 + .virtual = (unsigned long)CMX2XX_IT8152_VIRT,
486 486 .pfn = __phys_to_pfn(PXA_CS4_PHYS),
487 487 .length = SZ_64M,
488 488 .type = MT_DEVICE
arch/arm/mach-pxa/include/mach/addr-map.h
Diff comments   View file @ 97b09da
... ... @@ -20,7 +20,7 @@
20 20 * Peripheral Bus
21 21 */
22 22 #define PERIPH_PHYS 0x40000000
23   -#define PERIPH_VIRT 0xf2000000
  23 +#define PERIPH_VIRT IOMEM(0xf2000000)
24 24 #define PERIPH_SIZE 0x02000000
25 25  
26 26 /*
27 27  
28 28  
... ... @@ -28,21 +28,21 @@
28 28 */
29 29 #define PXA2XX_SMEMC_PHYS 0x48000000
30 30 #define PXA3XX_SMEMC_PHYS 0x4a000000
31   -#define SMEMC_VIRT 0xf6000000
  31 +#define SMEMC_VIRT IOMEM(0xf6000000)
32 32 #define SMEMC_SIZE 0x00100000
33 33  
34 34 /*
35 35 * Dynamic Memory Controller (only on PXA3xx)
36 36 */
37 37 #define DMEMC_PHYS 0x48100000
38   -#define DMEMC_VIRT 0xf6100000
  38 +#define DMEMC_VIRT IOMEM(0xf6100000)
39 39 #define DMEMC_SIZE 0x00100000
40 40  
41 41 /*
42 42 * Internal Memory Controller (PXA27x and later)
43 43 */
44 44 #define IMEMC_PHYS 0x58000000
45   -#define IMEMC_VIRT 0xfe000000
  45 +#define IMEMC_VIRT IOMEM(0xfe000000)
46 46 #define IMEMC_SIZE 0x00100000
47 47  
48 48 #endif /* __ASM_MACH_ADDR_MAP_H */
arch/arm/mach-pxa/include/mach/balloon3.h
Diff comments   View file @ 97b09da
... ... @@ -23,7 +23,7 @@
23 23 };
24 24  
25 25 #define BALLOON3_FPGA_PHYS PXA_CS4_PHYS
26   -#define BALLOON3_FPGA_VIRT (0xf1000000) /* as per balloon2 */
  26 +#define BALLOON3_FPGA_VIRT IOMEM(0xf1000000) /* as per balloon2 */
27 27 #define BALLOON3_FPGA_LENGTH 0x01000000
28 28  
29 29 #define BALLOON3_FPGA_SETnCLR (0x1000)
arch/arm/mach-pxa/include/mach/hardware.h
Diff comments   View file @ 97b09da
... ... @@ -36,22 +36,23 @@
36 36 * Note that not all PXA2xx chips implement all those addresses, and the
37 37 * kernel only maps the minimum needed range of this mapping.
38 38 */
39   -#define io_p2v(x) (0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
40 39 #define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
  40 +#define io_p2v(x) IOMEM(0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
41 41  
42 42 #ifndef __ASSEMBLY__
  43 +# define IOMEM(x) ((void __iomem *)(x))
  44 +# define __REG(x) (*((volatile u32 __iomem *)io_p2v(x)))
43 45  
44   -# define __REG(x) (*((volatile u32 *)io_p2v(x)))
45   -
46 46 /* With indexed regs we don't want to feed the index through io_p2v()
47 47 especially if it is a variable, otherwise horrible code will result. */
48 48 # define __REG2(x,y) \
49   - (*(volatile u32 *)((u32)&__REG(x) + (y)))
  49 + (*(volatile u32 __iomem*)((u32)&__REG(x) + (y)))
50 50  
51 51 # define __PREG(x) (io_v2p((u32)&(x)))
52 52  
53 53 #else
54 54  
  55 +# define IOMEM(x) x
55 56 # define __REG(x) io_p2v(x)
56 57 # define __PREG(x) io_v2p(x)
57 58  
arch/arm/mach-pxa/include/mach/lpd270.h
Diff comments   View file @ 97b09da
... ... @@ -13,13 +13,13 @@
13 13 #define __ASM_ARCH_LPD270_H
14 14  
15 15 #define LPD270_CPLD_PHYS PXA_CS2_PHYS
16   -#define LPD270_CPLD_VIRT 0xf0000000
  16 +#define LPD270_CPLD_VIRT IOMEM(0xf0000000)
17 17 #define LPD270_CPLD_SIZE 0x00100000
18 18  
19 19 #define LPD270_ETH_PHYS (PXA_CS2_PHYS + 0x01000000)
20 20  
21 21 /* CPLD registers */
22   -#define LPD270_CPLD_REG(x) ((unsigned long)(LPD270_CPLD_VIRT + (x)))
  22 +#define LPD270_CPLD_REG(x) (LPD270_CPLD_VIRT + (x))
23 23 #define LPD270_CONTROL LPD270_CPLD_REG(0x00)
24 24 #define LPD270_PERIPHERAL0 LPD270_CPLD_REG(0x04)
25 25 #define LPD270_PERIPHERAL1 LPD270_CPLD_REG(0x08)
arch/arm/mach-pxa/include/mach/mtd-xip.h
Diff comments   View file @ 97b09da
... ... @@ -16,7 +16,6 @@
16 16 #define __ARCH_PXA_MTD_XIP_H__
17 17  
18 18 #include <mach/regs-ost.h>
19   -#include <mach/regs-intc.h>
20 19  
21 20 #define xip_irqpending() (ICIP & ICMR)
22 21  
arch/arm/mach-pxa/include/mach/palmtx.h
Diff comments   View file @ 97b09da
... ... @@ -71,7 +71,7 @@
71 71  
72 72 /* Various addresses */
73 73 #define PALMTX_PCMCIA_PHYS 0x28000000
74   -#define PALMTX_PCMCIA_VIRT 0xf0000000
  74 +#define PALMTX_PCMCIA_VIRT IOMEM(0xf0000000)
75 75 #define PALMTX_PCMCIA_SIZE 0x100000
76 76  
77 77 #define PALMTX_PHYS_RAM_START 0xa0000000
... ... @@ -84,8 +84,8 @@
84 84  
85 85 #define PALMTX_NAND_ALE_PHYS (PALMTX_PHYS_NAND_START | (1 << 24))
86 86 #define PALMTX_NAND_CLE_PHYS (PALMTX_PHYS_NAND_START | (1 << 25))
87   -#define PALMTX_NAND_ALE_VIRT 0xff100000
88   -#define PALMTX_NAND_CLE_VIRT 0xff200000
  87 +#define PALMTX_NAND_ALE_VIRT IOMEM(0xff100000)
  88 +#define PALMTX_NAND_CLE_VIRT IOMEM(0xff200000)
89 89  
90 90 /* TOUCHSCREEN */
91 91 #define AC97_LINK_FRAME 21
arch/arm/mach-pxa/include/mach/smemc.h
Diff comments   View file @ 97b09da
... ... @@ -13,7 +13,7 @@
13 13  
14 14 #define PXA2XX_SMEMC_BASE 0x48000000
15 15 #define PXA3XX_SMEMC_BASE 0x4a000000
16   -#define SMEMC_VIRT 0xf6000000
  16 +#define SMEMC_VIRT IOMEM(0xf6000000)
17 17  
18 18 #define MDCNFG (SMEMC_VIRT + 0x00) /* SDRAM Configuration Register 0 */
19 19 #define MDREFR (SMEMC_VIRT + 0x04) /* SDRAM Refresh Control Register */
arch/arm/mach-pxa/include/mach/zeus.h
Diff comments   View file @ 97b09da
... ... @@ -68,7 +68,7 @@
68 68 * Be gentle, and remap that over 32kB...
69 69 */
70 70  
71   -#define ZEUS_CPLD (0xf0000000)
  71 +#define ZEUS_CPLD IOMEM(0xf0000000)
72 72 #define ZEUS_CPLD_VERSION (ZEUS_CPLD + 0x0000)
73 73 #define ZEUS_CPLD_ISA_IRQ (ZEUS_CPLD + 0x1000)
74 74 #define ZEUS_CPLD_CONTROL (ZEUS_CPLD + 0x2000)
... ... @@ -76,7 +76,7 @@
76 76 /* CPLD register bits */
77 77 #define ZEUS_CPLD_CONTROL_CF_RST 0x01
78 78  
79   -#define ZEUS_PC104IO (0xf1000000)
  79 +#define ZEUS_PC104IO IOMEM(0xf1000000)
80 80  
81 81 #define ZEUS_SRAM_SIZE (256 * 1024)
82 82  
arch/arm/mach-pxa/irq.c
Diff comments   View file @ 97b09da
... ... @@ -25,7 +25,7 @@
25 25  
26 26 #include "generic.h"
27 27  
28   -#define IRQ_BASE (void __iomem *)io_p2v(0x40d00000)
  28 +#define IRQ_BASE io_p2v(0x40d00000)
29 29  
30 30 #define ICIP (0x000)
31 31 #define ICMR (0x004)
... ... @@ -63,7 +63,7 @@
63 63 0x40d00130,
64 64 };
65 65  
66   - return (void __iomem *)io_p2v(phys_base[i]);
  66 + return io_p2v(phys_base[i]);
67 67 }
68 68  
69 69 void pxa_mask_irq(struct irq_data *d)
arch/arm/mach-pxa/lpd270.c
Diff comments   View file @ 97b09da
... ... @@ -480,7 +480,7 @@
480 480  
481 481 static struct map_desc lpd270_io_desc[] __initdata = {
482 482 {
483   - .virtual = LPD270_CPLD_VIRT,
  483 + .virtual = (unsigned long)LPD270_CPLD_VIRT,
484 484 .pfn = __phys_to_pfn(LPD270_CPLD_PHYS),
485 485 .length = LPD270_CPLD_SIZE,
486 486 .type = MT_DEVICE,
arch/arm/mach-pxa/palmtx.c
Diff comments   View file @ 97b09da
... ... @@ -247,7 +247,7 @@
247 247 unsigned int ctrl)
248 248 {
249 249 struct nand_chip *this = mtd->priv;
250   - unsigned long nandaddr = (unsigned long)this->IO_ADDR_W;
  250 + char __iomem *nandaddr = this->IO_ADDR_W;
251 251  
252 252 if (cmd == NAND_CMD_NONE)
253 253 return;
254 254  
255 255  
... ... @@ -315,17 +315,17 @@
315 315 ******************************************************************************/
316 316 static struct map_desc palmtx_io_desc[] __initdata = {
317 317 {
318   - .virtual = PALMTX_PCMCIA_VIRT,
  318 + .virtual = (unsigned long)PALMTX_PCMCIA_VIRT,
319 319 .pfn = __phys_to_pfn(PALMTX_PCMCIA_PHYS),
320 320 .length = PALMTX_PCMCIA_SIZE,
321 321 .type = MT_DEVICE,
322 322 }, {
323   - .virtual = PALMTX_NAND_ALE_VIRT,
  323 + .virtual = (unsigned long)PALMTX_NAND_ALE_VIRT,
324 324 .pfn = __phys_to_pfn(PALMTX_NAND_ALE_PHYS),
325 325 .length = SZ_1M,
326 326 .type = MT_DEVICE,
327 327 }, {
328   - .virtual = PALMTX_NAND_CLE_VIRT,
  328 + .virtual = (unsigned long)PALMTX_NAND_CLE_VIRT,
329 329 .pfn = __phys_to_pfn(PALMTX_NAND_CLE_PHYS),
330 330 .length = SZ_1M,
331 331 .type = MT_DEVICE,
arch/arm/mach-pxa/pxa25x.c
Diff comments   View file @ 97b09da
... ... @@ -324,7 +324,7 @@
324 324  
325 325 static struct map_desc pxa25x_io_desc[] __initdata = {
326 326 { /* Mem Ctl */
327   - .virtual = SMEMC_VIRT,
  327 + .virtual = (unsigned long)SMEMC_VIRT,
328 328 .pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE),
329 329 .length = 0x00200000,
330 330 .type = MT_DEVICE
arch/arm/mach-pxa/pxa27x.c
Diff comments   View file @ 97b09da
... ... @@ -390,7 +390,7 @@
390 390  
391 391 static struct map_desc pxa27x_io_desc[] __initdata = {
392 392 { /* Mem Ctl */
393   - .virtual = SMEMC_VIRT,
  393 + .virtual = (unsigned long)SMEMC_VIRT,
394 394 .pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE),
395 395 .length = 0x00200000,
396 396 .type = MT_DEVICE
arch/arm/mach-pxa/pxa3xx.c
Diff comments   View file @ 97b09da
... ... @@ -394,7 +394,7 @@
394 394  
395 395 static struct map_desc pxa3xx_io_desc[] __initdata = {
396 396 { /* Mem Ctl */
397   - .virtual = SMEMC_VIRT,
  397 + .virtual = (unsigned long)SMEMC_VIRT,
398 398 .pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE),
399 399 .length = 0x00200000,
400 400 .type = MT_DEVICE
arch/arm/mach-pxa/zeus.c
Diff comments   View file @ 97b09da
... ... @@ -860,25 +860,25 @@
860 860  
861 861 static struct map_desc zeus_io_desc[] __initdata = {
862 862 {
863   - .virtual = ZEUS_CPLD_VERSION,
  863 + .virtual = (unsigned long)ZEUS_CPLD_VERSION,
864 864 .pfn = __phys_to_pfn(ZEUS_CPLD_VERSION_PHYS),
865 865 .length = 0x1000,
866 866 .type = MT_DEVICE,
867 867 },
868 868 {
869   - .virtual = ZEUS_CPLD_ISA_IRQ,
  869 + .virtual = (unsigned long)ZEUS_CPLD_ISA_IRQ,
870 870 .pfn = __phys_to_pfn(ZEUS_CPLD_ISA_IRQ_PHYS),
871 871 .length = 0x1000,
872 872 .type = MT_DEVICE,
873 873 },
874 874 {
875   - .virtual = ZEUS_CPLD_CONTROL,
  875 + .virtual = (unsigned long)ZEUS_CPLD_CONTROL,
876 876 .pfn = __phys_to_pfn(ZEUS_CPLD_CONTROL_PHYS),
877 877 .length = 0x1000,
878 878 .type = MT_DEVICE,
879 879 },
880 880 {
881   - .virtual = ZEUS_PC104IO,
  881 + .virtual = (unsigned long)ZEUS_PC104IO,
882 882 .pfn = __phys_to_pfn(ZEUS_PC104IO_PHYS),
883 883 .length = 0x00800000,
884 884 .type = MT_DEVICE,
arch/arm/plat-pxa/gpio.c
Diff comments   View file @ 97b09da
... ... @@ -122,7 +122,7 @@
122 122 struct gpio_chip *c = &chips[i].chip;
123 123  
124 124 sprintf(chips[i].label, "gpio-%d", i);
125   - chips[i].regbase = (void __iomem *)GPIO_BANK(i);
  125 + chips[i].regbase = GPIO_BANK(i);
126 126  
127 127 c->base = gpio;
128 128 c->label = chips[i].label;
arch/arm/plat-pxa/include/plat/mfp.h
Diff comments   View file @ 97b09da
... ... @@ -456,7 +456,7 @@
456 456  
457 457 #define MFP_ADDR_END { MFP_PIN_INVALID, 0 }
458 458  
459   -void __init mfp_init_base(unsigned long mfpr_base);
  459 +void __init mfp_init_base(void __iomem *mfpr_base);
460 460 void __init mfp_init_addr(struct mfp_addr_map *map);
461 461  
462 462 /*
arch/arm/plat-pxa/mfp.c
Diff comments   View file @ 97b09da
... ... @@ -229,7 +229,7 @@
229 229 spin_unlock_irqrestore(&mfp_spin_lock, flags);
230 230 }
231 231  
232   -void __init mfp_init_base(unsigned long mfpr_base)
  232 +void __init mfp_init_base(void __iomem *mfpr_base)
233 233 {
234 234 int i;
235 235  
... ... @@ -237,7 +237,7 @@
237 237 for (i = 0; i < ARRAY_SIZE(mfp_table); i++)
238 238 mfp_table[i].config = -1;
239 239  
240   - mfpr_mmio_base = (void __iomem *)mfpr_base;
  240 + mfpr_mmio_base = mfpr_base;
241 241 }
242 242  
243 243 void __init mfp_init_addr(struct mfp_addr_map *map)
drivers/pcmcia/pxa2xx_balloon3.c
Diff comments   View file @ 97b09da
... ... @@ -97,7 +97,7 @@
97 97 static int balloon3_pcmcia_configure_socket(struct soc_pcmcia_socket *skt,
98 98 const socket_state_t *state)
99 99 {
100   - __raw_writew(BALLOON3_CF_RESET, BALLOON3_CF_CONTROL_REG |
  100 + __raw_writew(BALLOON3_CF_RESET, BALLOON3_CF_CONTROL_REG +
101 101 ((state->flags & SS_RESET) ?
102 102 BALLOON3_FPGA_SETnCLR : 0));
103 103 return 0;
drivers/video/mbx/mbxfb.c
Diff comments   View file @ 97b09da
... ... @@ -34,7 +34,7 @@
34 34 #include "regs.h"
35 35 #include "reg_bits.h"
36 36  
37   -static unsigned long virt_base_2700;
  37 +static void __iomem *virt_base_2700;
38 38  
39 39 #define write_reg(val, reg) do { writel((val), (reg)); } while(0)
40 40  
... ... @@ -850,7 +850,7 @@
850 850 {
851 851 /* make frame buffer memory enter self-refresh mode */
852 852 write_reg_dly(LMPWR_MC_PWR_SRM, LMPWR);
853   - while (LMPWRSTAT != LMPWRSTAT_MC_PWR_SRM)
  853 + while (readl(LMPWRSTAT) != LMPWRSTAT_MC_PWR_SRM)
854 854 ; /* empty statement */
855 855  
856 856 /* reset the device, since it's initial state is 'mostly sleeping' */
... ... @@ -946,7 +946,7 @@
946 946 ret = -EINVAL;
947 947 goto err3;
948 948 }
949   - virt_base_2700 = (unsigned long)mfbi->reg_virt_addr;
  949 + virt_base_2700 = mfbi->reg_virt_addr;
950 950  
951 951 mfbi->fb_virt_addr = ioremap_nocache(mfbi->fb_phys_addr,
952 952 res_size(mfbi->fb_req));