Commit 980307a817e5aba53eb10323bf1d9fd2365ee2f9
1 parent
9dc8089d38
Exists in
emb_imx_lf-5.15.y
Add i.mx6 quadplus smarc card support
Showing 3 changed files with 34 additions and 69 deletions Side-by-side Diff
arch/arm/boot/dts/Makefile
| ... | ... | @@ -630,6 +630,11 @@ |
| 630 | 630 | imx6q-smarc-wxga.dtb \ |
| 631 | 631 | imx6q-smarc-xga.dtb \ |
| 632 | 632 | imx6q-smarc-1080p.dtb \ |
| 633 | + imx6qp-smarc.dtb \ | |
| 634 | + imx6qp-smarc-wvga.dtb \ | |
| 635 | + imx6qp-smarc-wxga.dtb \ | |
| 636 | + imx6qp-smarc-xga.dtb \ | |
| 637 | + imx6qp-smarc-1080p.dtb \ | |
| 633 | 638 | imx6q-solidsense.dtb \ |
| 634 | 639 | imx6q-tbs2910.dtb \ |
| 635 | 640 | imx6q-ts4900.dtb \ |
arch/arm/boot/dts/imx6q-smarc.dts
arch/arm/boot/dts/imx6qp-smarc.dts
| 1 | -// SPDX-License-Identifier: GPL-2.0+ OR MIT | |
| 1 | +// SPDX-License-Identifier: GPL-2.0+ | |
| 2 | 2 | // |
| 3 | -// Copyright 2016 Freescale Semiconductor, Inc. | |
| 3 | +// Copyright 2012 Freescale Semiconductor, Inc. | |
| 4 | +// Copyright 2011 Linaro Ltd. | |
| 5 | +// Copyright 2023 Embedian, Inc. | |
| 4 | 6 | |
| 5 | 7 | /dts-v1/; |
| 6 | 8 | |
| 7 | 9 | |
| 8 | 10 | |
| 9 | 11 | |
| 10 | 12 | |
| 11 | 13 | |
| 12 | 14 | |
| 13 | 15 | |
| 14 | 16 | |
| 15 | 17 | |
| 16 | 18 | |
| 17 | 19 | |
| 18 | 20 | |
| 19 | 21 | |
| ... | ... | @@ -12,105 +14,63 @@ |
| 12 | 14 | compatible = "fsl,imx6qp-smarc", "fsl,imx6qp"; |
| 13 | 15 | }; |
| 14 | 16 | |
| 15 | -&iomuxc { | |
| 16 | - imx6qdl-smarc { | |
| 17 | - pinctrl_usdhc2: usdhc2grp { | |
| 18 | - fsl,pins = < | |
| 19 | - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 | |
| 20 | - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 | |
| 21 | - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 | |
| 22 | - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 | |
| 23 | - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 | |
| 24 | - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 | |
| 25 | - >; | |
| 26 | - }; | |
| 17 | +&ldb { | |
| 18 | + lvds-channel@0 { | |
| 19 | + crtc = "ipu2-di0"; | |
| 20 | + }; | |
| 27 | 21 | |
| 28 | - pinctrl_usdhc3: usdhc3grp { | |
| 29 | - fsl,pins = < | |
| 30 | - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | |
| 31 | - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071 | |
| 32 | - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | |
| 33 | - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | |
| 34 | - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | |
| 35 | - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | |
| 36 | - MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 | |
| 37 | - >; | |
| 38 | - }; | |
| 39 | - | |
| 40 | - pinctrl_usdhc4: usdhc4grp { | |
| 41 | - fsl,pins = < | |
| 42 | - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 | |
| 43 | - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10071 | |
| 44 | - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 | |
| 45 | - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 | |
| 46 | - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 | |
| 47 | - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 | |
| 48 | - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 | |
| 49 | - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 | |
| 50 | - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 | |
| 51 | - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 | |
| 52 | - >; | |
| 53 | - }; | |
| 22 | + lvds-channel@1 { | |
| 23 | + crtc = "ipu2-di1"; | |
| 54 | 24 | }; |
| 55 | 25 | }; |
| 56 | 26 | |
| 57 | -&sata { | |
| 27 | +&mxcfb1 { | |
| 28 | + prefetch; | |
| 58 | 29 | status = "okay"; |
| 59 | 30 | }; |
| 60 | 31 | |
| 61 | -&pre1 { | |
| 32 | +&mxcfb2 { | |
| 33 | + prefetch; | |
| 62 | 34 | status = "okay"; |
| 63 | 35 | }; |
| 64 | 36 | |
| 65 | -&pre2 { | |
| 37 | +&mxcfb3 { | |
| 38 | + prefetch; | |
| 66 | 39 | status = "okay"; |
| 67 | 40 | }; |
| 68 | 41 | |
| 69 | -&pre3 { | |
| 42 | +&mxcfb4 { | |
| 43 | + prefetch; | |
| 70 | 44 | status = "okay"; |
| 71 | 45 | }; |
| 72 | 46 | |
| 73 | -&pre4 { | |
| 47 | +&sata { | |
| 74 | 48 | status = "okay"; |
| 75 | 49 | }; |
| 76 | 50 | |
| 77 | -&prg1 { | |
| 78 | - memory-region = <&memory>; | |
| 51 | +&pre1 { | |
| 79 | 52 | status = "okay"; |
| 80 | 53 | }; |
| 81 | 54 | |
| 82 | -&prg2 { | |
| 83 | - memory-region = <&memory>; | |
| 55 | +&pre2 { | |
| 84 | 56 | status = "okay"; |
| 85 | 57 | }; |
| 86 | 58 | |
| 87 | -&mxcfb1 { | |
| 88 | - prefetch; | |
| 59 | +&pre3 { | |
| 89 | 60 | status = "okay"; |
| 90 | 61 | }; |
| 91 | 62 | |
| 92 | -&mxcfb2 { | |
| 93 | - prefetch; | |
| 63 | +&pre4 { | |
| 94 | 64 | status = "okay"; |
| 95 | 65 | }; |
| 96 | 66 | |
| 97 | -&mxcfb3 { | |
| 98 | - prefetch; | |
| 67 | +&prg1 { | |
| 68 | + memory-region = <&memory>; | |
| 99 | 69 | status = "okay"; |
| 100 | 70 | }; |
| 101 | 71 | |
| 102 | -&mxcfb4 { | |
| 103 | - prefetch; | |
| 72 | +&prg2 { | |
| 73 | + memory-region = <&memory>; | |
| 104 | 74 | status = "okay"; |
| 105 | -}; | |
| 106 | - | |
| 107 | -&ldb { | |
| 108 | - lvds-channel@0 { | |
| 109 | - crtc = "ipu2-di0"; | |
| 110 | - }; | |
| 111 | - | |
| 112 | - lvds-channel@1 { | |
| 113 | - crtc = "ipu2-di1"; | |
| 114 | - }; | |
| 115 | 75 | }; |