Eric Lee / smarc-fsl-linux-kernel

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Commit 9941b8129030c9202aaf39114477a0e58c0d6ffc

Authored by Yongqiang Sun
Committed by Alex Deucher
1 parent 8f43965f79

drm/amd/display: Not doing optimize bandwidth if flip pending. 

[Why]
In some scenario like 1366x768 VSR enabled connected with a 4K monitor
and playing 4K video in clone mode, underflow will be observed due to
decrease dppclk when previouse surface scan isn't finished

[How]
In this use case, surface flip is switching between 4K and 1366x768,
1366x768 needs smaller dppclk, and when decrease the clk and previous
surface scan is for 4K and scan isn't done, underflow will happen.  Not
doing optimize bandwidth in case of flip pending.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Showing 1 changed file with 23 additions and 0 deletions Side-by-side Diff

drivers/gpu/drm/amd/display/dc/core/dc.c
Diff comments   View file @ 9941b81
... ... @@ -1360,6 +1360,26 @@
1360 1360 return (result == DC_OK);
1361 1361 }
1362 1362  
  1363 +static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
  1364 +{
  1365 + int i;
  1366 + struct pipe_ctx *pipe;
  1367 +
  1368 + for (i = 0; i < MAX_PIPES; i++) {
  1369 + pipe = &context->res_ctx.pipe_ctx[i];
  1370 +
  1371 + if (!pipe->plane_state)
  1372 + continue;
  1373 +
  1374 + /* Must set to false to start with, due to OR in update function */
  1375 + pipe->plane_state->status.is_flip_pending = false;
  1376 + dc->hwss.update_pending_status(pipe);
  1377 + if (pipe->plane_state->status.is_flip_pending)
  1378 + return true;
  1379 + }
  1380 + return false;
  1381 +}
  1382 +
1363 1383 bool dc_post_update_surfaces_to_stream(struct dc *dc)
1364 1384 {
1365 1385 int i;
... ... @@ -1369,6 +1389,9 @@
1369 1389 return true;
1370 1390  
1371 1391 post_surface_trace(dc);
  1392 +
  1393 + if (is_flip_pending_in_pipes(dc, context))
  1394 + return true;
1372 1395  
1373 1396 for (i = 0; i < dc->res_pool->pipe_count; i++)
1374 1397 if (context->res_ctx.pipe_ctx[i].stream == NULL ||