Eric Lee / smarc-fsl-linux-kernel

1

/*

1

/*

2

* Samsung MIPI DSIM Bridge

2

* Samsung MIPI DSIM Bridge

3

*

3

*

4

5

*

5

*

6

* This program is free software; you can redistribute it and/or modify

6

* This program is free software; you can redistribute it and/or modify

7

* it under the terms of the GNU General Public License as published by

7

* it under the terms of the GNU General Public License as published by

8

* the Free Software Foundation; either version 2 of the License, or

8

* the Free Software Foundation; either version 2 of the License, or

9

* (at your option) any later version.

9

* (at your option) any later version.

10

*

10

*

11

* This program is distributed in the hope that it will be useful,

11

* This program is distributed in the hope that it will be useful,

12

* but WITHOUT ANY WARRANTY; without even the implied warranty of

12

* but WITHOUT ANY WARRANTY; without even the implied warranty of

13

* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

13

* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

14

* GNU General Public License for more details.

14

* GNU General Public License for more details.

15

*/

15

*/

16

17

#include <asm/unaligned.h>

17

#include <asm/unaligned.h>

18

#include <linux/clk.h>

18

#include <linux/clk.h>

19

#include <linux/completion.h>

19

#include <linux/completion.h>

20

#include <linux/delay.h>

20

#include <linux/delay.h>

21

#include <linux/module.h>

21

#include <linux/module.h>

22

#include <linux/of_graph.h>

22

#include <linux/of_graph.h>

23

#include <drm/bridge/sec_mipi_dsim.h>

23

#include <drm/bridge/sec_mipi_dsim.h>

24

#include <drm/drmP.h>

24

#include <drm/drmP.h>

25

#include <drm/drm_atomic_helper.h>

25

#include <drm/drm_atomic_helper.h>

26

#include <drm/drm_bridge.h>

26

#include <drm/drm_bridge.h>

27

#include <drm/drm_connector.h>

27

#include <drm/drm_connector.h>

28

#include <drm/drm_crtc_helper.h>

28

#include <drm/drm_crtc_helper.h>

29

#include <drm/drm_encoder.h>

29

#include <drm/drm_encoder.h>

30

#include <drm/drm_fourcc.h>

30

#include <drm/drm_fourcc.h>

31

#include <drm/drm_mipi_dsi.h>

31

#include <drm/drm_mipi_dsi.h>

32

#include <drm/drm_panel.h>

32

#include <drm/drm_panel.h>

33

#include <video/videomode.h>

33

#include <video/videomode.h>

34

#include <video/mipi_display.h>

34

#include <video/mipi_display.h>

35

36

/* dsim registers */

36

/* dsim registers */

37

#define DSIM_VERSION 0x00

37

#define DSIM_VERSION 0x00

38

#define DSIM_STATUS 0x04

38

#define DSIM_STATUS 0x04

39

#define DSIM_RGB_STATUS 0x08

39

#define DSIM_RGB_STATUS 0x08

40

#define DSIM_SWRST 0x0c

40

#define DSIM_SWRST 0x0c

41

#define DSIM_CLKCTRL 0x10

41

#define DSIM_CLKCTRL 0x10

42

#define DSIM_TIMEOUT 0x14

42

#define DSIM_TIMEOUT 0x14

43

#define DSIM_CONFIG 0x18

43

#define DSIM_CONFIG 0x18

44

#define DSIM_ESCMODE 0x1c

44

#define DSIM_ESCMODE 0x1c

45

#define DSIM_MDRESOL 0x20

45

#define DSIM_MDRESOL 0x20

46

#define DSIM_MVPORCH 0x24

46

#define DSIM_MVPORCH 0x24

47

#define DSIM_MHPORCH 0x28

47

#define DSIM_MHPORCH 0x28

48

#define DSIM_MSYNC 0x2c

48

#define DSIM_MSYNC 0x2c

49

#define DSIM_SDRESOL 0x30

49

#define DSIM_SDRESOL 0x30

50

#define DSIM_INTSRC 0x34

50

#define DSIM_INTSRC 0x34

51

#define DSIM_INTMSK 0x38

51

#define DSIM_INTMSK 0x38

52

53

/* packet */

53

/* packet */

54

#define DSIM_PKTHDR 0x3c

54

#define DSIM_PKTHDR 0x3c

55

#define DSIM_PAYLOAD 0x40

55

#define DSIM_PAYLOAD 0x40

56

#define DSIM_RXFIFO 0x44

56

#define DSIM_RXFIFO 0x44

57

#define DSIM_FIFOTHLD 0x48

57

#define DSIM_FIFOTHLD 0x48

58

#define DSIM_FIFOCTRL 0x4c

58

#define DSIM_FIFOCTRL 0x4c

59

#define DSIM_MEMACCHR 0x50

59

#define DSIM_MEMACCHR 0x50

60

#define DSIM_MULTI_PKT 0x78

60

#define DSIM_MULTI_PKT 0x78

61

62

/* pll control */

62

/* pll control */

63

#define DSIM_PLLCTRL_1G 0x90

63

#define DSIM_PLLCTRL_1G 0x90

64

#define DSIM_PLLCTRL 0x94

64

#define DSIM_PLLCTRL 0x94

65

#define DSIM_PLLCTRL1 0x98

65

#define DSIM_PLLCTRL1 0x98

66

#define DSIM_PLLCTRL2 0x9c

66

#define DSIM_PLLCTRL2 0x9c

67

#define DSIM_PLLTMR 0xa0

67

#define DSIM_PLLTMR 0xa0

68

69

/* dphy */

69

/* dphy */

70

#define DSIM_PHYTIMING 0xb4

70

#define DSIM_PHYTIMING 0xb4

71

#define DSIM_PHYTIMING1 0xb8

71

#define DSIM_PHYTIMING1 0xb8

72

#define DSIM_PHYTIMING2 0xbc

72

#define DSIM_PHYTIMING2 0xbc

73

74

/* reg bit manipulation */

74

/* reg bit manipulation */

75

#define REG_MASK(e, s) (((1 << ((e) - (s) + 1)) - 1) << (s))

75

#define REG_MASK(e, s) (((1 << ((e) - (s) + 1)) - 1) << (s))

76

#define REG_PUT(x, e, s) (((x) << (s)) & REG_MASK(e, s))

76

#define REG_PUT(x, e, s) (((x) << (s)) & REG_MASK(e, s))

77

#define REG_GET(x, e, s) (((x) & REG_MASK(e, s)) >> (s))

77

#define REG_GET(x, e, s) (((x) & REG_MASK(e, s)) >> (s))

78

79

/* register bit fields */

79

/* register bit fields */

80

#define STATUS_PLLSTABLE BIT(31)

80

#define STATUS_PLLSTABLE BIT(31)

81

#define STATUS_SWRSTRLS BIT(20)

81

#define STATUS_SWRSTRLS BIT(20)

82

#define STATUS_TXREADYHSCLK BIT(10)

82

#define STATUS_TXREADYHSCLK BIT(10)

83

#define STATUS_ULPSCLK BIT(9)

83

#define STATUS_ULPSCLK BIT(9)

84

#define STATUS_STOPSTATECLK BIT(8)

84

#define STATUS_STOPSTATECLK BIT(8)

85

#define STATUS_GET_ULPSDAT(x) REG_GET(x, 7, 4)

85

#define STATUS_GET_ULPSDAT(x) REG_GET(x, 7, 4)

86

#define STATUS_GET_STOPSTATEDAT(x) REG_GET(x, 3, 0)

86

#define STATUS_GET_STOPSTATEDAT(x) REG_GET(x, 3, 0)

87

88

#define RGB_STATUS_CMDMODE_INSEL BIT(31)

88

#define RGB_STATUS_CMDMODE_INSEL BIT(31)

89

#define RGB_STATUS_GET_RGBSTATE(x) REG_GET(x, 12, 0)

89

#define RGB_STATUS_GET_RGBSTATE(x) REG_GET(x, 12, 0)

90

91

#define CLKCTRL_TXREQUESTHSCLK BIT(31)

91

#define CLKCTRL_TXREQUESTHSCLK BIT(31)

92

#define CLKCTRL_DPHY_SEL_1G BIT(29)

92

#define CLKCTRL_DPHY_SEL_1G BIT(29)

93

#define CLKCTRL_DPHY_SEL_1P5G (0x0 << 29)

93

#define CLKCTRL_DPHY_SEL_1P5G (0x0 << 29)

94

#define CLKCTRL_ESCCLKEN BIT(28)

94

#define CLKCTRL_ESCCLKEN BIT(28)

95

#define CLKCTRL_PLLBYPASS BIT(29)

95

#define CLKCTRL_PLLBYPASS BIT(29)

96

#define CLKCTRL_BYTECLKSRC_DPHY_PLL REG_PUT(0, 26, 25)

96

#define CLKCTRL_BYTECLKSRC_DPHY_PLL REG_PUT(0, 26, 25)

97

#define CLKCTRL_BYTECLKEN BIT(24)

97

#define CLKCTRL_BYTECLKEN BIT(24)

98

#define CLKCTRL_SET_LANEESCCLKEN(x) REG_PUT(x, 23, 19)

98

#define CLKCTRL_SET_LANEESCCLKEN(x) REG_PUT(x, 23, 19)

99

#define CLKCTRL_SET_ESCPRESCALER(x) REG_PUT(x, 15, 0)

99

#define CLKCTRL_SET_ESCPRESCALER(x) REG_PUT(x, 15, 0)

100

101

#define TIMEOUT_SET_BTAOUT(x) REG_PUT(x, 23, 16)

101

#define TIMEOUT_SET_BTAOUT(x) REG_PUT(x, 23, 16)

102

#define TIMEOUT_SET_LPDRTOUT(x) REG_PUT(x, 15, 0)

102

#define TIMEOUT_SET_LPDRTOUT(x) REG_PUT(x, 15, 0)

103

104

#define CONFIG_NON_CONTINUOUS_CLOCK_LANE BIT(31)

104

#define CONFIG_NON_CONTINUOUS_CLOCK_LANE BIT(31)

105

#define CONFIG_CLKLANE_STOP_START BIT(30)

105

#define CONFIG_CLKLANE_STOP_START BIT(30)

106

#define CONFIG_MFLUSH_VS BIT(29)

106

#define CONFIG_MFLUSH_VS BIT(29)

107

#define CONFIG_EOT_R03 BIT(28)

107

#define CONFIG_EOT_R03 BIT(28)

108

#define CONFIG_SYNCINFORM BIT(27)

108

#define CONFIG_SYNCINFORM BIT(27)

109

#define CONFIG_BURSTMODE BIT(26)

109

#define CONFIG_BURSTMODE BIT(26)

110

#define CONFIG_VIDEOMODE BIT(25)

110

#define CONFIG_VIDEOMODE BIT(25)

111

#define CONFIG_AUTOMODE BIT(24)

111

#define CONFIG_AUTOMODE BIT(24)

112

#define CONFIG_HSEDISABLEMODE BIT(23)

112

#define CONFIG_HSEDISABLEMODE BIT(23)

113

#define CONFIG_HFPDISABLEMODE BIT(22)

113

#define CONFIG_HFPDISABLEMODE BIT(22)

114

#define CONFIG_HBPDISABLEMODE BIT(21)

114

#define CONFIG_HBPDISABLEMODE BIT(21)

115

#define CONFIG_HSADISABLEMODE BIT(20)

115

#define CONFIG_HSADISABLEMODE BIT(20)

116

#define CONFIG_SET_MAINVC(x) REG_PUT(x, 19, 18)

116

#define CONFIG_SET_MAINVC(x) REG_PUT(x, 19, 18)

117

#define CONFIG_SET_SUBVC(x) REG_PUT(x, 17, 16)

117

#define CONFIG_SET_SUBVC(x) REG_PUT(x, 17, 16)

118

#define CONFIG_SET_MAINPIXFORMAT(x) REG_PUT(x, 14, 12)

118

#define CONFIG_SET_MAINPIXFORMAT(x) REG_PUT(x, 14, 12)

119

#define CONFIG_SET_SUBPIXFORMAT(x) REG_PUT(x, 10, 8)

119

#define CONFIG_SET_SUBPIXFORMAT(x) REG_PUT(x, 10, 8)

120

#define CONFIG_SET_NUMOFDATLANE(x) REG_PUT(x, 6, 5)

120

#define CONFIG_SET_NUMOFDATLANE(x) REG_PUT(x, 6, 5)

121

#define CONFIG_SET_LANEEN(x) REG_PUT(x, 4, 0)

121

#define CONFIG_SET_LANEEN(x) REG_PUT(x, 4, 0)

122

123

#define ESCMODE_SET_STOPSTATE_CNT(X) REG_PUT(x, 31, 21)

123

#define ESCMODE_SET_STOPSTATE_CNT(X) REG_PUT(x, 31, 21)

124

#define ESCMODE_FORCESTOPSTATE BIT(20)

124

#define ESCMODE_FORCESTOPSTATE BIT(20)

125

#define ESCMODE_FORCEBTA BIT(16)

125

#define ESCMODE_FORCEBTA BIT(16)

126

#define ESCMODE_CMDLPDT BIT(7)

126

#define ESCMODE_CMDLPDT BIT(7)

127

#define ESCMODE_TXLPDT BIT(6)

127

#define ESCMODE_TXLPDT BIT(6)

128

#define ESCMODE_TXTRIGGERRST BIT(5)

128

#define ESCMODE_TXTRIGGERRST BIT(5)

129

130

#define MDRESOL_MAINSTANDBY BIT(31)

130

#define MDRESOL_MAINSTANDBY BIT(31)

131

#define MDRESOL_SET_MAINVRESOL(x) REG_PUT(x, 27, 16)

131

#define MDRESOL_SET_MAINVRESOL(x) REG_PUT(x, 27, 16)

132

#define MDRESOL_SET_MAINHRESOL(x) REG_PUT(x, 11, 0)

132

#define MDRESOL_SET_MAINHRESOL(x) REG_PUT(x, 11, 0)

133

134

#define MVPORCH_SET_CMDALLOW(x) REG_PUT(x, 31, 28)

134

#define MVPORCH_SET_CMDALLOW(x) REG_PUT(x, 31, 28)

135

#define MVPORCH_SET_STABLEVFP(x) REG_PUT(x, 26, 16)

135

#define MVPORCH_SET_STABLEVFP(x) REG_PUT(x, 26, 16)

136

#define MVPORCH_SET_MAINVBP(x) REG_PUT(x, 10, 0)

136

#define MVPORCH_SET_MAINVBP(x) REG_PUT(x, 10, 0)

137

138

#define MHPORCH_SET_MAINHFP(x) REG_PUT(x, 31, 16)

138

#define MHPORCH_SET_MAINHFP(x) REG_PUT(x, 31, 16)

139

#define MHPORCH_SET_MAINHBP(x) REG_PUT(x, 15, 0)

139

#define MHPORCH_SET_MAINHBP(x) REG_PUT(x, 15, 0)

140

141

#define MSYNC_SET_MAINVSA(x) REG_PUT(x, 31, 22)

141

#define MSYNC_SET_MAINVSA(x) REG_PUT(x, 31, 22)

142

#define MSYNC_SET_MAINHSA(x) REG_PUT(x, 15, 0)

142

#define MSYNC_SET_MAINHSA(x) REG_PUT(x, 15, 0)

143

144

#define INTSRC_PLLSTABLE BIT(31)

144

#define INTSRC_PLLSTABLE BIT(31)

145

#define INTSRC_SWRSTRELEASE BIT(30)

145

#define INTSRC_SWRSTRELEASE BIT(30)

146

#define INTSRC_SFRPLFIFOEMPTY BIT(29)

146

#define INTSRC_SFRPLFIFOEMPTY BIT(29)

147

#define INTSRC_SFRPHFIFOEMPTY BIT(28)

147

#define INTSRC_SFRPHFIFOEMPTY BIT(28)

148

#define INTSRC_FRAMEDONE BIT(24)

148

#define INTSRC_FRAMEDONE BIT(24)

149

#define INTSRC_LPDRTOUT BIT(21)

149

#define INTSRC_LPDRTOUT BIT(21)

150

#define INTSRC_TATOUT BIT(20)

150

#define INTSRC_TATOUT BIT(20)

151

#define INTSRC_RXDATDONE BIT(18)

151

#define INTSRC_RXDATDONE BIT(18)

152

#define INTSRC_RXTE BIT(17)

152

#define INTSRC_RXTE BIT(17)

153

#define INTSRC_RXACK BIT(16)

153

#define INTSRC_RXACK BIT(16)

154

#define INTSRC_MASK (INTSRC_PLLSTABLE | \

154

#define INTSRC_MASK (INTSRC_PLLSTABLE | \

155

INTSRC_SWRSTRELEASE | \

155

INTSRC_SWRSTRELEASE | \

156

INTSRC_SFRPLFIFOEMPTY | \

156

INTSRC_SFRPLFIFOEMPTY | \

157

INTSRC_SFRPHFIFOEMPTY | \

157

INTSRC_SFRPHFIFOEMPTY | \

158

INTSRC_FRAMEDONE | \

158

INTSRC_FRAMEDONE | \

159

INTSRC_LPDRTOUT | \

159

INTSRC_LPDRTOUT | \

160

INTSRC_TATOUT | \

160

INTSRC_TATOUT | \

161

INTSRC_RXDATDONE | \

161

INTSRC_RXDATDONE | \

162

INTSRC_RXTE | \

162

INTSRC_RXTE | \

163

INTSRC_RXACK)

163

INTSRC_RXACK)

164

165

#define INTMSK_MSKPLLSTABLE BIT(31)

165

#define INTMSK_MSKPLLSTABLE BIT(31)

166

#define INTMSK_MSKSWRELEASE BIT(30)

166

#define INTMSK_MSKSWRELEASE BIT(30)

167

#define INTMSK_MSKSFRPLFIFOEMPTY BIT(29)

167

#define INTMSK_MSKSFRPLFIFOEMPTY BIT(29)

168

#define INTMSK_MSKSFRPHFIFOEMPTY BIT(28)

168

#define INTMSK_MSKSFRPHFIFOEMPTY BIT(28)

169

#define INTMSK_MSKFRAMEDONE BIT(24)

169

#define INTMSK_MSKFRAMEDONE BIT(24)

170

#define INTMSK_MSKLPDRTOUT BIT(21)

170

#define INTMSK_MSKLPDRTOUT BIT(21)

171

#define INTMSK_MSKTATOUT BIT(20)

171

#define INTMSK_MSKTATOUT BIT(20)

172

#define INTMSK_MSKRXDATDONE BIT(18)

172

#define INTMSK_MSKRXDATDONE BIT(18)

173

#define INTMSK_MSKRXTE BIT(17)

173

#define INTMSK_MSKRXTE BIT(17)

174

#define INTMSK_MSKRXACK BIT(16)

174

#define INTMSK_MSKRXACK BIT(16)

175

176

#define PKTHDR_SET_DATA1(x) REG_PUT(x, 23, 16)

176

#define PKTHDR_SET_DATA1(x) REG_PUT(x, 23, 16)

177

#define PKTHDR_GET_DATA1(x) REG_GET(x, 23, 16)

177

#define PKTHDR_GET_DATA1(x) REG_GET(x, 23, 16)

178

#define PKTHDR_SET_DATA0(x) REG_PUT(x, 15, 8)

178

#define PKTHDR_SET_DATA0(x) REG_PUT(x, 15, 8)

179

#define PKTHDR_GET_DATA0(x) REG_GET(x, 15, 8)

179

#define PKTHDR_GET_DATA0(x) REG_GET(x, 15, 8)

180

#define PKTHDR_GET_WC(x) REG_GET(x, 23, 8)

180

#define PKTHDR_GET_WC(x) REG_GET(x, 23, 8)

181

#define PKTHDR_SET_DI(x) REG_PUT(x, 7, 0)

181

#define PKTHDR_SET_DI(x) REG_PUT(x, 7, 0)

182

#define PKTHDR_GET_DI(x) REG_GET(x, 7, 0)

182

#define PKTHDR_GET_DI(x) REG_GET(x, 7, 0)

183

#define PKTHDR_SET_DT(x) REG_PUT(x, 5, 0)

183

#define PKTHDR_SET_DT(x) REG_PUT(x, 5, 0)

184

#define PKTHDR_GET_DT(x) REG_GET(x, 5, 0)

184

#define PKTHDR_GET_DT(x) REG_GET(x, 5, 0)

185

#define PKTHDR_SET_VC(x) REG_PUT(x, 7, 6)

185

#define PKTHDR_SET_VC(x) REG_PUT(x, 7, 6)

186

#define PKTHDR_GET_VC(x) REG_GET(x, 7, 6)

186

#define PKTHDR_GET_VC(x) REG_GET(x, 7, 6)

187

188

#define FIFOCTRL_FULLRX BIT(25)

188

#define FIFOCTRL_FULLRX BIT(25)

189

#define FIFOCTRL_EMPTYRX BIT(24)

189

#define FIFOCTRL_EMPTYRX BIT(24)

190

#define FIFOCTRL_FULLHSFR BIT(23)

190

#define FIFOCTRL_FULLHSFR BIT(23)

191

#define FIFOCTRL_EMPTYHSFR BIT(22)

191

#define FIFOCTRL_EMPTYHSFR BIT(22)

192

#define FIFOCTRL_FULLLSFR BIT(21)

192

#define FIFOCTRL_FULLLSFR BIT(21)

193

#define FIFOCTRL_EMPTYLSFR BIT(20)

193

#define FIFOCTRL_EMPTYLSFR BIT(20)

194

#define FIFOCTRL_FULLHMAIN BIT(11)

194

#define FIFOCTRL_FULLHMAIN BIT(11)

195

#define FIFOCTRL_EMPTYHMAIN BIT(10)

195

#define FIFOCTRL_EMPTYHMAIN BIT(10)

196

#define FIFOCTRL_FULLLMAIN BIT(9)

196

#define FIFOCTRL_FULLLMAIN BIT(9)

197

#define FIFOCTRL_EMPTYLMAIN BIT(8)

197

#define FIFOCTRL_EMPTYLMAIN BIT(8)

198

#define FIFOCTRL_NINITRX BIT(4)

198

#define FIFOCTRL_NINITRX BIT(4)

199

#define FIFOCTRL_NINITSFR BIT(3)

199

#define FIFOCTRL_NINITSFR BIT(3)

200

#define FIFOCTRL_NINITI80 BIT(2)

200

#define FIFOCTRL_NINITI80 BIT(2)

201

#define FIFOCTRL_NINITSUB BIT(1)

201

#define FIFOCTRL_NINITSUB BIT(1)

202

#define FIFOCTRL_NINITMAIN BIT(0)

202

#define FIFOCTRL_NINITMAIN BIT(0)

203

204

#define PLLCTRL_DPDNSWAP_CLK BIT(25)

204

#define PLLCTRL_DPDNSWAP_CLK BIT(25)

205

#define PLLCTRL_DPDNSWAP_DAT BIT(24)

205

#define PLLCTRL_DPDNSWAP_DAT BIT(24)

206

#define PLLCTRL_PLLEN BIT(23)

206

#define PLLCTRL_PLLEN BIT(23)

207

#define PLLCTRL_SET_PMS(x) REG_PUT(x, 19, 1)

207

#define PLLCTRL_SET_PMS(x) REG_PUT(x, 19, 1)

208

#define PLLCTRL_SET_P(x) REG_PUT(x, 18, 13)

208

#define PLLCTRL_SET_P(x) REG_PUT(x, 18, 13)

209

#define PLLCTRL_SET_M(x) REG_PUT(x, 12, 3)

209

#define PLLCTRL_SET_M(x) REG_PUT(x, 12, 3)

210

#define PLLCTRL_SET_S(x) REG_PUT(x, 2, 0)

210

#define PLLCTRL_SET_S(x) REG_PUT(x, 2, 0)

211

212

#define PHYTIMING_SET_M_TLPXCTL(x) REG_PUT(x, 15, 8)

212

#define PHYTIMING_SET_M_TLPXCTL(x) REG_PUT(x, 15, 8)

213

#define PHYTIMING_SET_M_THSEXITCTL(x) REG_PUT(x, 7, 0)

213

#define PHYTIMING_SET_M_THSEXITCTL(x) REG_PUT(x, 7, 0)

214

215

#define PHYTIMING1_SET_M_TCLKPRPRCTL(x) REG_PUT(x, 31, 24)

215

#define PHYTIMING1_SET_M_TCLKPRPRCTL(x) REG_PUT(x, 31, 24)

216

#define PHYTIMING1_SET_M_TCLKZEROCTL(x) REG_PUT(x, 23, 16)

216

#define PHYTIMING1_SET_M_TCLKZEROCTL(x) REG_PUT(x, 23, 16)

217

#define PHYTIMING1_SET_M_TCLKPOSTCTL(x) REG_PUT(x, 15, 8)

217

#define PHYTIMING1_SET_M_TCLKPOSTCTL(x) REG_PUT(x, 15, 8)

218

#define PHYTIMING1_SET_M_TCLKTRAILCTL(x) REG_PUT(x, 7, 0)

218

#define PHYTIMING1_SET_M_TCLKTRAILCTL(x) REG_PUT(x, 7, 0)

219

220

#define PHYTIMING2_SET_M_THSPRPRCTL(x) REG_PUT(x, 23, 16)

220

#define PHYTIMING2_SET_M_THSPRPRCTL(x) REG_PUT(x, 23, 16)

221

#define PHYTIMING2_SET_M_THSZEROCTL(x) REG_PUT(x, 15, 8)

221

#define PHYTIMING2_SET_M_THSZEROCTL(x) REG_PUT(x, 15, 8)

222

#define PHYTIMING2_SET_M_THSTRAILCTL(x) REG_PUT(x, 7, 0)

222

#define PHYTIMING2_SET_M_THSTRAILCTL(x) REG_PUT(x, 7, 0)

223

224

#define dsim_read(dsim, reg) readl(dsim->base + reg)

224

#define dsim_read(dsim, reg) readl(dsim->base + reg)

225

#define dsim_write(dsim, val, reg) writel(val, dsim->base + reg)

225

#define dsim_write(dsim, val, reg) writel(val, dsim->base + reg)

226

227

/* fixed phy ref clk rate */

227

/* fixed phy ref clk rate */

228

#define PHY_REF_CLK 27000000

228

#define PHY_REF_CLK 27000000

229

230

#define MAX_MAIN_HRESOL 2047

230

#define MAX_MAIN_HRESOL 2047

231

#define MAX_MAIN_VRESOL 2047

231

#define MAX_MAIN_VRESOL 2047

232

#define MAX_SUB_HRESOL 1024

232

#define MAX_SUB_HRESOL 1024

233

#define MAX_SUB_VRESOL 1024

233

#define MAX_SUB_VRESOL 1024

234

235

/* in KHZ */

235

/* in KHZ */

236

#define MAX_ESC_CLK_FREQ 20000

236

#define MAX_ESC_CLK_FREQ 20000

237

238

/* dsim all irqs index */

238

/* dsim all irqs index */

239

#define PLLSTABLE 1

239

#define PLLSTABLE 1

240

#define SWRSTRELEASE 2

240

#define SWRSTRELEASE 2

241

#define SFRPLFIFOEMPTY 3

241

#define SFRPLFIFOEMPTY 3

242

#define SFRPHFIFOEMPTY 4

242

#define SFRPHFIFOEMPTY 4

243

#define SYNCOVERRIDE 5

243

#define SYNCOVERRIDE 5

244

#define BUSTURNOVER 6

244

#define BUSTURNOVER 6

245

#define FRAMEDONE 7

245

#define FRAMEDONE 7

246

#define LPDRTOUT 8

246

#define LPDRTOUT 8

247

#define TATOUT 9

247

#define TATOUT 9

248

#define RXDATDONE 10

248

#define RXDATDONE 10

249

#define RXTE 11

249

#define RXTE 11

250

#define RXACK 12

250

#define RXACK 12

251

#define ERRRXECC 13

251

#define ERRRXECC 13

252

#define ERRRXCRC 14

252

#define ERRRXCRC 14

253

#define ERRESC3 15

253

#define ERRESC3 15

254

#define ERRESC2 16

254

#define ERRESC2 16

255

#define ERRESC1 17

255

#define ERRESC1 17

256

#define ERRESC0 18

256

#define ERRESC0 18

257

#define ERRSYNC3 19

257

#define ERRSYNC3 19

258

#define ERRSYNC2 20

258

#define ERRSYNC2 20

259

#define ERRSYNC1 21

259

#define ERRSYNC1 21

260

#define ERRSYNC0 22

260

#define ERRSYNC0 22

261

#define ERRCONTROL3 23

261

#define ERRCONTROL3 23

262

#define ERRCONTROL2 24

262

#define ERRCONTROL2 24

263

#define ERRCONTROL1 25

263

#define ERRCONTROL1 25

264

#define ERRCONTROL0 26

264

#define ERRCONTROL0 26

265

266

#define MIPI_FIFO_TIMEOUT msecs_to_jiffies(250)

266

#define MIPI_FIFO_TIMEOUT msecs_to_jiffies(250)

267

268

#define to_sec_mipi_dsim(dsi) container_of(dsi, struct sec_mipi_dsim, dsi_host)

268

#define to_sec_mipi_dsim(dsi) container_of(dsi, struct sec_mipi_dsim, dsi_host)

269

#define conn_to_sec_mipi_dsim(conn) \

269

#define conn_to_sec_mipi_dsim(conn) \

270

container_of(conn, struct sec_mipi_dsim, connector)

270

container_of(conn, struct sec_mipi_dsim, connector)

271

272

/* DSIM PLL configuration from spec:

272

/* DSIM PLL configuration from spec:

273

*

273

*

274

* Fout(DDR) = (M * Fin) / (P * 2^S), so Fout / Fin = M / (P * 2^S)

274

* Fout(DDR) = (M * Fin) / (P * 2^S), so Fout / Fin = M / (P * 2^S)

275

* Fin_pll = Fin / P (6 ~ 12 MHz)

275

* Fin_pll = Fin / P (6 ~ 12 MHz)

276

* S: [2:0], M: [12:3], P: [18:13], so

276

* S: [2:0], M: [12:3], P: [18:13], so

277

* TODO: 'S' is in [0 ~ 3], 'M' is in, 'P' is in [1 ~ 33]

277

* TODO: 'S' is in [0 ~ 3], 'M' is in, 'P' is in [1 ~ 33]

278

*

278

*

279

*/

279

*/

280

281

/* used for CEA standard modes */

281

/* used for CEA standard modes */

282

struct dsim_hblank_par {

282

struct dsim_hblank_par {

283

char *name; /* drm display mode name */

283

char *name; /* drm display mode name */

284

int vrefresh;

284

int vrefresh;

285

int hfp_wc;

285

int hfp_wc;

286

int hbp_wc;

286

int hbp_wc;

287

int hsa_wc;

287

int hsa_wc;

288

int lanes;

288

int lanes;

289

};

289

};

290

291

struct dsim_pll_pms {

291

struct dsim_pll_pms {

292

uint64_t bit_clk; /* kHz */

292

uint32_t bit_clk; /* kHz */

293

uint32_t p;

293

uint32_t p;

294

uint32_t m;

294

uint32_t m;

295

uint32_t s;

295

uint32_t s;

296

};

296

};

297

298

struct sec_mipi_dsim {

298

struct sec_mipi_dsim {

299

struct mipi_dsi_host dsi_host;

299

struct mipi_dsi_host dsi_host;

300

struct drm_connector connector;

300

struct drm_connector connector;

301

struct drm_encoder *encoder;

301

struct drm_encoder *encoder;

302

struct drm_bridge *bridge;

302

struct drm_bridge *bridge;

303

struct drm_bridge *next;

303

struct drm_bridge *next;

304

struct drm_panel *panel;

304

struct drm_panel *panel;

305

struct device *dev;

305

struct device *dev;

306

307

void __iomem *base;

307

void __iomem *base;

308

int irq;

308

int irq;

309

310

struct clk *clk_cfg;

310

struct clk *clk_cfg;

311

struct clk *clk_pllref;

311

struct clk *clk_pllref;

312

struct clk *pclk; /* pixel clock */

312

struct clk *pclk; /* pixel clock */

313

314

/* kHz clocks */

314

/* kHz clocks */

315

uint64_t pix_clk;

315

uint32_t pix_clk;

316

uint64_t bit_clk;

316

uint32_t bit_clk;

317

318

unsigned int lanes;

318

unsigned int lanes;

319

unsigned int channel; /* virtual channel */

319

unsigned int channel; /* virtual channel */

320

enum mipi_dsi_pixel_format format;

320

enum mipi_dsi_pixel_format format;

321

unsigned long mode_flags;

321

unsigned long mode_flags;

322

const struct dsim_hblank_par *hpar;

322

const struct dsim_hblank_par *hpar;

323

unsigned int pms;

323

unsigned int pms;

324

unsigned int p;

324

unsigned int p;

325

unsigned int m;

325

unsigned int m;

326

unsigned int s;

326

unsigned int s;

327

unsigned long long lp_data_rate;

327

unsigned long long lp_data_rate;

328

unsigned long long hs_data_rate;

328

unsigned long long hs_data_rate;

329

struct videomode vmode;

329

struct videomode vmode;

330

331

struct completion pll_stable;

331

struct completion pll_stable;

332

struct completion ph_tx_done;

332

struct completion ph_tx_done;

333

struct completion pl_tx_done;

333

struct completion pl_tx_done;

334

struct completion rx_done;

334

struct completion rx_done;

335

const struct sec_mipi_dsim_plat_data *pdata;

335

const struct sec_mipi_dsim_plat_data *pdata;

336

};

336

};

337

338

#define DSIM_HBLANK_PARAM(nm, vf, hfp, hbp, hsa, num) \

338

#define DSIM_HBLANK_PARAM(nm, vf, hfp, hbp, hsa, num) \

339

.name = (nm), \

339

.name = (nm), \

340

.vrefresh = (vf), \

340

.vrefresh = (vf), \

341

.hfp_wc = (hfp), \

341

.hfp_wc = (hfp), \

342

.hbp_wc = (hbp), \

342

.hbp_wc = (hbp), \

343

.hsa_wc = (hsa), \

343

.hsa_wc = (hsa), \

344

.lanes = (num)

344

.lanes = (num)

345

346

#define DSIM_PLL_PMS(c, pp, mm, ss) \

346

#define DSIM_PLL_PMS(c, pp, mm, ss) \

347

.bit_clk = (c), \

347

.bit_clk = (c), \

348

.p = (pp), \

348

.p = (pp), \

349

.m = (mm), \

349

.m = (mm), \

350

.s = (ss)

350

.s = (ss)

351

352

static const struct dsim_hblank_par hblank_4lanes[] = {

352

static const struct dsim_hblank_par hblank_4lanes[] = {

353

/* { 88, 148, 44 } */

353

/* { 88, 148, 44 } */

354

{ DSIM_HBLANK_PARAM("1920x1080", 60, 60, 105, 27, 4), },

354

{ DSIM_HBLANK_PARAM("1920x1080", 60, 60, 105, 27, 4), },

355

/* { 528, 148, 44 } */

355

/* { 528, 148, 44 } */

356

{ DSIM_HBLANK_PARAM("1920x1080", 50, 390, 105, 27, 4), },

356

{ DSIM_HBLANK_PARAM("1920x1080", 50, 390, 105, 27, 4), },

357

/* { 88, 148, 44 } */

357

/* { 88, 148, 44 } */

358

{ DSIM_HBLANK_PARAM("1920x1080", 30, 60, 105, 27, 4), },

358

{ DSIM_HBLANK_PARAM("1920x1080", 30, 60, 105, 27, 4), },

359

/* { 110, 220, 40 } */

359

/* { 110, 220, 40 } */

360

{ DSIM_HBLANK_PARAM("1280x720" , 60, 78, 159, 24, 4), },

360

{ DSIM_HBLANK_PARAM("1280x720" , 60, 78, 159, 24, 4), },

361

/* { 440, 220, 40 } */

361

/* { 440, 220, 40 } */

362

{ DSIM_HBLANK_PARAM("1280x720" , 50, 324, 159, 24, 4), },

362

{ DSIM_HBLANK_PARAM("1280x720" , 50, 324, 159, 24, 4), },

363

/* { 16, 60, 62 } */

363

/* { 16, 60, 62 } */

364

{ DSIM_HBLANK_PARAM("720x480" , 60, 6, 39, 40, 4), },

364

{ DSIM_HBLANK_PARAM("720x480" , 60, 6, 39, 40, 4), },

365

/* { 12, 68, 64 } */

365

/* { 12, 68, 64 } */

366

{ DSIM_HBLANK_PARAM("720x576" , 50, 3, 45, 42, 4), },

366

{ DSIM_HBLANK_PARAM("720x576" , 50, 3, 45, 42, 4), },

367

/* { 16, 48, 96 } */

367

/* { 16, 48, 96 } */

368

{ DSIM_HBLANK_PARAM("640x480" , 60, 6, 30, 66, 4), },

368

{ DSIM_HBLANK_PARAM("640x480" , 60, 6, 30, 66, 4), },

369

};

369

};

370

371

static const struct dsim_hblank_par hblank_2lanes[] = {

371

static const struct dsim_hblank_par hblank_2lanes[] = {

372

/* { 88, 148, 44 } */

372

/* { 88, 148, 44 } */

373

{ DSIM_HBLANK_PARAM("1920x1080", 30, 114, 210, 60, 2), },

373

{ DSIM_HBLANK_PARAM("1920x1080", 30, 114, 210, 60, 2), },

374

/* { 110, 220, 40 } */

374

/* { 110, 220, 40 } */

375

{ DSIM_HBLANK_PARAM("1280x720" , 60, 159, 320, 40, 2), },

375

{ DSIM_HBLANK_PARAM("1280x720" , 60, 159, 320, 40, 2), },

376

/* { 440, 220, 40 } */

376

/* { 440, 220, 40 } */

377

{ DSIM_HBLANK_PARAM("1280x720" , 50, 654, 320, 40, 2), },

377

{ DSIM_HBLANK_PARAM("1280x720" , 50, 654, 320, 40, 2), },

378

/* { 16, 60, 62 } */

378

/* { 16, 60, 62 } */

379

{ DSIM_HBLANK_PARAM("720x480" , 60, 16, 66, 88, 2), },

379

{ DSIM_HBLANK_PARAM("720x480" , 60, 16, 66, 88, 2), },

380

/* { 12, 68, 64 } */

380

/* { 12, 68, 64 } */

381

{ DSIM_HBLANK_PARAM("720x576" , 50, 12, 96, 72, 2), },

381

{ DSIM_HBLANK_PARAM("720x576" , 50, 12, 96, 72, 2), },

382

/* { 16, 48, 96 } */

382

/* { 16, 48, 96 } */

383

{ DSIM_HBLANK_PARAM("640x480" , 60, 18, 66, 138, 2), },

383

{ DSIM_HBLANK_PARAM("640x480" , 60, 18, 66, 138, 2), },

384

};

384

};

385

386

static const struct dsim_pll_pms pll_pms[] = {

386

static const struct dsim_pll_pms pll_pms[] = {

387

{ DSIM_PLL_PMS(891000, 1, 66, 1), },

387

{ DSIM_PLL_PMS(891000, 1, 66, 1), },

388

{ DSIM_PLL_PMS(890112, 1, 66, 1), },

388

{ DSIM_PLL_PMS(890112, 1, 66, 1), },

389

{ DSIM_PLL_PMS(594000, 3, 66, 0), },

389

{ DSIM_PLL_PMS(594000, 3, 66, 0), },

390

{ DSIM_PLL_PMS(593408, 3, 66, 0), },

390

{ DSIM_PLL_PMS(593408, 3, 66, 0), },

391

{ DSIM_PLL_PMS(445500, 1, 66, 2), },

391

{ DSIM_PLL_PMS(445500, 1, 66, 2), },

392

{ DSIM_PLL_PMS(445056, 1, 66, 2), },

392

{ DSIM_PLL_PMS(445056, 1, 66, 2), },

393

{ DSIM_PLL_PMS(324000, 3, 72, 1), },

393

{ DSIM_PLL_PMS(324000, 3, 72, 1), },

394

{ DSIM_PLL_PMS(324324, 3, 72, 1), },

394

{ DSIM_PLL_PMS(324324, 3, 72, 1), },

395

{ DSIM_PLL_PMS(162000, 3, 72, 2), },

395

{ DSIM_PLL_PMS(162000, 3, 72, 2), },

396

{ DSIM_PLL_PMS(162162, 3, 72, 2), },

396

{ DSIM_PLL_PMS(162162, 3, 72, 2), },

397

};

397

};

398

399

static const struct dsim_hblank_par *sec_mipi_dsim_get_hblank_par(const char *name,

399

static const struct dsim_hblank_par *sec_mipi_dsim_get_hblank_par(const char *name,

400

int vrefresh,

400

int vrefresh,

401

int lanes)

401

int lanes)

402

{

402

{

403

int i, size;

403

int i, size;

404

const struct dsim_hblank_par *hpar, *hblank;

404

const struct dsim_hblank_par *hpar, *hblank;

405

406

if (unlikely(!name))

406

if (unlikely(!name))

407

return NULL;

407

return NULL;

408

409

switch (lanes) {

409

switch (lanes) {

410

case 2:

410

case 2:

411

hblank = hblank_2lanes;

411

hblank = hblank_2lanes;

412

size = ARRAY_SIZE(hblank_2lanes);

412

size = ARRAY_SIZE(hblank_2lanes);

413

break;

413

break;

414

case 4:

414

case 4:

415

hblank = hblank_4lanes;

415

hblank = hblank_4lanes;

416

size = ARRAY_SIZE(hblank_4lanes);

416

size = ARRAY_SIZE(hblank_4lanes);

417

break;

417

break;

418

default:

418

default:

419

pr_err("No hblank data for mode %s with %d lanes\n",

419

pr_err("No hblank data for mode %s with %d lanes\n",

420

name, lanes);

420

name, lanes);

421

return NULL;

421

return NULL;

422

}

422

}

423

424

for (i = 0; i < size; i++) {

424

for (i = 0; i < size; i++) {

425

hpar = &hblank[i];

425

hpar = &hblank[i];

426

427

if (!strcmp(name, hpar->name)) {

427

if (!strcmp(name, hpar->name)) {

428

if (vrefresh != hpar->vrefresh)

428

if (vrefresh != hpar->vrefresh)

429

continue;

429

continue;

430

431

/* found */

431

/* found */

432

return hpar;

432

return hpar;

433

}

433

}

434

}

434

}

435

436

return NULL;

436

return NULL;

437

}

437

}

438

439

static const struct dsim_pll_pms *sec_mipi_dsim_get_pms(uint64_t bit_clk)

439

static const struct dsim_pll_pms *sec_mipi_dsim_get_pms(uint32_t bit_clk)

440

{

440

{

441

int i;

441

int i;

442

const struct dsim_pll_pms *pms;

442

const struct dsim_pll_pms *pms;

443

444

for (i = 0; i < ARRAY_SIZE(pll_pms); i++) {

444

for (i = 0; i < ARRAY_SIZE(pll_pms); i++) {

445

pms = &pll_pms[i];

445

pms = &pll_pms[i];

446

447

if (bit_clk == pms->bit_clk)

447

if (bit_clk == pms->bit_clk)

448

return pms;

448

return pms;

449

}

449

}

450

451

return NULL;

451

return NULL;

452

}

452

}

453

454

static void sec_mipi_dsim_irq_init(struct sec_mipi_dsim *dsim);

454

static void sec_mipi_dsim_irq_init(struct sec_mipi_dsim *dsim);

455

456

/* For now, dsim only support one device attached */

456

/* For now, dsim only support one device attached */

457

static int sec_mipi_dsim_host_attach(struct mipi_dsi_host *host,

457

static int sec_mipi_dsim_host_attach(struct mipi_dsi_host *host,

458

struct mipi_dsi_device *dsi)

458

struct mipi_dsi_device *dsi)

459

{

459

{

460

struct sec_mipi_dsim *dsim = to_sec_mipi_dsim(host);

460

struct sec_mipi_dsim *dsim = to_sec_mipi_dsim(host);

461

const struct sec_mipi_dsim_plat_data *pdata = dsim->pdata;

461

const struct sec_mipi_dsim_plat_data *pdata = dsim->pdata;

462

struct device *dev = dsim->dev;

462

struct device *dev = dsim->dev;

463

struct drm_panel *panel;

463

struct drm_panel *panel;

464

465

if (!dsi->lanes || dsi->lanes > pdata->max_data_lanes) {

465

if (!dsi->lanes || dsi->lanes > pdata->max_data_lanes) {

466

dev_err(dev, "invalid data lanes number\n");

466

dev_err(dev, "invalid data lanes number\n");

467

return -EINVAL;

467

return -EINVAL;

468

}

468

}

469

470

if (dsim->channel)

470

if (dsim->channel)

471

return -EINVAL;

471

return -EINVAL;

472

473

if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO) ||

473

if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO) ||

474

!((dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) ||

474

!((dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) ||

475

(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE))) {

475

(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE))) {

476

dev_err(dev, "unsupported dsi mode\n");

476

dev_err(dev, "unsupported dsi mode\n");

477

return -EINVAL;

477

return -EINVAL;

478

}

478

}

479

480

if (dsi->format != MIPI_DSI_FMT_RGB888 &&

480

if (dsi->format != MIPI_DSI_FMT_RGB888 &&

481

dsi->format != MIPI_DSI_FMT_RGB565 &&

481

dsi->format != MIPI_DSI_FMT_RGB565 &&

482

dsi->format != MIPI_DSI_FMT_RGB666 &&

482

dsi->format != MIPI_DSI_FMT_RGB666 &&

483

dsi->format != MIPI_DSI_FMT_RGB666_PACKED) {

483

dsi->format != MIPI_DSI_FMT_RGB666_PACKED) {

484

dev_err(dev, "unsupported pixel format: %#x\n", dsi->format);

484

dev_err(dev, "unsupported pixel format: %#x\n", dsi->format);

485

return -EINVAL;

485

return -EINVAL;

486

}

486

}

487

488

if (!dsim->next) {

488

if (!dsim->next) {

489

/* 'dsi' must be panel device */

489

/* 'dsi' must be panel device */

490

panel = of_drm_find_panel(dsi->dev.of_node);

490

panel = of_drm_find_panel(dsi->dev.of_node);

491

492

if (!panel) {

492

if (!panel) {

493

dev_err(dev, "refuse unknown dsi device attach\n");

493

dev_err(dev, "refuse unknown dsi device attach\n");

494

WARN_ON(!panel);

494

WARN_ON(!panel);

495

return -ENODEV;

495

return -ENODEV;

496

}

496

}

497

498

/* Don't support multiple panels */

498

/* Don't support multiple panels */

499

if (dsim->panel && panel && dsim->panel != panel) {

499

if (dsim->panel && panel && dsim->panel != panel) {

500

dev_err(dev, "don't support multiple panels\n");

500

dev_err(dev, "don't support multiple panels\n");

501

return -EBUSY;

501

return -EBUSY;

502

}

502

}

503

504

dsim->panel = panel;

504

dsim->panel = panel;

505

}

505

}

506

507

/* TODO: DSIM 3 lanes has some display issue, so

507

/* TODO: DSIM 3 lanes has some display issue, so

508

* avoid 3 lanes enable, and force data lanes to

508

* avoid 3 lanes enable, and force data lanes to

509

* be 2.

509

* be 2.

510

*/

510

*/

511

if (dsi->lanes == 3)

511

if (dsi->lanes == 3)

512

dsi->lanes = 2;

512

dsi->lanes = 2;

513

514

dsim->lanes = dsi->lanes;

514

dsim->lanes = dsi->lanes;

515

dsim->channel = dsi->channel;

515

dsim->channel = dsi->channel;

516

dsim->format = dsi->format;

516

dsim->format = dsi->format;

517

dsim->mode_flags = dsi->mode_flags;

517

dsim->mode_flags = dsi->mode_flags;

518

519

/* TODO: support later */

519

/* TODO: support later */

520

#if 0

520

#if 0

521

if (dsim->connector.dev)

521

if (dsim->connector.dev)

522

drm_helper_hpd_irq_event(dsim->connector.dev);

522

drm_helper_hpd_irq_event(dsim->connector.dev);

523

#endif

523

#endif

524

525

return 0;

525

return 0;

526

}

526

}

527

528

static int sec_mipi_dsim_host_detach(struct mipi_dsi_host *host,

528

static int sec_mipi_dsim_host_detach(struct mipi_dsi_host *host,

529

struct mipi_dsi_device *dsi)

529

struct mipi_dsi_device *dsi)

530

{

530

{

531

struct sec_mipi_dsim *dsim = to_sec_mipi_dsim(host);

531

struct sec_mipi_dsim *dsim = to_sec_mipi_dsim(host);

532

533

if (WARN_ON(!dsim->next && !dsim->panel))

533

if (WARN_ON(!dsim->next && !dsim->panel))

534

return -ENODEV;

534

return -ENODEV;

535

536

/* clear the saved dsi parameters */

536

/* clear the saved dsi parameters */

537

dsim->lanes = 0;

537

dsim->lanes = 0;

538

dsim->channel = 0;

538

dsim->channel = 0;

539

dsim->format = 0;

539

dsim->format = 0;

540

dsim->mode_flags = 0;

540

dsim->mode_flags = 0;

541

542

return 0;

542

return 0;

543

}

543

}

544

545

static void sec_mipi_dsim_config_cmd_lpm(struct sec_mipi_dsim *dsim,

545

static void sec_mipi_dsim_config_cmd_lpm(struct sec_mipi_dsim *dsim,

546

bool enable)

546

bool enable)

547

{

547

{

548

uint32_t escmode;

548

uint32_t escmode;

549

550

escmode = dsim_read(dsim, DSIM_ESCMODE);

550

escmode = dsim_read(dsim, DSIM_ESCMODE);

551

552

if (enable)

552

if (enable)

553

escmode |= ESCMODE_CMDLPDT;

553

escmode |= ESCMODE_CMDLPDT;

554

else

554

else

555

escmode &= ~ESCMODE_CMDLPDT;

555

escmode &= ~ESCMODE_CMDLPDT;

556

557

dsim_write(dsim, escmode, DSIM_ESCMODE);

557

dsim_write(dsim, escmode, DSIM_ESCMODE);

558

}

558

}

559

560

static void sec_mipi_dsim_write_pl_to_sfr_fifo(struct sec_mipi_dsim *dsim,

560

static void sec_mipi_dsim_write_pl_to_sfr_fifo(struct sec_mipi_dsim *dsim,

561

const void *payload,

561

const void *payload,

562

size_t length)

562

size_t length)

563

{

563

{

564

uint32_t pl_data;

564

uint32_t pl_data;

565

566

if (!length)

566

if (!length)

567

return;

567

return;

568

569

while (length >= 4) {

569

while (length >= 4) {

570

pl_data = get_unaligned_le32(payload);

570

pl_data = get_unaligned_le32(payload);

571

dsim_write(dsim, pl_data, DSIM_PAYLOAD);

571

dsim_write(dsim, pl_data, DSIM_PAYLOAD);

572

payload += 4;

572

payload += 4;

573

length -= 4;

573

length -= 4;

574

}

574

}

575

576

pl_data = 0;

576

pl_data = 0;

577

switch (length) {

577

switch (length) {

578

case 3:

578

case 3:

579

pl_data |= ((u8 *)payload)[2] << 16;

579

pl_data |= ((u8 *)payload)[2] << 16;

580

case 2:

580

case 2:

581

pl_data |= ((u8 *)payload)[1] << 8;

581

pl_data |= ((u8 *)payload)[1] << 8;

582

case 1:

582

case 1:

583

pl_data |= ((u8 *)payload)[0];

583

pl_data |= ((u8 *)payload)[0];

584

dsim_write(dsim, pl_data, DSIM_PAYLOAD);

584

dsim_write(dsim, pl_data, DSIM_PAYLOAD);

585

break;

585

break;

586

}

586

}

587

}

587

}

588

589

static void sec_mipi_dsim_write_ph_to_sfr_fifo(struct sec_mipi_dsim *dsim,

589

static void sec_mipi_dsim_write_ph_to_sfr_fifo(struct sec_mipi_dsim *dsim,

590

void *header,

590

void *header,

591

bool use_lpm)

591

bool use_lpm)

592

{

592

{

593

uint32_t pkthdr;

593

uint32_t pkthdr;

594

595

pkthdr = PKTHDR_SET_DATA1(((u8 *)header)[2]) | /* WC MSB */

595

pkthdr = PKTHDR_SET_DATA1(((u8 *)header)[2]) | /* WC MSB */

596

PKTHDR_SET_DATA0(((u8 *)header)[1]) | /* WC LSB */

596

PKTHDR_SET_DATA0(((u8 *)header)[1]) | /* WC LSB */

597

PKTHDR_SET_DI(((u8 *)header)[0]); /* Data ID */

597

PKTHDR_SET_DI(((u8 *)header)[0]); /* Data ID */

598

599

dsim_write(dsim, pkthdr, DSIM_PKTHDR);

599

dsim_write(dsim, pkthdr, DSIM_PKTHDR);

600

}

600

}

601

602

static int sec_mipi_dsim_read_pl_from_sfr_fifo(struct sec_mipi_dsim *dsim,

602

static int sec_mipi_dsim_read_pl_from_sfr_fifo(struct sec_mipi_dsim *dsim,

603

void *payload,

603

void *payload,

604

size_t length)

604

size_t length)

605

{

605

{

606

uint8_t data_type;

606

uint8_t data_type;

607

uint16_t word_count = 0;

607

uint16_t word_count = 0;

608

uint32_t fifoctrl, ph, pl;

608

uint32_t fifoctrl, ph, pl;

609

610

fifoctrl = dsim_read(dsim, DSIM_FIFOCTRL);

610

fifoctrl = dsim_read(dsim, DSIM_FIFOCTRL);

611

612

if (WARN_ON(fifoctrl & FIFOCTRL_EMPTYRX))

612

if (WARN_ON(fifoctrl & FIFOCTRL_EMPTYRX))

613

return -EINVAL;

613

return -EINVAL;

614

615

ph = dsim_read(dsim, DSIM_RXFIFO);

615

ph = dsim_read(dsim, DSIM_RXFIFO);

616

data_type = PKTHDR_GET_DT(ph);

616

data_type = PKTHDR_GET_DT(ph);

617

switch (data_type) {

617

switch (data_type) {

618

case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:

618

case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:

619

dev_err(dsim->dev, "peripheral report error: (0-7)%x, (8-15)%x\n",

619

dev_err(dsim->dev, "peripheral report error: (0-7)%x, (8-15)%x\n",

620

PKTHDR_GET_DATA0(ph), PKTHDR_GET_DATA1(ph));

620

PKTHDR_GET_DATA0(ph), PKTHDR_GET_DATA1(ph));

621

return -EPROTO;

621

return -EPROTO;

622

case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:

622

case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:

623

case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:

623

case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:

624

if (!WARN_ON(length < 2)) {

624

if (!WARN_ON(length < 2)) {

625

((u8 *)payload)[1] = PKTHDR_GET_DATA1(ph);

625

((u8 *)payload)[1] = PKTHDR_GET_DATA1(ph);

626

word_count++;

626

word_count++;

627

}

627

}

628

/* fall through */

628

/* fall through */

629

case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:

629

case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:

630

case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:

630

case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:

631

((u8 *)payload)[0] = PKTHDR_GET_DATA0(ph);

631

((u8 *)payload)[0] = PKTHDR_GET_DATA0(ph);

632

word_count++;

632

word_count++;

633

length = word_count;

633

length = word_count;

634

break;

634

break;

635

case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:

635

case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:

636

case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:

636

case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:

637

word_count = PKTHDR_GET_WC(ph);

637

word_count = PKTHDR_GET_WC(ph);

638

if (word_count > length) {

638

if (word_count > length) {

639

dev_err(dsim->dev, "invalid receive buffer length\n");

639

dev_err(dsim->dev, "invalid receive buffer length\n");

640

return -EINVAL;

640

return -EINVAL;

641

}

641

}

642

643

length = word_count;

643

length = word_count;

644

645

while (word_count >= 4) {

645

while (word_count >= 4) {

646

pl = dsim_read(dsim, DSIM_RXFIFO);

646

pl = dsim_read(dsim, DSIM_RXFIFO);

647

((u8 *)payload)[0] = pl & 0xff;

647

((u8 *)payload)[0] = pl & 0xff;

648

((u8 *)payload)[1] = (pl >> 8) & 0xff;

648

((u8 *)payload)[1] = (pl >> 8) & 0xff;

649

((u8 *)payload)[2] = (pl >> 16) & 0xff;

649

((u8 *)payload)[2] = (pl >> 16) & 0xff;

650

((u8 *)payload)[3] = (pl >> 24) & 0xff;

650

((u8 *)payload)[3] = (pl >> 24) & 0xff;

651

payload += 4;

651

payload += 4;

652

word_count -= 4;

652

word_count -= 4;

653

}

653

}

654

655

if (word_count > 0) {

655

if (word_count > 0) {

656

pl = dsim_read(dsim, DSIM_RXFIFO);

656

pl = dsim_read(dsim, DSIM_RXFIFO);

657

658

switch (word_count) {

658

switch (word_count) {

659

case 3:

659

case 3:

660

((u8 *)payload)[2] = (pl >> 16) & 0xff;

660

((u8 *)payload)[2] = (pl >> 16) & 0xff;

661

case 2:

661

case 2:

662

((u8 *)payload)[1] = (pl >> 8) & 0xff;

662

((u8 *)payload)[1] = (pl >> 8) & 0xff;

663

case 1:

663

case 1:

664

((u8 *)payload)[0] = pl & 0xff;

664

((u8 *)payload)[0] = pl & 0xff;

665

break;

665

break;

666

}

666

}

667

}

667

}

668

669

break;

669

break;

670

default:

670

default:

671

return -EINVAL;

671

return -EINVAL;

672

}

672

}

673

674

return length;

674

return length;

675

}

675

}

676

677

static ssize_t sec_mipi_dsim_host_transfer(struct mipi_dsi_host *host,

677

static ssize_t sec_mipi_dsim_host_transfer(struct mipi_dsi_host *host,

678

const struct mipi_dsi_msg *msg)

678

const struct mipi_dsi_msg *msg)

679

{

679

{

680

int ret;

680

int ret;

681

bool use_lpm;

681

bool use_lpm;

682

struct mipi_dsi_packet packet;

682

struct mipi_dsi_packet packet;

683

struct sec_mipi_dsim *dsim = to_sec_mipi_dsim(host);

683

struct sec_mipi_dsim *dsim = to_sec_mipi_dsim(host);

684

685

if ((msg->rx_buf && !msg->rx_len) || (msg->rx_len && !msg->rx_buf))

685

if ((msg->rx_buf && !msg->rx_len) || (msg->rx_len && !msg->rx_buf))

686

return -EINVAL;

686

return -EINVAL;

687

688

ret = mipi_dsi_create_packet(&packet, msg);

688

ret = mipi_dsi_create_packet(&packet, msg);

689

if (ret) {

689

if (ret) {

690

dev_err(dsim->dev, "failed to create dsi packet: %d\n", ret);

690

dev_err(dsim->dev, "failed to create dsi packet: %d\n", ret);

691

return ret;

691

return ret;

692

}

692

}

693

694

/* need to read data from peripheral */

694

/* need to read data from peripheral */

695

if (unlikely(msg->rx_buf))

695

if (unlikely(msg->rx_buf))

696

reinit_completion(&dsim->rx_done);

696

reinit_completion(&dsim->rx_done);

697

698

/* config LPM for CMD TX */

698

/* config LPM for CMD TX */

699

use_lpm = msg->flags & MIPI_DSI_MSG_USE_LPM ? true : false;

699

use_lpm = msg->flags & MIPI_DSI_MSG_USE_LPM ? true : false;

700

sec_mipi_dsim_config_cmd_lpm(dsim, use_lpm);

700

sec_mipi_dsim_config_cmd_lpm(dsim, use_lpm);

701

702

if (packet.payload_length) { /* Long Packet case */

702

if (packet.payload_length) { /* Long Packet case */

703

reinit_completion(&dsim->pl_tx_done);

703

reinit_completion(&dsim->pl_tx_done);

704

705

/* write packet payload */

705

/* write packet payload */

706

sec_mipi_dsim_write_pl_to_sfr_fifo(dsim,

706

sec_mipi_dsim_write_pl_to_sfr_fifo(dsim,

707

packet.payload,

707

packet.payload,

708

packet.payload_length);

708

packet.payload_length);

709

710

/* write packet header */

710

/* write packet header */

711

sec_mipi_dsim_write_ph_to_sfr_fifo(dsim,

711

sec_mipi_dsim_write_ph_to_sfr_fifo(dsim,

712

packet.header,

712

packet.header,

713

use_lpm);

713

use_lpm);

714

715

ret = wait_for_completion_timeout(&dsim->ph_tx_done,

715

ret = wait_for_completion_timeout(&dsim->ph_tx_done,

716

MIPI_FIFO_TIMEOUT);

716

MIPI_FIFO_TIMEOUT);

717

if (!ret) {

717

if (!ret) {

718

dev_err(dsim->dev, "wait payload tx done time out\n");

718

dev_err(dsim->dev, "wait payload tx done time out\n");

719

return -EBUSY;

719

return -EBUSY;

720

}

720

}

721

} else {

721

} else {

722

reinit_completion(&dsim->ph_tx_done);

722

reinit_completion(&dsim->ph_tx_done);

723

724

/* write packet header */

724

/* write packet header */

725

sec_mipi_dsim_write_ph_to_sfr_fifo(dsim,

725

sec_mipi_dsim_write_ph_to_sfr_fifo(dsim,

726

packet.header,

726

packet.header,

727

use_lpm);

727

use_lpm);

728

729

ret = wait_for_completion_timeout(&dsim->ph_tx_done,

729

ret = wait_for_completion_timeout(&dsim->ph_tx_done,

730

MIPI_FIFO_TIMEOUT);

730

MIPI_FIFO_TIMEOUT);

731

if (!ret) {

731

if (!ret) {

732

dev_err(dsim->dev, "wait pkthdr tx done time out\n");

732

dev_err(dsim->dev, "wait pkthdr tx done time out\n");

733

return -EBUSY;

733

return -EBUSY;

734

}

734

}

735

}

735

}

736

737

/* read packet payload */

737

/* read packet payload */

738

if (unlikely(msg->rx_buf)) {

738

if (unlikely(msg->rx_buf)) {

739

ret = wait_for_completion_timeout(&dsim->rx_done,

739

ret = wait_for_completion_timeout(&dsim->rx_done,

740

MIPI_FIFO_TIMEOUT);

740

MIPI_FIFO_TIMEOUT);

741

if (!ret) {

741

if (!ret) {

742

dev_err(dsim->dev, "wait rx done time out\n");

742

dev_err(dsim->dev, "wait rx done time out\n");

743

return -EBUSY;

743

return -EBUSY;

744

}

744

}

745

746

ret = sec_mipi_dsim_read_pl_from_sfr_fifo(dsim,

746

ret = sec_mipi_dsim_read_pl_from_sfr_fifo(dsim,

747

msg->rx_buf,

747

msg->rx_buf,

748

msg->rx_len);

748

msg->rx_len);

749

if (ret < 0)

749

if (ret < 0)

750

return ret;

750

return ret;

751

}

751

}

752

753

return 0;

753

return 0;

754

}

754

}

755

756

static const struct mipi_dsi_host_ops sec_mipi_dsim_host_ops = {

756

static const struct mipi_dsi_host_ops sec_mipi_dsim_host_ops = {

757

.attach = sec_mipi_dsim_host_attach,

757

.attach = sec_mipi_dsim_host_attach,

758

.detach = sec_mipi_dsim_host_detach,

758

.detach = sec_mipi_dsim_host_detach,

759

.transfer = sec_mipi_dsim_host_transfer,

759

.transfer = sec_mipi_dsim_host_transfer,

760

};

760

};

761

762

static int sec_mipi_dsim_bridge_attach(struct drm_bridge *bridge)

762

static int sec_mipi_dsim_bridge_attach(struct drm_bridge *bridge)

763

{

763

{

764

int ret;

764

int ret;

765

struct sec_mipi_dsim *dsim = bridge->driver_private;

765

struct sec_mipi_dsim *dsim = bridge->driver_private;

766

struct device *dev = dsim->dev;

766

struct device *dev = dsim->dev;

767

struct device_node *np = dev->of_node;

767

struct device_node *np = dev->of_node;

768

struct device_node *endpoint, *remote;

768

struct device_node *endpoint, *remote;

769

struct drm_bridge *next = NULL;

769

struct drm_bridge *next = NULL;

770

struct drm_encoder *encoder = dsim->encoder;

770

struct drm_encoder *encoder = dsim->encoder;

771

772

/* TODO: All bridges and planes should have already been added */

772

/* TODO: All bridges and planes should have already been added */

773

774

/* A panel has been found, ignor other dsi devices */

774

/* A panel has been found, ignor other dsi devices */

775

if (dsim->panel)

775

if (dsim->panel)

776

return 0;

776

return 0;

777

778

/* find next bridge */

778

/* find next bridge */

779

endpoint = of_graph_get_next_endpoint(np, NULL);

779

endpoint = of_graph_get_next_endpoint(np, NULL);

780

/* At least one endpoint should be existed */

780

/* At least one endpoint should be existed */

781

if (!endpoint)

781

if (!endpoint)

782

return -ENODEV;

782

return -ENODEV;

783

784

while(endpoint && !next) {

784

while(endpoint && !next) {

785

remote = of_graph_get_remote_port_parent(endpoint);

785

remote = of_graph_get_remote_port_parent(endpoint);

786

787

if (!remote || !of_device_is_available(remote)) {

787

if (!remote || !of_device_is_available(remote)) {

788

of_node_put(remote);

788

of_node_put(remote);

789

endpoint = of_graph_get_next_endpoint(np, endpoint);

789

endpoint = of_graph_get_next_endpoint(np, endpoint);

790

continue;

790

continue;

791

}

791

}

792

793

next = of_drm_find_bridge(remote);

793

next = of_drm_find_bridge(remote);

794

if (next) {

794

if (next) {

795

/* Found */

795

/* Found */

796

of_node_put(endpoint);

796

of_node_put(endpoint);

797

break;

797

break;

798

}

798

}

799

800

endpoint = of_graph_get_next_endpoint(np, endpoint);

800

endpoint = of_graph_get_next_endpoint(np, endpoint);

801

}

801

}

802

803

/* No valid dsi device attached */

803

/* No valid dsi device attached */

804

if (!next)

804

if (!next)

805

return -ENODEV;

805

return -ENODEV;

806

807

/* duplicate bridges or next bridge exists */

807

/* duplicate bridges or next bridge exists */

808

WARN_ON(bridge == next || bridge->next || dsim->next);

808

WARN_ON(bridge == next || bridge->next || dsim->next);

809

810

dsim->next = next;

810

dsim->next = next;

811

next->encoder = encoder;

811

next->encoder = encoder;

812

ret = drm_bridge_attach(encoder, next, bridge);

812

ret = drm_bridge_attach(encoder, next, bridge);

813

if (ret) {

813

if (ret) {

814

dev_err(dev, "Unable to attach bridge %s: %d\n",

814

dev_err(dev, "Unable to attach bridge %s: %d\n",

815

remote->name, ret);

815

remote->name, ret);

816

dsim->next = NULL;

816

dsim->next = NULL;

817

return ret;

817

return ret;

818

}

818

}

819

820

/* bridge chains */

820

/* bridge chains */

821

bridge->next = next;

821

bridge->next = next;

822

823

return 0;

823

return 0;

824

}

824

}

825

826

static int sec_mipi_dsim_config_pll(struct sec_mipi_dsim *dsim)

826

static int sec_mipi_dsim_config_pll(struct sec_mipi_dsim *dsim)

827

{

827

{

828

int ret;

828

int ret;

829

uint32_t pllctrl = 0, status, data_lanes_en, stop;

829

uint32_t pllctrl = 0, status, data_lanes_en, stop;

830

831

dsim_write(dsim, 0x8000, DSIM_PLLTMR);

831

dsim_write(dsim, 0x8000, DSIM_PLLTMR);

832

833

/* TODO: config dp/dn swap if requires */

833

/* TODO: config dp/dn swap if requires */

834

835

pllctrl |= PLLCTRL_SET_PMS(dsim->pms) | PLLCTRL_PLLEN;

835

pllctrl |= PLLCTRL_SET_PMS(dsim->pms) | PLLCTRL_PLLEN;

836

dsim_write(dsim, pllctrl, DSIM_PLLCTRL);

836

dsim_write(dsim, pllctrl, DSIM_PLLCTRL);

837

838

ret = wait_for_completion_timeout(&dsim->pll_stable, HZ / 10);

838

ret = wait_for_completion_timeout(&dsim->pll_stable, HZ / 10);

839

if (!ret) {

839

if (!ret) {

840

dev_err(dsim->dev, "wait for pll stable time out\n");

840

dev_err(dsim->dev, "wait for pll stable time out\n");

841

return -EBUSY;

841

return -EBUSY;

842

}

842

}

843

844

/* wait for clk & data lanes to go to stop state */

844

/* wait for clk & data lanes to go to stop state */

845

mdelay(1);

845

mdelay(1);

846

847

data_lanes_en = (0x1 << dsim->lanes) - 1;

847

data_lanes_en = (0x1 << dsim->lanes) - 1;

848

status = dsim_read(dsim, DSIM_STATUS);

848

status = dsim_read(dsim, DSIM_STATUS);

849

if (!(status & STATUS_STOPSTATECLK)) {

849

if (!(status & STATUS_STOPSTATECLK)) {

850

dev_err(dsim->dev, "clock is not in stop state\n");

850

dev_err(dsim->dev, "clock is not in stop state\n");

851

return -EBUSY;

851

return -EBUSY;

852

}

852

}

853

854

stop = STATUS_GET_STOPSTATEDAT(status);

854

stop = STATUS_GET_STOPSTATEDAT(status);

855

if ((stop & data_lanes_en) != data_lanes_en) {

855

if ((stop & data_lanes_en) != data_lanes_en) {

856

dev_err(dsim->dev,

856

dev_err(dsim->dev,

857

"one or more data lanes is not in stop state\n");

857

"one or more data lanes is not in stop state\n");

858

return -EBUSY;

858

return -EBUSY;

859

}

859

}

860

861

return 0;

861

return 0;

862

}

862

}

863

864

static void sec_mipi_dsim_set_main_mode(struct sec_mipi_dsim *dsim)

864

static void sec_mipi_dsim_set_main_mode(struct sec_mipi_dsim *dsim)

865

{

865

{

866

uint32_t bpp, hfp_wc, hbp_wc, hsa_wc;

866

uint32_t bpp, hfp_wc, hbp_wc, hsa_wc;

867

uint32_t mdresol = 0, mvporch = 0, mhporch = 0, msync = 0;

867

uint32_t mdresol = 0, mvporch = 0, mhporch = 0, msync = 0;

868

struct videomode *vmode = &dsim->vmode;

868

struct videomode *vmode = &dsim->vmode;

869

870

mdresol |= MDRESOL_SET_MAINVRESOL(vmode->vactive) |

870

mdresol |= MDRESOL_SET_MAINVRESOL(vmode->vactive) |

871

MDRESOL_SET_MAINHRESOL(vmode->hactive);

871

MDRESOL_SET_MAINHRESOL(vmode->hactive);

872

dsim_write(dsim, mdresol, DSIM_MDRESOL);

872

dsim_write(dsim, mdresol, DSIM_MDRESOL);

873

874

mvporch |= MVPORCH_SET_MAINVBP(vmode->vback_porch) |

874

mvporch |= MVPORCH_SET_MAINVBP(vmode->vback_porch) |

875

MVPORCH_SET_STABLEVFP(vmode->vfront_porch) |

875

MVPORCH_SET_STABLEVFP(vmode->vfront_porch) |

876

MVPORCH_SET_CMDALLOW(0x0);

876

MVPORCH_SET_CMDALLOW(0x0);

877

dsim_write(dsim, mvporch, DSIM_MVPORCH);

877

dsim_write(dsim, mvporch, DSIM_MVPORCH);

878

879

bpp = mipi_dsi_pixel_format_to_bpp(dsim->format);

879

bpp = mipi_dsi_pixel_format_to_bpp(dsim->format);

880

881

/* calculate hfp & hbp word counts */

881

/* calculate hfp & hbp word counts */

882

if (dsim->panel || !dsim->hpar) {

882

if (dsim->panel || !dsim->hpar) {

883

hfp_wc = vmode->hfront_porch * (bpp >> 3);

883

hfp_wc = vmode->hfront_porch * (bpp >> 3);

884

hbp_wc = vmode->hback_porch * (bpp >> 3);

884

hbp_wc = vmode->hback_porch * (bpp >> 3);

885

} else {

885

} else {

886

hfp_wc = dsim->hpar->hfp_wc;

886

hfp_wc = dsim->hpar->hfp_wc;

887

hbp_wc = dsim->hpar->hbp_wc;

887

hbp_wc = dsim->hpar->hbp_wc;

888

}

888

}

889

890

mhporch |= MHPORCH_SET_MAINHFP(hfp_wc) |

890

mhporch |= MHPORCH_SET_MAINHFP(hfp_wc) |

891

MHPORCH_SET_MAINHBP(hbp_wc);

891

MHPORCH_SET_MAINHBP(hbp_wc);

892

893

dsim_write(dsim, mhporch, DSIM_MHPORCH);

893

dsim_write(dsim, mhporch, DSIM_MHPORCH);

894

895

/* calculate hsa word counts */

895

/* calculate hsa word counts */

896

if (dsim->panel || !dsim->hpar)

896

if (dsim->panel || !dsim->hpar)

897

hsa_wc = vmode->hsync_len * (bpp >> 3);

897

hsa_wc = vmode->hsync_len * (bpp >> 3);

898

else

898

else

899

hsa_wc = dsim->hpar->hsa_wc;

899

hsa_wc = dsim->hpar->hsa_wc;

900

901

msync |= MSYNC_SET_MAINVSA(vmode->vsync_len) |

901

msync |= MSYNC_SET_MAINVSA(vmode->vsync_len) |

902

MSYNC_SET_MAINHSA(hsa_wc);

902

MSYNC_SET_MAINHSA(hsa_wc);

903

904

dsim_write(dsim, msync, DSIM_MSYNC);

904

dsim_write(dsim, msync, DSIM_MSYNC);

905

}

905

}

906

907

static void sec_mipi_dsim_config_dpi(struct sec_mipi_dsim *dsim)

907

static void sec_mipi_dsim_config_dpi(struct sec_mipi_dsim *dsim)

908

{

908

{

909

uint32_t config = 0, rgb_status = 0, data_lanes_en;

909

uint32_t config = 0, rgb_status = 0, data_lanes_en;

910

911

if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO)

911

if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO)

912

rgb_status &= ~RGB_STATUS_CMDMODE_INSEL;

912

rgb_status &= ~RGB_STATUS_CMDMODE_INSEL;

913

else

913

else

914

rgb_status |= RGB_STATUS_CMDMODE_INSEL;

914

rgb_status |= RGB_STATUS_CMDMODE_INSEL;

915

916

dsim_write(dsim, rgb_status, DSIM_RGB_STATUS);

916

dsim_write(dsim, rgb_status, DSIM_RGB_STATUS);

917

918

if (dsim->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {

918

if (dsim->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {

919

config |= CONFIG_NON_CONTINUOUS_CLOCK_LANE;

919

config |= CONFIG_NON_CONTINUOUS_CLOCK_LANE;

920

config |= CONFIG_CLKLANE_STOP_START;

920

config |= CONFIG_CLKLANE_STOP_START;

921

}

921

}

922

923

if (dsim->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH)

923

if (dsim->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH)

924

config |= CONFIG_MFLUSH_VS;

924

config |= CONFIG_MFLUSH_VS;

925

926

/* disable EoT packets in HS mode */

926

/* disable EoT packets in HS mode */

927

if (dsim->mode_flags & MIPI_DSI_MODE_EOT_PACKET)

927

if (dsim->mode_flags & MIPI_DSI_MODE_EOT_PACKET)

928

config |= CONFIG_EOT_R03;

928

config |= CONFIG_EOT_R03;

929

930

if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO) {

930

if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO) {

931

config |= CONFIG_VIDEOMODE;

931

config |= CONFIG_VIDEOMODE;

932

933

if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)

933

if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)

934

config |= CONFIG_BURSTMODE;

934

config |= CONFIG_BURSTMODE;

935

936

else if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)

936

else if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)

937

config |= CONFIG_SYNCINFORM;

937

config |= CONFIG_SYNCINFORM;

938

939

if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)

939

if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)

940

config |= CONFIG_AUTOMODE;

940

config |= CONFIG_AUTOMODE;

941

942

if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)

942

if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)

943

config |= CONFIG_HSEDISABLEMODE;

943

config |= CONFIG_HSEDISABLEMODE;

944

945

if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_HFP)

945

if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_HFP)

946

config |= CONFIG_HFPDISABLEMODE;

946

config |= CONFIG_HFPDISABLEMODE;

947

948

if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_HBP)

948

if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_HBP)

949

config |= CONFIG_HBPDISABLEMODE;

949

config |= CONFIG_HBPDISABLEMODE;

950

951

if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_HSA)

951

if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_HSA)

952

config |= CONFIG_HSADISABLEMODE;

952

config |= CONFIG_HSADISABLEMODE;

953

}

953

}

954

955

config |= CONFIG_SET_MAINVC(dsim->channel);

955

config |= CONFIG_SET_MAINVC(dsim->channel);

956

957

if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO) {

957

if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO) {

958

switch (dsim->format) {

958

switch (dsim->format) {

959

case MIPI_DSI_FMT_RGB565:

959

case MIPI_DSI_FMT_RGB565:

960

config |= CONFIG_SET_MAINPIXFORMAT(0x4);

960

config |= CONFIG_SET_MAINPIXFORMAT(0x4);

961

break;

961

break;

962

case MIPI_DSI_FMT_RGB666_PACKED:

962

case MIPI_DSI_FMT_RGB666_PACKED:

963

config |= CONFIG_SET_MAINPIXFORMAT(0x5);

963

config |= CONFIG_SET_MAINPIXFORMAT(0x5);

964

break;

964

break;

965

case MIPI_DSI_FMT_RGB666:

965

case MIPI_DSI_FMT_RGB666:

966

config |= CONFIG_SET_MAINPIXFORMAT(0x6);

966

config |= CONFIG_SET_MAINPIXFORMAT(0x6);

967

break;

967

break;

968

case MIPI_DSI_FMT_RGB888:

968

case MIPI_DSI_FMT_RGB888:

969

config |= CONFIG_SET_MAINPIXFORMAT(0x7);

969

config |= CONFIG_SET_MAINPIXFORMAT(0x7);

970

break;

970

break;

971

default:

971

default:

972

config |= CONFIG_SET_MAINPIXFORMAT(0x7);

972

config |= CONFIG_SET_MAINPIXFORMAT(0x7);

973

break;

973

break;

974

}

974

}

975

}

975

}

976

977

/* config data lanes number and enable lanes */

977

/* config data lanes number and enable lanes */

978

data_lanes_en = (0x1 << dsim->lanes) - 1;

978

data_lanes_en = (0x1 << dsim->lanes) - 1;

979

config |= CONFIG_SET_NUMOFDATLANE(dsim->lanes - 1);

979

config |= CONFIG_SET_NUMOFDATLANE(dsim->lanes - 1);

980

config |= CONFIG_SET_LANEEN(0x1 | data_lanes_en << 1);

980

config |= CONFIG_SET_LANEEN(0x1 | data_lanes_en << 1);

981

982

dsim_write(dsim, config, DSIM_CONFIG);

982

dsim_write(dsim, config, DSIM_CONFIG);

983

}

983

}

984

985

static void sec_mipi_dsim_config_dphy(struct sec_mipi_dsim *dsim)

985

static void sec_mipi_dsim_config_dphy(struct sec_mipi_dsim *dsim)

986

{

986

{

987

struct sec_mipi_dsim_dphy_timing key = { 0 };

987

struct sec_mipi_dsim_dphy_timing key = { 0 };

988

const struct sec_mipi_dsim_dphy_timing *match = NULL;

988

const struct sec_mipi_dsim_dphy_timing *match = NULL;

989

const struct sec_mipi_dsim_plat_data *pdata = dsim->pdata;

989

const struct sec_mipi_dsim_plat_data *pdata = dsim->pdata;

990

uint32_t phytiming = 0, phytiming1 = 0, phytiming2 = 0, timeout = 0;

990

uint32_t phytiming = 0, phytiming1 = 0, phytiming2 = 0, timeout = 0;

991

uint32_t hactive, vactive;

991

uint32_t hactive, vactive;

992

struct videomode *vmode = &dsim->vmode;

992

struct videomode *vmode = &dsim->vmode;

993

struct drm_display_mode mode;

993

struct drm_display_mode mode;

994

995

key.bit_clk = DIV_ROUND_CLOSEST_ULL(dsim->bit_clk, 1000);

995

key.bit_clk = DIV_ROUND_CLOSEST_ULL(dsim->bit_clk, 1000);

996

997

/* '1280x720@60Hz' mode with 2 data lanes

997

/* '1280x720@60Hz' mode with 2 data lanes

998

* requires special fine tuning for DPHY

998

* requires special fine tuning for DPHY

999

* TIMING config according to the tests.

999

* TIMING config according to the tests.

1000

*/

1000

*/

1001

if (dsim->lanes == 2) {

1001

if (dsim->lanes == 2) {

1002

hactive = vmode->hactive;

1002

hactive = vmode->hactive;

1003

vactive = vmode->vactive;

1003

vactive = vmode->vactive;

1004

1005

if (hactive == 1280 && vactive == 720) {

1005

if (hactive == 1280 && vactive == 720) {

1006

memset(&mode, 0x0, sizeof(mode));

1006

memset(&mode, 0x0, sizeof(mode));

1007

drm_display_mode_from_videomode(vmode, &mode);

1007

drm_display_mode_from_videomode(vmode, &mode);

1008

1009

if (drm_mode_vrefresh(&mode) == 60)

1009

if (drm_mode_vrefresh(&mode) == 60)

1010

key.bit_clk >>= 1;

1010

key.bit_clk >>= 1;

1011

}

1011

}

1012

}

1012

}

1013

1014

match = bsearch(&key, pdata->dphy_timing, pdata->num_dphy_timing,

1014

match = bsearch(&key, pdata->dphy_timing, pdata->num_dphy_timing,

1015

sizeof(struct sec_mipi_dsim_dphy_timing),

1015

sizeof(struct sec_mipi_dsim_dphy_timing),

1016

pdata->dphy_timing_cmp);

1016

pdata->dphy_timing_cmp);

1017

if (WARN_ON(!match))

1017

if (WARN_ON(!match))

1018

return;

1018

return;

1019

1020

phytiming |= PHYTIMING_SET_M_TLPXCTL(match->lpx) |

1020

phytiming |= PHYTIMING_SET_M_TLPXCTL(match->lpx) |

1021

PHYTIMING_SET_M_THSEXITCTL(match->hs_exit);

1021

PHYTIMING_SET_M_THSEXITCTL(match->hs_exit);

1022

dsim_write(dsim, phytiming, DSIM_PHYTIMING);

1022

dsim_write(dsim, phytiming, DSIM_PHYTIMING);

1023

1024

phytiming1 |= PHYTIMING1_SET_M_TCLKPRPRCTL(match->clk_prepare) |

1024

phytiming1 |= PHYTIMING1_SET_M_TCLKPRPRCTL(match->clk_prepare) |

1025

PHYTIMING1_SET_M_TCLKZEROCTL(match->clk_zero) |

1025

PHYTIMING1_SET_M_TCLKZEROCTL(match->clk_zero) |

1026

PHYTIMING1_SET_M_TCLKPOSTCTL(match->clk_post) |

1026

PHYTIMING1_SET_M_TCLKPOSTCTL(match->clk_post) |

1027

PHYTIMING1_SET_M_TCLKTRAILCTL(match->clk_trail);

1027

PHYTIMING1_SET_M_TCLKTRAILCTL(match->clk_trail);

1028

dsim_write(dsim, phytiming1, DSIM_PHYTIMING1);

1028

dsim_write(dsim, phytiming1, DSIM_PHYTIMING1);

1029

1030

phytiming2 |= PHYTIMING2_SET_M_THSPRPRCTL(match->hs_prepare) |

1030

phytiming2 |= PHYTIMING2_SET_M_THSPRPRCTL(match->hs_prepare) |

1031

PHYTIMING2_SET_M_THSZEROCTL(match->hs_zero) |

1031

PHYTIMING2_SET_M_THSZEROCTL(match->hs_zero) |

1032

PHYTIMING2_SET_M_THSTRAILCTL(match->hs_trail);

1032

PHYTIMING2_SET_M_THSTRAILCTL(match->hs_trail);

1033

dsim_write(dsim, phytiming2, DSIM_PHYTIMING2);

1033

dsim_write(dsim, phytiming2, DSIM_PHYTIMING2);

1034

1035

timeout |= TIMEOUT_SET_BTAOUT(0xff) |

1035

timeout |= TIMEOUT_SET_BTAOUT(0xff) |

1036

TIMEOUT_SET_LPDRTOUT(0xff);

1036

TIMEOUT_SET_LPDRTOUT(0xff);

1037

dsim_write(dsim, timeout, DSIM_TIMEOUT);

1037

dsim_write(dsim, timeout, DSIM_TIMEOUT);

1038

}

1038

}

1039

1040

static void sec_mipi_dsim_init_fifo_pointers(struct sec_mipi_dsim *dsim)

1040

static void sec_mipi_dsim_init_fifo_pointers(struct sec_mipi_dsim *dsim)

1041

{

1041

{

1042

uint32_t fifoctrl, fifo_ptrs;

1042

uint32_t fifoctrl, fifo_ptrs;

1043

1044

fifoctrl = dsim_read(dsim, DSIM_FIFOCTRL);

1044

fifoctrl = dsim_read(dsim, DSIM_FIFOCTRL);

1045

1046

fifo_ptrs = FIFOCTRL_NINITRX |

1046

fifo_ptrs = FIFOCTRL_NINITRX |

1047

FIFOCTRL_NINITSFR |

1047

FIFOCTRL_NINITSFR |

1048

FIFOCTRL_NINITI80 |

1048

FIFOCTRL_NINITI80 |

1049

FIFOCTRL_NINITSUB |

1049

FIFOCTRL_NINITSUB |

1050

FIFOCTRL_NINITMAIN;

1050

FIFOCTRL_NINITMAIN;

1051

1052

fifoctrl &= ~fifo_ptrs;

1052

fifoctrl &= ~fifo_ptrs;

1053

dsim_write(dsim, fifoctrl, DSIM_FIFOCTRL);

1053

dsim_write(dsim, fifoctrl, DSIM_FIFOCTRL);

1054

udelay(500);

1054

udelay(500);

1055

1056

fifoctrl |= fifo_ptrs;

1056

fifoctrl |= fifo_ptrs;

1057

dsim_write(dsim, fifoctrl, DSIM_FIFOCTRL);

1057

dsim_write(dsim, fifoctrl, DSIM_FIFOCTRL);

1058

udelay(500);

1058

udelay(500);

1059

}

1059

}

1060

1061

static void sec_mipi_dsim_config_clkctrl(struct sec_mipi_dsim *dsim)

1061

static void sec_mipi_dsim_config_clkctrl(struct sec_mipi_dsim *dsim)

1062

{

1062

{

1063

uint32_t clkctrl = 0, data_lanes_en;

1063

uint32_t clkctrl = 0, data_lanes_en;

1064

uint64_t byte_clk, esc_prescaler;

1064

uint32_t byte_clk, esc_prescaler;

1065

1066

clkctrl |= CLKCTRL_TXREQUESTHSCLK;

1066

clkctrl |= CLKCTRL_TXREQUESTHSCLK;

1067

1068

/* using 1.5Gbps PHY */

1068

/* using 1.5Gbps PHY */

1069

clkctrl |= CLKCTRL_DPHY_SEL_1P5G;

1069

clkctrl |= CLKCTRL_DPHY_SEL_1P5G;

1070

1071

clkctrl |= CLKCTRL_ESCCLKEN;

1071

clkctrl |= CLKCTRL_ESCCLKEN;

1072

1073

clkctrl &= ~CLKCTRL_PLLBYPASS;

1073

clkctrl &= ~CLKCTRL_PLLBYPASS;

1074

1075

clkctrl |= CLKCTRL_BYTECLKSRC_DPHY_PLL;

1075

clkctrl |= CLKCTRL_BYTECLKSRC_DPHY_PLL;

1076

1077

clkctrl |= CLKCTRL_BYTECLKEN;

1077

clkctrl |= CLKCTRL_BYTECLKEN;

1078

1079

data_lanes_en = (0x1 << dsim->lanes) - 1;

1079

data_lanes_en = (0x1 << dsim->lanes) - 1;

1080

clkctrl |= CLKCTRL_SET_LANEESCCLKEN(0x1 | data_lanes_en << 1);

1080

clkctrl |= CLKCTRL_SET_LANEESCCLKEN(0x1 | data_lanes_en << 1);

1081

1082

/* calculate esc prescaler from byte clock:

1082

/* calculate esc prescaler from byte clock:

1083

* EscClk = ByteClk / EscPrescaler;

1083

* EscClk = ByteClk / EscPrescaler;

1084

*/

1084

*/

1085

byte_clk = dsim->bit_clk >> 3;

1085

byte_clk = dsim->bit_clk >> 3;

1086

esc_prescaler = DIV_ROUND_UP_ULL(byte_clk, MAX_ESC_CLK_FREQ);

1086

esc_prescaler = DIV_ROUND_UP(byte_clk, MAX_ESC_CLK_FREQ);

1087

clkctrl |= CLKCTRL_SET_ESCPRESCALER(esc_prescaler);

1087

clkctrl |= CLKCTRL_SET_ESCPRESCALER(esc_prescaler);

1088

1089

dsim_write(dsim, clkctrl, DSIM_CLKCTRL);

1089

dsim_write(dsim, clkctrl, DSIM_CLKCTRL);

1090

}

1090

}

1091

1092

static void sec_mipi_dsim_set_standby(struct sec_mipi_dsim *dsim,

1092

static void sec_mipi_dsim_set_standby(struct sec_mipi_dsim *dsim,

1093

bool standby)

1093

bool standby)

1094

{

1094

{

1095

uint32_t mdresol = 0;

1095

uint32_t mdresol = 0;

1096

1097

mdresol = dsim_read(dsim, DSIM_MDRESOL);

1097

mdresol = dsim_read(dsim, DSIM_MDRESOL);

1098

1099

if (standby)

1099

if (standby)

1100

mdresol |= MDRESOL_MAINSTANDBY;

1100

mdresol |= MDRESOL_MAINSTANDBY;

1101

else

1101

else

1102

mdresol &= ~MDRESOL_MAINSTANDBY;

1102

mdresol &= ~MDRESOL_MAINSTANDBY;

1103

1104

dsim_write(dsim, mdresol, DSIM_MDRESOL);

1104

dsim_write(dsim, mdresol, DSIM_MDRESOL);

1105

}

1105

}

1106

1107

int sec_mipi_dsim_check_pll_out(void *driver_private,

1107

int sec_mipi_dsim_check_pll_out(void *driver_private,

1108

const struct drm_display_mode *mode)

1108

const struct drm_display_mode *mode)

1109

{

1109

{

1110

int bpp;

1110

int bpp;

1111

uint64_t pix_clk, bit_clk, ref_clk;

1111

uint32_t pix_clk, bit_clk, ref_clk;

1112

struct sec_mipi_dsim *dsim = driver_private;

1112

struct sec_mipi_dsim *dsim = driver_private;

1113

const struct sec_mipi_dsim_plat_data *pdata = dsim->pdata;

1113

const struct sec_mipi_dsim_plat_data *pdata = dsim->pdata;

1114

const struct dsim_hblank_par *hpar;

1114

const struct dsim_hblank_par *hpar;

1115

const struct dsim_pll_pms *pms;

1115

const struct dsim_pll_pms *pms;

1116

1117

bpp = mipi_dsi_pixel_format_to_bpp(dsim->format);

1117

bpp = mipi_dsi_pixel_format_to_bpp(dsim->format);

1118

if (bpp < 0)

1118

if (bpp < 0)

1119

return -EINVAL;

1119

return -EINVAL;

1120

1121

pix_clk = (uint64_t)mode->clock * 1000;

1121

pix_clk = mode->clock;

1122

bit_clk = DIV_ROUND_UP_ULL(pix_clk * bpp, dsim->lanes);

1122

bit_clk = DIV_ROUND_UP(pix_clk * bpp, dsim->lanes);

1123

1124

if (bit_clk > pdata->max_data_rate) {

1124

if (bit_clk * 1000 > pdata->max_data_rate) {

1125

dev_err(dsim->dev,

1125

dev_err(dsim->dev,

1126

"reuest bit clk freq exceeds lane's maximum value\n");

1126

"reuest bit clk freq exceeds lane's maximum value\n");

1127

return -EINVAL;

1127

return -EINVAL;

1128

}

1128

}

1129

1130

dsim->pix_clk = DIV_ROUND_UP_ULL(pix_clk, 1000);

1130

dsim->pix_clk = pix_clk;

1131

dsim->bit_clk = DIV_ROUND_UP_ULL(bit_clk, 1000);

1131

dsim->bit_clk = bit_clk;

1132

1133

dsim->pms = 0x4210;

1133

dsim->pms = 0x4210;

1134

dsim->hpar = NULL;

1134

dsim->hpar = NULL;

1135

if (dsim->panel)

1135

if (dsim->panel)

1136

return 0;

1136

return 0;

1137

1138

if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {

1138

if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {

1139

hpar = sec_mipi_dsim_get_hblank_par(mode->name,

1139

hpar = sec_mipi_dsim_get_hblank_par(mode->name,

1140

mode->vrefresh,

1140

mode->vrefresh,

1141

dsim->lanes);

1141

dsim->lanes);

1142

if (!hpar)

1142

if (!hpar)

1143

return -EINVAL;

1143

return -EINVAL;

1144

dsim->hpar = hpar;

1144

dsim->hpar = hpar;

1145

1146

pms = sec_mipi_dsim_get_pms(dsim->bit_clk);

1146

pms = sec_mipi_dsim_get_pms(dsim->bit_clk);

1147

if (WARN_ON(!pms))

1147

if (WARN_ON(!pms))

1148

return -EINVAL;

1148

return -EINVAL;

1149

1150

ref_clk = PHY_REF_CLK / 1000;

1150

ref_clk = PHY_REF_CLK / 1000;

1151

/* TODO: add PMS calculate and check

1151

/* TODO: add PMS calculate and check

1152

* Only support '1080p@60Hz' for now,

1152

* Only support '1080p@60Hz' for now,

1153

* add other modes support later

1153

* add other modes support later

1154

*/

1154

*/

1155

dsim->pms = PLLCTRL_SET_P(pms->p) |

1155

dsim->pms = PLLCTRL_SET_P(pms->p) |

1156

PLLCTRL_SET_M(pms->m) |

1156

PLLCTRL_SET_M(pms->m) |

1157

PLLCTRL_SET_S(pms->s);

1157

PLLCTRL_SET_S(pms->s);

1158

}

1158

}

1159

1160

return 0;

1160

return 0;

1161

}

1161

}

1162

EXPORT_SYMBOL(sec_mipi_dsim_check_pll_out);

1162

EXPORT_SYMBOL(sec_mipi_dsim_check_pll_out);

1163

1164

static void sec_mipi_dsim_bridge_enable(struct drm_bridge *bridge)

1164

static void sec_mipi_dsim_bridge_enable(struct drm_bridge *bridge)

1165

{

1165

{

1166

int ret;

1166

int ret;

1167

struct sec_mipi_dsim *dsim = bridge->driver_private;

1167

struct sec_mipi_dsim *dsim = bridge->driver_private;

1168

1169

/* At this moment, the dsim bridge's preceding encoder has

1169

/* At this moment, the dsim bridge's preceding encoder has

1170

* already been enabled. So the dsim can be configed here

1170

* already been enabled. So the dsim can be configed here

1171

*/

1171

*/

1172

1173

/* config main display mode */

1173

/* config main display mode */

1174

sec_mipi_dsim_set_main_mode(dsim);

1174

sec_mipi_dsim_set_main_mode(dsim);

1175

1176

/* config dsim dpi */

1176

/* config dsim dpi */

1177

sec_mipi_dsim_config_dpi(dsim);

1177

sec_mipi_dsim_config_dpi(dsim);

1178

1179

/* config dsim pll */

1179

/* config dsim pll */

1180

ret = sec_mipi_dsim_config_pll(dsim);

1180

ret = sec_mipi_dsim_config_pll(dsim);

1181

if (ret) {

1181

if (ret) {

1182

dev_err(dsim->dev, "dsim pll config failed: %d\n", ret);

1182

dev_err(dsim->dev, "dsim pll config failed: %d\n", ret);

1183

return;

1183

return;

1184

}

1184

}

1185

1186

/* config dphy timings */

1186

/* config dphy timings */

1187

sec_mipi_dsim_config_dphy(dsim);

1187

sec_mipi_dsim_config_dphy(dsim);

1188

1189

/* initialize FIFO pointers */

1189

/* initialize FIFO pointers */

1190

sec_mipi_dsim_init_fifo_pointers(dsim);

1190

sec_mipi_dsim_init_fifo_pointers(dsim);

1191

1192

/* prepare panel if exists */

1192

/* prepare panel if exists */

1193

if (dsim->panel) {

1193

if (dsim->panel) {

1194

ret = drm_panel_prepare(dsim->panel);

1194

ret = drm_panel_prepare(dsim->panel);

1195

if (unlikely(ret)) {

1195

if (unlikely(ret)) {

1196

dev_err(dsim->dev, "panel prepare failed: %d\n", ret);

1196

dev_err(dsim->dev, "panel prepare failed: %d\n", ret);

1197

return;

1197

return;

1198

}

1198

}

1199

}

1199

}

1200

1201

/* config esc clock, byte clock and etc */

1201

/* config esc clock, byte clock and etc */

1202

sec_mipi_dsim_config_clkctrl(dsim);

1202

sec_mipi_dsim_config_clkctrl(dsim);

1203

1204

/* enable panel if exists */

1204

/* enable panel if exists */

1205

if (dsim->panel) {

1205

if (dsim->panel) {

1206

ret = drm_panel_enable(dsim->panel);

1206

ret = drm_panel_enable(dsim->panel);

1207

if (unlikely(ret)) {

1207

if (unlikely(ret)) {

1208

dev_err(dsim->dev, "panel enable failed: %d\n", ret);

1208

dev_err(dsim->dev, "panel enable failed: %d\n", ret);

1209

goto panel_unprepare;

1209

goto panel_unprepare;

1210

}

1210

}

1211

}

1211

}

1212

1213

/* enable data transfer of dsim */

1213

/* enable data transfer of dsim */

1214

sec_mipi_dsim_set_standby(dsim, true);

1214

sec_mipi_dsim_set_standby(dsim, true);

1215

1216

return;

1216

return;

1217

1218

panel_unprepare:

1218

panel_unprepare:

1219

ret = drm_panel_unprepare(dsim->panel);

1219

ret = drm_panel_unprepare(dsim->panel);

1220

if (unlikely(ret))

1220

if (unlikely(ret))

1221

dev_err(dsim->dev, "panel unprepare failed: %d\n", ret);

1221

dev_err(dsim->dev, "panel unprepare failed: %d\n", ret);

1222

}

1222

}

1223

1224

static void sec_mipi_dsim_disable_clkctrl(struct sec_mipi_dsim *dsim)

1224

static void sec_mipi_dsim_disable_clkctrl(struct sec_mipi_dsim *dsim)

1225

{

1225

{

1226

uint32_t clkctrl;

1226

uint32_t clkctrl;

1227

1228

clkctrl = dsim_read(dsim, DSIM_CLKCTRL);

1228

clkctrl = dsim_read(dsim, DSIM_CLKCTRL);

1229

1230

clkctrl &= ~CLKCTRL_TXREQUESTHSCLK;

1230

clkctrl &= ~CLKCTRL_TXREQUESTHSCLK;

1231

1232

clkctrl &= ~CLKCTRL_ESCCLKEN;

1232

clkctrl &= ~CLKCTRL_ESCCLKEN;

1233

1234

clkctrl &= ~CLKCTRL_BYTECLKEN;

1234

clkctrl &= ~CLKCTRL_BYTECLKEN;

1235

1236

dsim_write(dsim, clkctrl, DSIM_CLKCTRL);

1236

dsim_write(dsim, clkctrl, DSIM_CLKCTRL);

1237

}

1237

}

1238

1239

static void sec_mipi_dsim_disable_pll(struct sec_mipi_dsim *dsim)

1239

static void sec_mipi_dsim_disable_pll(struct sec_mipi_dsim *dsim)

1240

{

1240

{

1241

uint32_t pllctrl;

1241

uint32_t pllctrl;

1242

1243

pllctrl = dsim_read(dsim, DSIM_PLLCTRL);

1243

pllctrl = dsim_read(dsim, DSIM_PLLCTRL);

1244

1245

pllctrl &= ~PLLCTRL_PLLEN;

1245

pllctrl &= ~PLLCTRL_PLLEN;

1246

1247

dsim_write(dsim, pllctrl, DSIM_PLLCTRL);

1247

dsim_write(dsim, pllctrl, DSIM_PLLCTRL);

1248

}

1248

}

1249

1250

static void sec_mipi_dsim_bridge_disable(struct drm_bridge *bridge)

1250

static void sec_mipi_dsim_bridge_disable(struct drm_bridge *bridge)

1251

{

1251

{

1252

int ret;

1252

int ret;

1253

struct sec_mipi_dsim *dsim = bridge->driver_private;

1253

struct sec_mipi_dsim *dsim = bridge->driver_private;

1254

1255

/* disable panel if exists */

1255

/* disable panel if exists */

1256

if (dsim->panel) {

1256

if (dsim->panel) {

1257

ret = drm_panel_disable(dsim->panel);

1257

ret = drm_panel_disable(dsim->panel);

1258

if (unlikely(ret))

1258

if (unlikely(ret))

1259

dev_err(dsim->dev, "panel disable failed: %d\n", ret);

1259

dev_err(dsim->dev, "panel disable failed: %d\n", ret);

1260

}

1260

}

1261

1262

/* disable data transfer of dsim */

1262

/* disable data transfer of dsim */

1263

sec_mipi_dsim_set_standby(dsim, false);

1263

sec_mipi_dsim_set_standby(dsim, false);

1264

1265

/* disable esc clock & byte clock */

1265

/* disable esc clock & byte clock */

1266

sec_mipi_dsim_disable_clkctrl(dsim);

1266

sec_mipi_dsim_disable_clkctrl(dsim);

1267

1268

/* disable dsim pll */

1268

/* disable dsim pll */

1269

sec_mipi_dsim_disable_pll(dsim);

1269

sec_mipi_dsim_disable_pll(dsim);

1270

1271

/* unprepare panel if exists */

1271

/* unprepare panel if exists */

1272

if (dsim->panel) {

1272

if (dsim->panel) {

1273

ret = drm_panel_unprepare(dsim->panel);

1273

ret = drm_panel_unprepare(dsim->panel);

1274

if (unlikely(ret))

1274

if (unlikely(ret))

1275

dev_err(dsim->dev, "panel unprepare failed: %d\n", ret);

1275

dev_err(dsim->dev, "panel unprepare failed: %d\n", ret);

1276

}

1276

}

1277

}

1277

}

1278

1279

static bool sec_mipi_dsim_bridge_mode_fixup(struct drm_bridge *bridge,

1279

static bool sec_mipi_dsim_bridge_mode_fixup(struct drm_bridge *bridge,

1280

const struct drm_display_mode *mode,

1280

const struct drm_display_mode *mode,

1281

struct drm_display_mode *adjusted_mode)

1281

struct drm_display_mode *adjusted_mode)

1282

{

1282

{

1283

int private_flags;

1283

int private_flags;

1284

struct sec_mipi_dsim *dsim = bridge->driver_private;

1284

struct sec_mipi_dsim *dsim = bridge->driver_private;

1285

1286

/* Since mipi dsi cannot do color conversion,

1286

/* Since mipi dsi cannot do color conversion,

1287

* so the pixel format output by mipi dsi should

1287

* so the pixel format output by mipi dsi should

1288

* be the same with the pixel format recieved by

1288

* be the same with the pixel format recieved by

1289

* mipi dsi. And the pixel format information needs

1289

* mipi dsi. And the pixel format information needs

1290

* to be passed to CRTC to be checked with the CRTC

1290

* to be passed to CRTC to be checked with the CRTC

1291

* attached plane fb pixel format.

1291

* attached plane fb pixel format.

1292

*/

1292

*/

1293

switch (dsim->format) {

1293

switch (dsim->format) {

1294

case MIPI_DSI_FMT_RGB888:

1294

case MIPI_DSI_FMT_RGB888:

1295

private_flags = MEDIA_BUS_FMT_RGB888_1X24;

1295

private_flags = MEDIA_BUS_FMT_RGB888_1X24;

1296

break;

1296

break;

1297

case MIPI_DSI_FMT_RGB666:

1297

case MIPI_DSI_FMT_RGB666:

1298

private_flags = MEDIA_BUS_FMT_RGB666_1X24_CPADHI;

1298

private_flags = MEDIA_BUS_FMT_RGB666_1X24_CPADHI;

1299

break;

1299

break;

1300

case MIPI_DSI_FMT_RGB666_PACKED:

1300

case MIPI_DSI_FMT_RGB666_PACKED:

1301

private_flags = MEDIA_BUS_FMT_RGB666_1X18;

1301

private_flags = MEDIA_BUS_FMT_RGB666_1X18;

1302

break;

1302

break;

1303

case MIPI_DSI_FMT_RGB565:

1303

case MIPI_DSI_FMT_RGB565:

1304

private_flags = MEDIA_BUS_FMT_RGB565_1X16;

1304

private_flags = MEDIA_BUS_FMT_RGB565_1X16;

1305

break;

1305

break;

1306

default:

1306

default:

1307

return false;

1307

return false;

1308

}

1308

}

1309

1310

adjusted_mode->private_flags = private_flags;

1310

adjusted_mode->private_flags = private_flags;

1311

1312

/* the 'bus_flags' in connector's display_info is useless

1312

/* the 'bus_flags' in connector's display_info is useless

1313

* for mipi dsim, since dsim only sends packets with no

1313

* for mipi dsim, since dsim only sends packets with no

1314

* polarities information in the packets. But the dsim

1314

* polarities information in the packets. But the dsim

1315

* host has some polarities requirements for the CRTC:

1315

* host has some polarities requirements for the CRTC:

1316

* dsim only can accpet active high Vsync, Hsync and DE

1316

* dsim only can accpet active high Vsync, Hsync and DE

1317

* signals.

1317

* signals.

1318

*/

1318

*/

1319

if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) {

1319

if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) {

1320

adjusted_mode->flags &= ~DRM_MODE_FLAG_NHSYNC;

1320

adjusted_mode->flags &= ~DRM_MODE_FLAG_NHSYNC;

1321

adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC;

1321

adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC;

1322

}

1322

}

1323

1324

if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) {

1324

if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) {

1325

adjusted_mode->flags &= ~DRM_MODE_FLAG_NVSYNC;

1325

adjusted_mode->flags &= ~DRM_MODE_FLAG_NVSYNC;

1326

adjusted_mode->flags |= DRM_MODE_FLAG_PVSYNC;

1326

adjusted_mode->flags |= DRM_MODE_FLAG_PVSYNC;

1327

}

1327

}

1328

1329

return true;

1329

return true;

1330

}

1330

}

1331

1332

static void sec_mipi_dsim_bridge_mode_set(struct drm_bridge *bridge,

1332

static void sec_mipi_dsim_bridge_mode_set(struct drm_bridge *bridge,

1333

struct drm_display_mode *mode,

1333

struct drm_display_mode *mode,

1334

struct drm_display_mode *adjusted_mode)

1334

struct drm_display_mode *adjusted_mode)

1335

{

1335

{

1336

struct sec_mipi_dsim *dsim = bridge->driver_private;

1336

struct sec_mipi_dsim *dsim = bridge->driver_private;

1337

1338

/* This hook is called when the display pipe is completely

1338

/* This hook is called when the display pipe is completely

1339

* off. And since the pm runtime is implemented, the dsim

1339

* off. And since the pm runtime is implemented, the dsim

1340

* hardware cannot be accessed at this moment. So move all

1340

* hardware cannot be accessed at this moment. So move all

1341

* the mode_set config to ->enable() hook.

1341

* the mode_set config to ->enable() hook.

1342

* And this hook is called only when 'mode_changed' is true,

1342

* And this hook is called only when 'mode_changed' is true,

1343

* so it is called not every time atomic commit.

1343

* so it is called not every time atomic commit.

1344

*/

1344

*/

1345

1346

/* workaround for CEA standard mode "1280x720@60"

1346

/* workaround for CEA standard mode "1280x720@60"

1347

* display on 4 data lanes with Non-burst with sync

1347

* display on 4 data lanes with Non-burst with sync

1348

* pulse DSI mode, since use the standard horizontal

1348

* pulse DSI mode, since use the standard horizontal

1349

* timings cannot display correctly. And this code

1349

* timings cannot display correctly. And this code

1350

* cannot be put into the dsim Bridge's mode_fixup,

1350

* cannot be put into the dsim Bridge's mode_fixup,

1351

* since the DSI device lane number change always

1351

* since the DSI device lane number change always

1352

* happens after that.

1352

* happens after that.

1353

*/

1353

*/

1354

if (!strcmp(mode->name, "1280x720") &&

1354

if (!strcmp(mode->name, "1280x720") &&

1355

mode->vrefresh == 60 &&

1355

mode->vrefresh == 60 &&

1356

dsim->lanes == 4 &&

1356

dsim->lanes == 4 &&

1357

dsim->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {

1357

dsim->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {

1358

adjusted_mode->hsync_start += 2;

1358

adjusted_mode->hsync_start += 2;

1359

adjusted_mode->hsync_end += 2;

1359

adjusted_mode->hsync_end += 2;

1360

adjusted_mode->htotal += 2;

1360

adjusted_mode->htotal += 2;

1361

}

1361

}

1362

1363

drm_display_mode_to_videomode(adjusted_mode, &dsim->vmode);

1363

drm_display_mode_to_videomode(adjusted_mode, &dsim->vmode);

1364

}

1364

}

1365

1366

static const struct drm_bridge_funcs sec_mipi_dsim_bridge_funcs = {

1366

static const struct drm_bridge_funcs sec_mipi_dsim_bridge_funcs = {

1367

.attach = sec_mipi_dsim_bridge_attach,

1367

.attach = sec_mipi_dsim_bridge_attach,

1368

.enable = sec_mipi_dsim_bridge_enable,

1368

.enable = sec_mipi_dsim_bridge_enable,

1369

.disable = sec_mipi_dsim_bridge_disable,

1369

.disable = sec_mipi_dsim_bridge_disable,

1370

.mode_set = sec_mipi_dsim_bridge_mode_set,

1370

.mode_set = sec_mipi_dsim_bridge_mode_set,

1371

.mode_fixup = sec_mipi_dsim_bridge_mode_fixup,

1371

.mode_fixup = sec_mipi_dsim_bridge_mode_fixup,

1372

};

1372

};

1373

1374

void sec_mipi_dsim_suspend(struct device *dev)

1374

void sec_mipi_dsim_suspend(struct device *dev)

1375

{

1375

{

1376

struct sec_mipi_dsim *dsim = dev_get_drvdata(dev);

1376

struct sec_mipi_dsim *dsim = dev_get_drvdata(dev);

1377

1378

/* TODO: add dsim reset */

1378

/* TODO: add dsim reset */

1379

1380

clk_disable_unprepare(dsim->clk_cfg);

1380

clk_disable_unprepare(dsim->clk_cfg);

1381

1382

clk_disable_unprepare(dsim->clk_pllref);

1382

clk_disable_unprepare(dsim->clk_pllref);

1383

}

1383

}

1384

EXPORT_SYMBOL(sec_mipi_dsim_suspend);

1384

EXPORT_SYMBOL(sec_mipi_dsim_suspend);

1385

1386

void sec_mipi_dsim_resume(struct device *dev)

1386

void sec_mipi_dsim_resume(struct device *dev)

1387

{

1387

{

1388

struct sec_mipi_dsim *dsim = dev_get_drvdata(dev);

1388

struct sec_mipi_dsim *dsim = dev_get_drvdata(dev);

1389

1390

clk_prepare_enable(dsim->clk_pllref);

1390

clk_prepare_enable(dsim->clk_pllref);

1391

1392

clk_prepare_enable(dsim->clk_cfg);

1392

clk_prepare_enable(dsim->clk_cfg);

1393

1394

sec_mipi_dsim_irq_init(dsim);

1394

sec_mipi_dsim_irq_init(dsim);

1395

1396

/* TODO: add dsim de-reset */

1396

/* TODO: add dsim de-reset */

1397

}

1397

}

1398

EXPORT_SYMBOL(sec_mipi_dsim_resume);

1398

EXPORT_SYMBOL(sec_mipi_dsim_resume);

1399

1400

static void __maybe_unused sec_mipi_dsim_irq_mask(struct sec_mipi_dsim *dsim,

1400

static void __maybe_unused sec_mipi_dsim_irq_mask(struct sec_mipi_dsim *dsim,

1401

int irq_idx)

1401

int irq_idx)

1402

{

1402

{

1403

uint32_t intmsk;

1403

uint32_t intmsk;

1404

1405

intmsk = dsim_read(dsim, DSIM_INTMSK);

1405

intmsk = dsim_read(dsim, DSIM_INTMSK);

1406

1407

switch (irq_idx) {

1407

switch (irq_idx) {

1408

case PLLSTABLE:

1408

case PLLSTABLE:

1409

intmsk |= INTMSK_MSKPLLSTABLE;

1409

intmsk |= INTMSK_MSKPLLSTABLE;

1410

break;

1410

break;

1411

case SWRSTRELEASE:

1411

case SWRSTRELEASE:

1412

intmsk |= INTMSK_MSKSWRELEASE;

1412

intmsk |= INTMSK_MSKSWRELEASE;

1413

break;

1413

break;

1414

case SFRPLFIFOEMPTY:

1414

case SFRPLFIFOEMPTY:

1415

intmsk |= INTMSK_MSKSFRPLFIFOEMPTY;

1415

intmsk |= INTMSK_MSKSFRPLFIFOEMPTY;

1416

break;

1416

break;

1417

case SFRPHFIFOEMPTY:

1417

case SFRPHFIFOEMPTY:

1418

intmsk |= INTMSK_MSKSFRPHFIFOEMPTY;

1418

intmsk |= INTMSK_MSKSFRPHFIFOEMPTY;

1419

break;

1419

break;

1420

case FRAMEDONE:

1420

case FRAMEDONE:

1421

intmsk |= INTMSK_MSKFRAMEDONE;

1421

intmsk |= INTMSK_MSKFRAMEDONE;

1422

break;

1422

break;

1423

case LPDRTOUT:

1423

case LPDRTOUT:

1424

intmsk |= INTMSK_MSKLPDRTOUT;

1424

intmsk |= INTMSK_MSKLPDRTOUT;

1425

break;

1425

break;

1426

case TATOUT:

1426

case TATOUT:

1427

intmsk |= INTMSK_MSKTATOUT;

1427

intmsk |= INTMSK_MSKTATOUT;

1428

break;

1428

break;

1429

case RXDATDONE:

1429

case RXDATDONE:

1430

intmsk |= INTMSK_MSKRXDATDONE;

1430

intmsk |= INTMSK_MSKRXDATDONE;

1431

break;

1431

break;

1432

case RXTE:

1432

case RXTE:

1433

intmsk |= INTMSK_MSKRXTE;

1433

intmsk |= INTMSK_MSKRXTE;

1434

break;

1434

break;

1435

case RXACK:

1435

case RXACK:

1436

intmsk |= INTMSK_MSKRXACK;

1436

intmsk |= INTMSK_MSKRXACK;

1437

break;

1437

break;

1438

default:

1438

default:

1439

/* unsupported irq */

1439

/* unsupported irq */

1440

return;

1440

return;

1441

}

1441

}

1442

1443

writel(intmsk, dsim->base + DSIM_INTMSK);

1443

writel(intmsk, dsim->base + DSIM_INTMSK);

1444

}

1444

}

1445

1446

static void sec_mipi_dsim_irq_unmask(struct sec_mipi_dsim *dsim,

1446

static void sec_mipi_dsim_irq_unmask(struct sec_mipi_dsim *dsim,

1447

int irq_idx)

1447

int irq_idx)

1448

{

1448

{

1449

uint32_t intmsk;

1449

uint32_t intmsk;

1450

1451

intmsk = dsim_read(dsim, DSIM_INTMSK);

1451

intmsk = dsim_read(dsim, DSIM_INTMSK);

1452

1453

switch (irq_idx) {

1453

switch (irq_idx) {

1454

case PLLSTABLE:

1454

case PLLSTABLE:

1455

intmsk &= ~INTMSK_MSKPLLSTABLE;

1455

intmsk &= ~INTMSK_MSKPLLSTABLE;

1456

break;

1456

break;

1457

case SWRSTRELEASE:

1457

case SWRSTRELEASE:

1458

intmsk &= ~INTMSK_MSKSWRELEASE;

1458

intmsk &= ~INTMSK_MSKSWRELEASE;

1459

break;

1459

break;

1460

case SFRPLFIFOEMPTY:

1460

case SFRPLFIFOEMPTY:

1461

intmsk &= ~INTMSK_MSKSFRPLFIFOEMPTY;

1461

intmsk &= ~INTMSK_MSKSFRPLFIFOEMPTY;

1462

break;

1462

break;

1463

case SFRPHFIFOEMPTY:

1463

case SFRPHFIFOEMPTY:

1464

intmsk &= ~INTMSK_MSKSFRPHFIFOEMPTY;

1464

intmsk &= ~INTMSK_MSKSFRPHFIFOEMPTY;

1465

break;

1465

break;

1466

case FRAMEDONE:

1466

case FRAMEDONE:

1467

intmsk &= ~INTMSK_MSKFRAMEDONE;

1467

intmsk &= ~INTMSK_MSKFRAMEDONE;

1468

break;

1468

break;

1469

case LPDRTOUT:

1469

case LPDRTOUT:

1470

intmsk &= ~INTMSK_MSKLPDRTOUT;

1470

intmsk &= ~INTMSK_MSKLPDRTOUT;

1471

break;

1471

break;

1472

case TATOUT:

1472

case TATOUT:

1473

intmsk &= ~INTMSK_MSKTATOUT;

1473

intmsk &= ~INTMSK_MSKTATOUT;

1474

break;

1474

break;

1475

case RXDATDONE:

1475

case RXDATDONE:

1476

intmsk &= ~INTMSK_MSKRXDATDONE;

1476

intmsk &= ~INTMSK_MSKRXDATDONE;

1477

break;

1477

break;

1478

case RXTE:

1478

case RXTE:

1479

intmsk &= ~INTMSK_MSKRXTE;

1479

intmsk &= ~INTMSK_MSKRXTE;

1480

break;

1480

break;

1481

case RXACK:

1481

case RXACK:

1482

intmsk &= ~INTMSK_MSKRXACK;

1482

intmsk &= ~INTMSK_MSKRXACK;

1483

break;

1483

break;

1484

default:

1484

default:

1485

/* unsupported irq */

1485

/* unsupported irq */

1486

return;

1486

return;

1487

}

1487

}

1488

1489

dsim_write(dsim, intmsk, DSIM_INTMSK);

1489

dsim_write(dsim, intmsk, DSIM_INTMSK);

1490

}

1490

}

1491

1492

/* write 1 clear irq */

1492

/* write 1 clear irq */

1493

static void sec_mipi_dsim_irq_clear(struct sec_mipi_dsim *dsim,

1493

static void sec_mipi_dsim_irq_clear(struct sec_mipi_dsim *dsim,

1494

int irq_idx)

1494

int irq_idx)

1495

{

1495

{

1496

uint32_t intsrc = 0;

1496

uint32_t intsrc = 0;

1497

1498

switch (irq_idx) {

1498

switch (irq_idx) {

1499

case PLLSTABLE:

1499

case PLLSTABLE:

1500

intsrc |= INTSRC_PLLSTABLE;

1500

intsrc |= INTSRC_PLLSTABLE;

1501

break;

1501

break;

1502

case SWRSTRELEASE:

1502

case SWRSTRELEASE:

1503

intsrc |= INTSRC_SWRSTRELEASE;

1503

intsrc |= INTSRC_SWRSTRELEASE;

1504

break;

1504

break;

1505

case SFRPLFIFOEMPTY:

1505

case SFRPLFIFOEMPTY:

1506

intsrc |= INTSRC_SFRPLFIFOEMPTY;

1506

intsrc |= INTSRC_SFRPLFIFOEMPTY;

1507

break;

1507

break;

1508

case SFRPHFIFOEMPTY:

1508

case SFRPHFIFOEMPTY:

1509

intsrc |= INTSRC_SFRPHFIFOEMPTY;

1509

intsrc |= INTSRC_SFRPHFIFOEMPTY;

1510

break;

1510

break;

1511

case FRAMEDONE:

1511

case FRAMEDONE:

1512

intsrc |= INTSRC_FRAMEDONE;

1512

intsrc |= INTSRC_FRAMEDONE;

1513

break;

1513

break;

1514

case LPDRTOUT:

1514

case LPDRTOUT:

1515

intsrc |= INTSRC_LPDRTOUT;

1515

intsrc |= INTSRC_LPDRTOUT;

1516

break;

1516

break;

1517

case TATOUT:

1517

case TATOUT:

1518

intsrc |= INTSRC_TATOUT;

1518

intsrc |= INTSRC_TATOUT;

1519

break;

1519

break;

1520

case RXDATDONE:

1520

case RXDATDONE:

1521

intsrc |= INTSRC_RXDATDONE;

1521

intsrc |= INTSRC_RXDATDONE;

1522

break;

1522

break;

1523

case RXTE:

1523

case RXTE:

1524

intsrc |= INTSRC_RXTE;

1524

intsrc |= INTSRC_RXTE;

1525

break;

1525

break;

1526

case RXACK:

1526

case RXACK:

1527

intsrc |= INTSRC_RXACK;

1527

intsrc |= INTSRC_RXACK;

1528

break;

1528

break;

1529

default:

1529

default:

1530

/* unsupported irq */

1530

/* unsupported irq */

1531

return;

1531

return;

1532

}

1532

}

1533

1534

dsim_write(dsim, intsrc, DSIM_INTSRC);

1534

dsim_write(dsim, intsrc, DSIM_INTSRC);

1535

}

1535

}

1536

1537

static void sec_mipi_dsim_irq_init(struct sec_mipi_dsim *dsim)

1537

static void sec_mipi_dsim_irq_init(struct sec_mipi_dsim *dsim)

1538

{

1538

{

1539

sec_mipi_dsim_irq_unmask(dsim, PLLSTABLE);

1539

sec_mipi_dsim_irq_unmask(dsim, PLLSTABLE);

1540

sec_mipi_dsim_irq_unmask(dsim, SWRSTRELEASE);

1540

sec_mipi_dsim_irq_unmask(dsim, SWRSTRELEASE);

1541

1542

if (dsim->panel) {

1542

if (dsim->panel) {

1543

sec_mipi_dsim_irq_unmask(dsim, SFRPLFIFOEMPTY);

1543

sec_mipi_dsim_irq_unmask(dsim, SFRPLFIFOEMPTY);

1544

sec_mipi_dsim_irq_unmask(dsim, SFRPHFIFOEMPTY);

1544

sec_mipi_dsim_irq_unmask(dsim, SFRPHFIFOEMPTY);

1545

sec_mipi_dsim_irq_unmask(dsim, LPDRTOUT);

1545

sec_mipi_dsim_irq_unmask(dsim, LPDRTOUT);

1546

sec_mipi_dsim_irq_unmask(dsim, TATOUT);

1546

sec_mipi_dsim_irq_unmask(dsim, TATOUT);

1547

sec_mipi_dsim_irq_unmask(dsim, RXDATDONE);

1547

sec_mipi_dsim_irq_unmask(dsim, RXDATDONE);

1548

sec_mipi_dsim_irq_unmask(dsim, RXTE);

1548

sec_mipi_dsim_irq_unmask(dsim, RXTE);

1549

sec_mipi_dsim_irq_unmask(dsim, RXACK);

1549

sec_mipi_dsim_irq_unmask(dsim, RXACK);

1550

}

1550

}

1551

}

1551

}

1552

1553

static irqreturn_t sec_mipi_dsim_irq_handler(int irq, void *data)

1553

static irqreturn_t sec_mipi_dsim_irq_handler(int irq, void *data)

1554

{

1554

{

1555

uint32_t intsrc, status;

1555

uint32_t intsrc, status;

1556

struct sec_mipi_dsim *dsim = data;

1556

struct sec_mipi_dsim *dsim = data;

1557

1558

intsrc = dsim_read(dsim, DSIM_INTSRC);

1558

intsrc = dsim_read(dsim, DSIM_INTSRC);

1559

status = dsim_read(dsim, DSIM_STATUS);

1559

status = dsim_read(dsim, DSIM_STATUS);

1560

1561

if (WARN_ON(!intsrc)) {

1561

if (WARN_ON(!intsrc)) {

1562

dev_err(dsim->dev, "interrupt is not from dsim\n");

1562

dev_err(dsim->dev, "interrupt is not from dsim\n");

1563

return IRQ_NONE;

1563

return IRQ_NONE;

1564

}

1564

}

1565

1566

if (WARN_ON(!(intsrc & INTSRC_MASK))) {

1566

if (WARN_ON(!(intsrc & INTSRC_MASK))) {

1567

dev_warn(dsim->dev, "unenable irq happens: %#x\n", intsrc);

1567

dev_warn(dsim->dev, "unenable irq happens: %#x\n", intsrc);

1568

/* just clear irqs */

1568

/* just clear irqs */

1569

dsim_write(dsim, intsrc, DSIM_INTSRC);

1569

dsim_write(dsim, intsrc, DSIM_INTSRC);

1570

return IRQ_NONE;

1570

return IRQ_NONE;

1571

}

1571

}

1572

1573

if (intsrc & INTSRC_PLLSTABLE) {

1573

if (intsrc & INTSRC_PLLSTABLE) {

1574

WARN_ON(!(status & STATUS_PLLSTABLE));

1574

WARN_ON(!(status & STATUS_PLLSTABLE));

1575

sec_mipi_dsim_irq_clear(dsim, PLLSTABLE);

1575

sec_mipi_dsim_irq_clear(dsim, PLLSTABLE);

1576

complete(&dsim->pll_stable);

1576

complete(&dsim->pll_stable);

1577

}

1577

}

1578

1579

if (intsrc & INTSRC_SWRSTRELEASE)

1579

if (intsrc & INTSRC_SWRSTRELEASE)

1580

sec_mipi_dsim_irq_clear(dsim, SWRSTRELEASE);

1580

sec_mipi_dsim_irq_clear(dsim, SWRSTRELEASE);

1581

1582

if (intsrc & INTSRC_SFRPLFIFOEMPTY) {

1582

if (intsrc & INTSRC_SFRPLFIFOEMPTY) {

1583

sec_mipi_dsim_irq_clear(dsim, SFRPLFIFOEMPTY);

1583

sec_mipi_dsim_irq_clear(dsim, SFRPLFIFOEMPTY);

1584

complete(&dsim->pl_tx_done);

1584

complete(&dsim->pl_tx_done);

1585

}

1585

}

1586

1587

if (intsrc & INTSRC_SFRPHFIFOEMPTY) {

1587

if (intsrc & INTSRC_SFRPHFIFOEMPTY) {

1588

sec_mipi_dsim_irq_clear(dsim, SFRPHFIFOEMPTY);

1588

sec_mipi_dsim_irq_clear(dsim, SFRPHFIFOEMPTY);

1589

complete(&dsim->ph_tx_done);

1589

complete(&dsim->ph_tx_done);

1590

}

1590

}

1591

1592

if (WARN_ON(intsrc & INTSRC_LPDRTOUT)) {

1592

if (WARN_ON(intsrc & INTSRC_LPDRTOUT)) {

1593

sec_mipi_dsim_irq_clear(dsim, LPDRTOUT);

1593

sec_mipi_dsim_irq_clear(dsim, LPDRTOUT);

1594

dev_warn(dsim->dev, "LP RX timeout\n");

1594

dev_warn(dsim->dev, "LP RX timeout\n");

1595

}

1595

}

1596

1597

if (WARN_ON(intsrc & INTSRC_TATOUT)) {

1597

if (WARN_ON(intsrc & INTSRC_TATOUT)) {

1598

sec_mipi_dsim_irq_clear(dsim, TATOUT);

1598

sec_mipi_dsim_irq_clear(dsim, TATOUT);

1599

dev_warn(dsim->dev, "Turns around Acknowledge timeout\n");

1599

dev_warn(dsim->dev, "Turns around Acknowledge timeout\n");

1600

}

1600

}

1601

1602

if (intsrc & INTSRC_RXDATDONE) {

1602

if (intsrc & INTSRC_RXDATDONE) {

1603

sec_mipi_dsim_irq_clear(dsim, RXDATDONE);

1603

sec_mipi_dsim_irq_clear(dsim, RXDATDONE);

1604

complete(&dsim->rx_done);

1604

complete(&dsim->rx_done);

1605

}

1605

}

1606

1607

if (intsrc & INTSRC_RXTE) {

1607

if (intsrc & INTSRC_RXTE) {

1608

sec_mipi_dsim_irq_clear(dsim, RXTE);

1608

sec_mipi_dsim_irq_clear(dsim, RXTE);

1609

dev_dbg(dsim->dev, "TE Rx trigger received\n");

1609

dev_dbg(dsim->dev, "TE Rx trigger received\n");

1610

}

1610

}

1611

1612

if (intsrc & INTSRC_RXACK) {

1612

if (intsrc & INTSRC_RXACK) {

1613

sec_mipi_dsim_irq_clear(dsim, RXACK);

1613

sec_mipi_dsim_irq_clear(dsim, RXACK);

1614

dev_dbg(dsim->dev, "ACK Rx trigger received\n");

1614

dev_dbg(dsim->dev, "ACK Rx trigger received\n");

1615

}

1615

}

1616

1617

return IRQ_HANDLED;

1617

return IRQ_HANDLED;

1618

}

1618

}

1619

1620

static int sec_mipi_dsim_connector_get_modes(struct drm_connector *connector)

1620

static int sec_mipi_dsim_connector_get_modes(struct drm_connector *connector)

1621

{

1621

{

1622

struct sec_mipi_dsim *dsim = conn_to_sec_mipi_dsim(connector);

1622

struct sec_mipi_dsim *dsim = conn_to_sec_mipi_dsim(connector);

1623

1624

if (WARN_ON(!dsim->panel))

1624

if (WARN_ON(!dsim->panel))

1625

return -ENODEV;

1625

return -ENODEV;

1626

1627

return drm_panel_get_modes(dsim->panel);

1627

return drm_panel_get_modes(dsim->panel);

1628

}

1628

}

1629

1630

static const struct drm_connector_helper_funcs

1630

static const struct drm_connector_helper_funcs

1631

sec_mipi_dsim_connector_helper_funcs = {

1631

sec_mipi_dsim_connector_helper_funcs = {

1632

.get_modes = sec_mipi_dsim_connector_get_modes,

1632

.get_modes = sec_mipi_dsim_connector_get_modes,

1633

};

1633

};

1634

1635

static enum drm_connector_status

1635

static enum drm_connector_status

1636

sec_mipi_dsim_connector_detect(struct drm_connector *connector,

1636

sec_mipi_dsim_connector_detect(struct drm_connector *connector,

1637

bool force)

1637

bool force)

1638

{

1638

{

1639

/* TODO: add support later */

1639

/* TODO: add support later */

1640

1641

return connector_status_connected;

1641

return connector_status_connected;

1642

}

1642

}

1643

1644

static const struct drm_connector_funcs sec_mipi_dsim_connector_funcs = {

1644

static const struct drm_connector_funcs sec_mipi_dsim_connector_funcs = {

1645

.detect = sec_mipi_dsim_connector_detect,

1645

.detect = sec_mipi_dsim_connector_detect,

1646

.fill_modes = drm_helper_probe_single_connector_modes,

1646

.fill_modes = drm_helper_probe_single_connector_modes,

1647

.destroy = drm_connector_cleanup,

1647

.destroy = drm_connector_cleanup,

1648

.reset = drm_atomic_helper_connector_reset,

1648

.reset = drm_atomic_helper_connector_reset,

1649

.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,

1649

.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,

1650

.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,

1650

.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,

1651

};

1651

};

1652

1653

int sec_mipi_dsim_bind(struct device *dev, struct device *master, void *data,

1653

int sec_mipi_dsim_bind(struct device *dev, struct device *master, void *data,

1654

struct drm_encoder *encoder, struct resource *res,

1654

struct drm_encoder *encoder, struct resource *res,

1655

int irq, const struct sec_mipi_dsim_plat_data *pdata)

1655

int irq, const struct sec_mipi_dsim_plat_data *pdata)

1656

{

1656

{

1657

int ret, version;

1657

int ret, version;

1658

struct drm_device *drm_dev = data;

1658

struct drm_device *drm_dev = data;

1659

struct drm_bridge *bridge;

1659

struct drm_bridge *bridge;

1660

struct drm_connector *connector;

1660

struct drm_connector *connector;

1661

struct sec_mipi_dsim *dsim;

1661

struct sec_mipi_dsim *dsim;

1662

1663

dev_dbg(dev, "sec-dsim bridge bind begin\n");

1663

dev_dbg(dev, "sec-dsim bridge bind begin\n");

1664

1665

dsim = devm_kzalloc(dev, sizeof(*dsim), GFP_KERNEL);

1665

dsim = devm_kzalloc(dev, sizeof(*dsim), GFP_KERNEL);

1666

if (!dsim) {

1666

if (!dsim) {

1667

dev_err(dev, "Unable to allocate 'dsim'\n");

1667

dev_err(dev, "Unable to allocate 'dsim'\n");

1668

return -ENOMEM;

1668

return -ENOMEM;

1669

}

1669

}

1670

1671

dsim->dev = dev;

1671

dsim->dev = dev;

1672

dsim->irq = irq;

1672

dsim->irq = irq;

1673

dsim->pdata = pdata;

1673

dsim->pdata = pdata;

1674

dsim->encoder = encoder;

1674

dsim->encoder = encoder;

1675

1676

dsim->dsi_host.ops = &sec_mipi_dsim_host_ops;

1676

dsim->dsi_host.ops = &sec_mipi_dsim_host_ops;

1677

dsim->dsi_host.dev = dev;

1677

dsim->dsi_host.dev = dev;

1678

1679

dsim->base = devm_ioremap_resource(dev, res);

1679

dsim->base = devm_ioremap_resource(dev, res);

1680

if (IS_ERR(dsim->base))

1680

if (IS_ERR(dsim->base))

1681

return PTR_ERR(dsim->base);

1681

return PTR_ERR(dsim->base);

1682

1683

dsim->clk_pllref = devm_clk_get(dev, "pll-ref");

1683

dsim->clk_pllref = devm_clk_get(dev, "pll-ref");

1684

if (IS_ERR(dsim->clk_pllref)) {

1684

if (IS_ERR(dsim->clk_pllref)) {

1685

ret = PTR_ERR(dsim->clk_pllref);

1685

ret = PTR_ERR(dsim->clk_pllref);

1686

dev_err(dev, "Unable to get phy pll reference clock: %d\n", ret);

1686

dev_err(dev, "Unable to get phy pll reference clock: %d\n", ret);

1687

return ret;

1687

return ret;

1688

}

1688

}

1689

1690

dsim->clk_cfg = devm_clk_get(dev, "cfg");

1690

dsim->clk_cfg = devm_clk_get(dev, "cfg");

1691

if (IS_ERR(dsim->clk_cfg)) {

1691

if (IS_ERR(dsim->clk_cfg)) {

1692

ret = PTR_ERR(dsim->clk_cfg);

1692

ret = PTR_ERR(dsim->clk_cfg);

1693

dev_err(dev, "Unable to get configuration clock: %d\n", ret);

1693

dev_err(dev, "Unable to get configuration clock: %d\n", ret);

1694

return ret;

1694

return ret;

1695

}

1695

}

1696

1697

clk_prepare_enable(dsim->clk_cfg);

1697

clk_prepare_enable(dsim->clk_cfg);

1698

version = dsim_read(dsim, DSIM_VERSION);

1698

version = dsim_read(dsim, DSIM_VERSION);

1699

WARN_ON(version != pdata->version);

1699

WARN_ON(version != pdata->version);

1700

clk_disable_unprepare(dsim->clk_cfg);

1700

clk_disable_unprepare(dsim->clk_cfg);

1701

1702

dev_info(dev, "version number is %#x\n", version);

1702

dev_info(dev, "version number is %#x\n", version);

1703

1704

/* TODO: set pll ref clock rate to be fixed with 27MHz */

1704

/* TODO: set pll ref clock rate to be fixed with 27MHz */

1705

ret = clk_set_rate(dsim->clk_pllref, PHY_REF_CLK);

1705

ret = clk_set_rate(dsim->clk_pllref, PHY_REF_CLK);

1706

if (ret) {

1706

if (ret) {

1707

dev_err(dev, "failed to set pll ref clock rate\n");

1707

dev_err(dev, "failed to set pll ref clock rate\n");

1708

return ret;

1708

return ret;

1709

}

1709

}

1710

1711

ret = devm_request_irq(dev, dsim->irq,

1711

ret = devm_request_irq(dev, dsim->irq,

1712

sec_mipi_dsim_irq_handler,

1712

sec_mipi_dsim_irq_handler,

1713

0, dev_name(dev), dsim);

1713

0, dev_name(dev), dsim);

1714

if (ret) {

1714

if (ret) {

1715

dev_err(dev, "failed to request dsim irq: %d\n", ret);

1715

dev_err(dev, "failed to request dsim irq: %d\n", ret);

1716

return ret;

1716

return ret;

1717

}

1717

}

1718

1719

init_completion(&dsim->pll_stable);

1719

init_completion(&dsim->pll_stable);

1720

init_completion(&dsim->ph_tx_done);

1720

init_completion(&dsim->ph_tx_done);

1721

init_completion(&dsim->pl_tx_done);

1721

init_completion(&dsim->pl_tx_done);

1722

init_completion(&dsim->rx_done);

1722

init_completion(&dsim->rx_done);

1723

1724

/* Initialize and attach sec dsim bridge */

1724

/* Initialize and attach sec dsim bridge */

1725

bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL);

1725

bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL);

1726

if (!bridge) {

1726

if (!bridge) {

1727

dev_err(dev, "Unable to allocate 'bridge'\n");

1727

dev_err(dev, "Unable to allocate 'bridge'\n");

1728

return -ENOMEM;

1728

return -ENOMEM;

1729

}

1729

}

1730

1731

/* mipi dsi host needs to be registered before bridge attach, since:

1731

/* mipi dsi host needs to be registered before bridge attach, since:

1732

* 1. Have Panel

1732

* 1. Have Panel

1733

* The 'mipi_dsi_host_register' will allocate a mipi_dsi_device

1733

* The 'mipi_dsi_host_register' will allocate a mipi_dsi_device

1734

* if the dsi host node has a panel child node in DTB. And dsi

1734

* if the dsi host node has a panel child node in DTB. And dsi

1735

* host ->attach() will be called in panel's probe().

1735

* host ->attach() will be called in panel's probe().

1736

*

1736

*

1737

* 2. Have Bridge

1737

* 2. Have Bridge

1738

* The dsi host ->attach() will be called through the below

1738

* The dsi host ->attach() will be called through the below

1739

* 'drm_bridge_attach()' which will attach next bridge in a

1739

* 'drm_bridge_attach()' which will attach next bridge in a

1740

* chain.

1740

* chain.

1741

*/

1741

*/

1742

ret = mipi_dsi_host_register(&dsim->dsi_host);

1742

ret = mipi_dsi_host_register(&dsim->dsi_host);

1743

if (ret) {

1743

if (ret) {

1744

dev_err(dev, "Unable to register mipi dsi host: %d\n", ret);

1744

dev_err(dev, "Unable to register mipi dsi host: %d\n", ret);

1745

return ret;

1745

return ret;

1746

}

1746

}

1747

1748

dsim->bridge = bridge;

1748

dsim->bridge = bridge;

1749

bridge->driver_private = dsim;

1749

bridge->driver_private = dsim;

1750

bridge->funcs = &sec_mipi_dsim_bridge_funcs;

1750

bridge->funcs = &sec_mipi_dsim_bridge_funcs;

1751

bridge->of_node = dev->of_node;

1751

bridge->of_node = dev->of_node;

1752

bridge->encoder = encoder;

1752

bridge->encoder = encoder;

1753

encoder->bridge = bridge;

1753

encoder->bridge = bridge;

1754

1755

dev_set_drvdata(dev, dsim);

1755

dev_set_drvdata(dev, dsim);

1756

1757

/* attach sec dsim bridge and its next bridge if exists */

1757

/* attach sec dsim bridge and its next bridge if exists */

1758

ret = drm_bridge_attach(encoder, bridge, NULL);

1758

ret = drm_bridge_attach(encoder, bridge, NULL);

1759

if (ret) {

1759

if (ret) {

1760

dev_err(dev, "Failed to attach bridge: %s\n", dev_name(dev));

1760

dev_err(dev, "Failed to attach bridge: %s\n", dev_name(dev));

1761

mipi_dsi_host_unregister(&dsim->dsi_host);

1761

mipi_dsi_host_unregister(&dsim->dsi_host);

1762

return ret;

1762

return ret;

1763

}

1763

}

1764

1765

if (dsim->panel) {

1765

if (dsim->panel) {

1766

/* A panel has been attached */

1766

/* A panel has been attached */

1767

connector = &dsim->connector;

1767

connector = &dsim->connector;

1768

1769

drm_connector_helper_add(connector,

1769

drm_connector_helper_add(connector,

1770

&sec_mipi_dsim_connector_helper_funcs);

1770

&sec_mipi_dsim_connector_helper_funcs);

1771

ret = drm_connector_init(drm_dev, connector,

1771

ret = drm_connector_init(drm_dev, connector,

1772

&sec_mipi_dsim_connector_funcs,

1772

&sec_mipi_dsim_connector_funcs,

1773

DRM_MODE_CONNECTOR_DSI);

1773

DRM_MODE_CONNECTOR_DSI);

1774

if (ret)

1774

if (ret)

1775

goto host_unregister;

1775

goto host_unregister;

1776

1777

/* TODO */

1777

/* TODO */

1778

connector->dpms = DRM_MODE_DPMS_OFF;

1778

connector->dpms = DRM_MODE_DPMS_OFF;

1779

1780

ret = drm_mode_connector_attach_encoder(connector, encoder);

1780

ret = drm_mode_connector_attach_encoder(connector, encoder);

1781

if (ret)

1781

if (ret)

1782

goto cleanup_connector;

1782

goto cleanup_connector;

1783

1784

ret = drm_panel_attach(dsim->panel, connector);

1784

ret = drm_panel_attach(dsim->panel, connector);

1785

if (ret)

1785

if (ret)

1786

goto cleanup_connector;

1786

goto cleanup_connector;

1787

}

1787

}

1788

1789

dev_dbg(dev, "sec-dsim bridge bind end\n");

1789

dev_dbg(dev, "sec-dsim bridge bind end\n");

1790

1791

return 0;

1791

return 0;

1792

1793

cleanup_connector:

1793

cleanup_connector:

1794

drm_connector_cleanup(connector);

1794

drm_connector_cleanup(connector);

1795

host_unregister:

1795

host_unregister:

1796

mipi_dsi_host_unregister(&dsim->dsi_host);

1796

mipi_dsi_host_unregister(&dsim->dsi_host);

1797

return ret;

1797

return ret;

1798

}

1798

}

1799

EXPORT_SYMBOL(sec_mipi_dsim_bind);

1799

EXPORT_SYMBOL(sec_mipi_dsim_bind);

1800

1801

void sec_mipi_dsim_unbind(struct device *dev, struct device *master, void *data)

1801

void sec_mipi_dsim_unbind(struct device *dev, struct device *master, void *data)

1802

{

1802

{

1803

struct sec_mipi_dsim *dsim = dev_get_drvdata(dev);

1803

struct sec_mipi_dsim *dsim = dev_get_drvdata(dev);

1804

1805

if (dsim->panel) {

1805

if (dsim->panel) {

1806

drm_panel_detach(dsim->panel);

1806

drm_panel_detach(dsim->panel);

1807

drm_connector_cleanup(&dsim->connector);

1807

drm_connector_cleanup(&dsim->connector);

1808

dsim->panel = NULL;

1808

dsim->panel = NULL;

1809

}

1809

}

1810

1811

mipi_dsi_host_unregister(&dsim->dsi_host);

1811

mipi_dsi_host_unregister(&dsim->dsi_host);

1812

}

1812

}

1813

EXPORT_SYMBOL(sec_mipi_dsim_unbind);

1813

EXPORT_SYMBOL(sec_mipi_dsim_unbind);

1814

1815

MODULE_DESCRIPTION("Samsung MIPI DSI Host Controller bridge driver");

1815

MODULE_DESCRIPTION("Samsung MIPI DSI Host Controller bridge driver");

1816

MODULE_AUTHOR("Fancy Fang <chen.fang@nxp.com>");

1816

MODULE_AUTHOR("Fancy Fang <chen.fang@nxp.com>");

1817

MODULE_LICENSE("GPL");

1817

MODULE_LICENSE("GPL");

1818

GITLAB

Eric Lee / smarc-fsl-linux-kernel

MLK-21150-1 drm/bridge: sec-dsim: change uint64_t clk fields to uint32_t