Eric Lee / smarc-fsl-linux-kernel

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Commit 9c4609783e120d86fdfa4d63af7227d69646e1ef

Authored by Fancy Fang
1 parent 074b89e4a2
Exists in smarc_8mm_imx_4.14.98_2.0.0_ga and in 4 other branches smarc-imx6_4.14.98_2.0.0_ga, smarc-imx7_4.14.98_2.0.0_ga, smarc_8m_00d0_imx_4.14.98_2.0.0_ga, smarc_8m_imx_4.14.98_2.0.0_ga

MLK-21150-1 drm/bridge: sec-dsim: change uint64_t clk fields to uint32_t 

Change the 'bit_clk' and 'pix_clk' fields of struct sec_mipi_dsim
and the 'bit_clk' field of struct dsim_pll_pms from 'uint64_t' type
to 'uint32_t' type, since first, these two fields are in KHz unit,
and so 32 bit unsigned integer is enough to hold the data values,
and second, use 32 bit integer can simplify related clocks compute.

Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 3e62c748a531ca5eacbf6a616d3a979be5222b9c)

Showing 1 changed file with 13 additions and 13 deletions Side-by-side Diff

drivers/gpu/drm/bridge/sec-dsim.c
Diff comments   View file @ 9c46097
1 1 /*
2 2 * Samsung MIPI DSIM Bridge
3 3 *
4   - * Copyright 2018 NXP
  4 + * Copyright 2018-2019 NXP
5 5 *
6 6 * This program is free software; you can redistribute it and/or modify
7 7 * it under the terms of the GNU General Public License as published by
... ... @@ -289,7 +289,7 @@
289 289 };
290 290  
291 291 struct dsim_pll_pms {
292   - uint64_t bit_clk; /* kHz */
  292 + uint32_t bit_clk; /* kHz */
293 293 uint32_t p;
294 294 uint32_t m;
295 295 uint32_t s;
... ... @@ -312,8 +312,8 @@
312 312 struct clk *pclk; /* pixel clock */
313 313  
314 314 /* kHz clocks */
315   - uint64_t pix_clk;
316   - uint64_t bit_clk;
  315 + uint32_t pix_clk;
  316 + uint32_t bit_clk;
317 317  
318 318 unsigned int lanes;
319 319 unsigned int channel; /* virtual channel */
... ... @@ -436,7 +436,7 @@
436 436 return NULL;
437 437 }
438 438  
439   -static const struct dsim_pll_pms *sec_mipi_dsim_get_pms(uint64_t bit_clk)
  439 +static const struct dsim_pll_pms *sec_mipi_dsim_get_pms(uint32_t bit_clk)
440 440 {
441 441 int i;
442 442 const struct dsim_pll_pms *pms;
... ... @@ -1061,7 +1061,7 @@
1061 1061 static void sec_mipi_dsim_config_clkctrl(struct sec_mipi_dsim *dsim)
1062 1062 {
1063 1063 uint32_t clkctrl = 0, data_lanes_en;
1064   - uint64_t byte_clk, esc_prescaler;
  1064 + uint32_t byte_clk, esc_prescaler;
1065 1065  
1066 1066 clkctrl |= CLKCTRL_TXREQUESTHSCLK;
1067 1067  
... ... @@ -1083,7 +1083,7 @@
1083 1083 * EscClk = ByteClk / EscPrescaler;
1084 1084 */
1085 1085 byte_clk = dsim->bit_clk >> 3;
1086   - esc_prescaler = DIV_ROUND_UP_ULL(byte_clk, MAX_ESC_CLK_FREQ);
  1086 + esc_prescaler = DIV_ROUND_UP(byte_clk, MAX_ESC_CLK_FREQ);
1087 1087 clkctrl |= CLKCTRL_SET_ESCPRESCALER(esc_prescaler);
1088 1088  
1089 1089 dsim_write(dsim, clkctrl, DSIM_CLKCTRL);
... ... @@ -1108,7 +1108,7 @@
1108 1108 const struct drm_display_mode *mode)
1109 1109 {
1110 1110 int bpp;
1111   - uint64_t pix_clk, bit_clk, ref_clk;
  1111 + uint32_t pix_clk, bit_clk, ref_clk;
1112 1112 struct sec_mipi_dsim *dsim = driver_private;
1113 1113 const struct sec_mipi_dsim_plat_data *pdata = dsim->pdata;
1114 1114 const struct dsim_hblank_par *hpar;
1115 1115  
1116 1116  
... ... @@ -1118,17 +1118,17 @@
1118 1118 if (bpp < 0)
1119 1119 return -EINVAL;
1120 1120  
1121   - pix_clk = (uint64_t)mode->clock * 1000;
1122   - bit_clk = DIV_ROUND_UP_ULL(pix_clk * bpp, dsim->lanes);
  1121 + pix_clk = mode->clock;
  1122 + bit_clk = DIV_ROUND_UP(pix_clk * bpp, dsim->lanes);
1123 1123  
1124   - if (bit_clk > pdata->max_data_rate) {
  1124 + if (bit_clk * 1000 > pdata->max_data_rate) {
1125 1125 dev_err(dsim->dev,
1126 1126 "reuest bit clk freq exceeds lane's maximum value\n");
1127 1127 return -EINVAL;
1128 1128 }
1129 1129  
1130   - dsim->pix_clk = DIV_ROUND_UP_ULL(pix_clk, 1000);
1131   - dsim->bit_clk = DIV_ROUND_UP_ULL(bit_clk, 1000);
  1130 + dsim->pix_clk = pix_clk;
  1131 + dsim->bit_clk = bit_clk;
1132 1132  
1133 1133 dsim->pms = 0x4210;
1134 1134 dsim->hpar = NULL;