Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq updates from Thomas Gleixner: "Two patches from the irq departement: - a simple fix to make dummy_irq_chip usable for wakeup scenarios - removal of the gic arch_extn hackery. Now that all users are converted we really want to get rid of the interface so people wont come up with new use cases" * 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip: gic: Drop support for gic_arch_extn genirq: Set IRQCHIP_SKIP_SET_WAKE flag for dummy_irq_chip

Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq updates from Thomas Gleixner: "Two patches from the irq departement: - a simple fix to make dummy_irq_chip usable for wakeup scenarios - removal of the gic arch_extn hackery. Now that all users are converted we really want to get rid of the interface so people wont come up with new use cases" * 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip: gic: Drop support for gic_arch_extn genirq: Set IRQCHIP_SKIP_SET_WAKE flag for dummy_irq_chip
Linus Torvalds
2 parents 95f3b1f4b1 1dcc73d7bb
Showing 3 changed files Side-by-side Diff
drivers/irqchip/irq-gic.c
include/linux/irqchip/arm-gic.h
kernel/irq/dummychip.c
@@ -82,19 +82,6 @@
 #define NR_GIC_CPU_IF 8
 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
  
-/*
- * Supported arch specific GIC irq extension.
- * Default make them NULL.
- */
-struct irq_chip gic_arch_extn = {
-	.irq_eoi	= NULL,
-	.irq_mask	= NULL,
-	.irq_unmask	= NULL,
-	.irq_retrigger	= NULL,
-	.irq_set_type	= NULL,
-	.irq_set_wake	= NULL,
-};
-
 #ifndef MAX_GIC_NR
 #define MAX_GIC_NR	1
 #endif
  
  
  
  
@@ -167,34 +154,16 @@
  
 static void gic_mask_irq(struct irq_data *d)
 {
-	unsigned long flags;
-
-	raw_spin_lock_irqsave(&irq_controller_lock, flags);
 	gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR);
-	if (gic_arch_extn.irq_mask)
-		gic_arch_extn.irq_mask(d);
-	raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
 }
  
 static void gic_unmask_irq(struct irq_data *d)
 {
-	unsigned long flags;
-
-	raw_spin_lock_irqsave(&irq_controller_lock, flags);
-	if (gic_arch_extn.irq_unmask)
-		gic_arch_extn.irq_unmask(d);
 	gic_poke_irq(d, GIC_DIST_ENABLE_SET);
-	raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
 }
  
 static void gic_eoi_irq(struct irq_data *d)
 {
-	if (gic_arch_extn.irq_eoi) {
-		raw_spin_lock(&irq_controller_lock);
-		gic_arch_extn.irq_eoi(d);
-		raw_spin_unlock(&irq_controller_lock);
-	}
-
 	writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
 }
  
@@ -251,8 +220,6 @@
 {
 	void __iomem *base = gic_dist_base(d);
 	unsigned int gicirq = gic_irq(d);
-	unsigned long flags;
-	int ret;
  
 	/* Interrupt configuration for SGIs can't be changed */
 	if (gicirq < 16)
  
@@ -263,27 +230,9 @@
 			    type != IRQ_TYPE_EDGE_RISING)
 		return -EINVAL;
  
-	raw_spin_lock_irqsave(&irq_controller_lock, flags);
-
-	if (gic_arch_extn.irq_set_type)
-		gic_arch_extn.irq_set_type(d, type);
-
-	ret = gic_configure_irq(gicirq, type, base, NULL);
-
-	raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
-
-	return ret;
+	return gic_configure_irq(gicirq, type, base, NULL);
 }
  
-static int gic_retrigger(struct irq_data *d)
-{
-	if (gic_arch_extn.irq_retrigger)
-		return gic_arch_extn.irq_retrigger(d);
-
-	/* the genirq layer expects 0 if we can't retrigger in hardware */
-	return 0;
-}
-
 #ifdef CONFIG_SMP
 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
 			    bool force)
@@ -312,21 +261,6 @@
 }
 #endif
  
-#ifdef CONFIG_PM
-static int gic_set_wake(struct irq_data *d, unsigned int on)
-{
-	int ret = -ENXIO;
-
-	if (gic_arch_extn.irq_set_wake)
-		ret = gic_arch_extn.irq_set_wake(d, on);
-
-	return ret;
-}
-
-#else
-#define gic_set_wake	NULL
-#endif
-
 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
 {
 	u32 irqstat, irqnr;
  
@@ -385,11 +319,9 @@
 	.irq_unmask		= gic_unmask_irq,
 	.irq_eoi		= gic_eoi_irq,
 	.irq_set_type		= gic_set_type,
-	.irq_retrigger		= gic_retrigger,
 #ifdef CONFIG_SMP
 	.irq_set_affinity	= gic_set_affinity,
 #endif
-	.irq_set_wake		= gic_set_wake,
 	.irq_get_irqchip_state	= gic_irq_get_irqchip_state,
 	.irq_set_irqchip_state	= gic_irq_set_irqchip_state,
 };
@@ -1055,7 +987,6 @@
 		set_handle_irq(gic_handle_irq);
 	}
  
-	gic_chip.flags |= gic_arch_extn.flags;
 	gic_dist_init(gic);
 	gic_cpu_init(gic);
 	gic_pm_init(gic);
@@ -95,8 +95,6 @@
  
 struct device_node;
  
-extern struct irq_chip gic_arch_extn;
-
 void gic_set_irqchip_flags(unsigned long flags);
 void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
 		    u32 offset, struct device_node *);
@@ -57,6 +57,7 @@
 	.irq_ack	= noop,
 	.irq_mask	= noop,
 	.irq_unmask	= noop,
+	.flags		= IRQCHIP_SKIP_SET_WAKE,
 };
 EXPORT_SYMBOL_GPL(dummy_irq_chip);
...	...	@@ -82,19 +82,6 @@
82	82	#define NR_GIC_CPU_IF 8
83	83	static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
84	84
85		-/*
86		- * Supported arch specific GIC irq extension.
87		- * Default make them NULL.
88		- */
89		-struct irq_chip gic_arch_extn = {
90		- .irq_eoi = NULL,
91		- .irq_mask = NULL,
92		- .irq_unmask = NULL,
93		- .irq_retrigger = NULL,
94		- .irq_set_type = NULL,
95		- .irq_set_wake = NULL,
96		-};
97		-
98	85	#ifndef MAX_GIC_NR
99	86	#define MAX_GIC_NR 1
100	87	#endif
101	88
102	89
103	90
104	91
...	...	@@ -167,34 +154,16 @@
167	154
168	155	static void gic_mask_irq(struct irq_data *d)
169	156	{
170		- unsigned long flags;
171		-
172		- raw_spin_lock_irqsave(&irq_controller_lock, flags);
173	157	gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR);
174		- if (gic_arch_extn.irq_mask)
175		- gic_arch_extn.irq_mask(d);
176		- raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
177	158	}
178	159
179	160	static void gic_unmask_irq(struct irq_data *d)
180	161	{
181		- unsigned long flags;
182		-
183		- raw_spin_lock_irqsave(&irq_controller_lock, flags);
184		- if (gic_arch_extn.irq_unmask)
185		- gic_arch_extn.irq_unmask(d);
186	162	gic_poke_irq(d, GIC_DIST_ENABLE_SET);
187		- raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
188	163	}
189	164
190	165	static void gic_eoi_irq(struct irq_data *d)
191	166	{
192		- if (gic_arch_extn.irq_eoi) {
193		- raw_spin_lock(&irq_controller_lock);
194		- gic_arch_extn.irq_eoi(d);
195		- raw_spin_unlock(&irq_controller_lock);
196		- }
197		-
198	167	writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
199	168	}
200	169
...	...	@@ -251,8 +220,6 @@
251	220	{
252	221	void __iomem *base = gic_dist_base(d);
253	222	unsigned int gicirq = gic_irq(d);
254		- unsigned long flags;
255		- int ret;
256	223
257	224	/* Interrupt configuration for SGIs can't be changed */
258	225	if (gicirq < 16)
259	226
...	...	@@ -263,27 +230,9 @@
263	230	type != IRQ_TYPE_EDGE_RISING)
264	231	return -EINVAL;
265	232
266		- raw_spin_lock_irqsave(&irq_controller_lock, flags);
267		-
268		- if (gic_arch_extn.irq_set_type)
269		- gic_arch_extn.irq_set_type(d, type);
270		-
271		- ret = gic_configure_irq(gicirq, type, base, NULL);
272		-
273		- raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
274		-
275		- return ret;
	233	+ return gic_configure_irq(gicirq, type, base, NULL);
276	234	}
277	235
278		-static int gic_retrigger(struct irq_data *d)
279		-{
280		- if (gic_arch_extn.irq_retrigger)
281		- return gic_arch_extn.irq_retrigger(d);
282		-
283		- /* the genirq layer expects 0 if we can't retrigger in hardware */
284		- return 0;
285		-}
286		-
287	236	#ifdef CONFIG_SMP
288	237	static int gic_set_affinity(struct irq_data d, const struct cpumask mask_val,
289	238	bool force)
...	...	@@ -312,21 +261,6 @@
312	261	}
313	262	#endif
314	263
315		-#ifdef CONFIG_PM
316		-static int gic_set_wake(struct irq_data *d, unsigned int on)
317		-{
318		- int ret = -ENXIO;
319		-
320		- if (gic_arch_extn.irq_set_wake)
321		- ret = gic_arch_extn.irq_set_wake(d, on);
322		-
323		- return ret;
324		-}
325		-
326		-#else
327		-#define gic_set_wake NULL
328		-#endif
329		-
330	264	static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
331	265	{
332	266	u32 irqstat, irqnr;
333	267
...	...	@@ -385,11 +319,9 @@
385	319	.irq_unmask = gic_unmask_irq,
386	320	.irq_eoi = gic_eoi_irq,
387	321	.irq_set_type = gic_set_type,
388		- .irq_retrigger = gic_retrigger,
389	322	#ifdef CONFIG_SMP
390	323	.irq_set_affinity = gic_set_affinity,
391	324	#endif
392		- .irq_set_wake = gic_set_wake,
393	325	.irq_get_irqchip_state = gic_irq_get_irqchip_state,
394	326	.irq_set_irqchip_state = gic_irq_set_irqchip_state,
395	327	};
...	...	@@ -1055,7 +987,6 @@
1055	987	set_handle_irq(gic_handle_irq);
1056	988	}
1057	989
1058		- gic_chip.flags \|= gic_arch_extn.flags;
1059	990	gic_dist_init(gic);
1060	991	gic_cpu_init(gic);
1061	992	gic_pm_init(gic);
...	...	@@ -95,8 +95,6 @@
95	95
96	96	struct device_node;
97	97
98		-extern struct irq_chip gic_arch_extn;
99		-
100	98	void gic_set_irqchip_flags(unsigned long flags);
101	99	void gic_init_bases(unsigned int, int, void __iomem , void __iomem ,
102	100	u32 offset, struct device_node *);
...	...	@@ -57,6 +57,7 @@
57	57	.irq_ack = noop,
58	58	.irq_mask = noop,
59	59	.irq_unmask = noop,
	60	+ .flags = IRQCHIP_SKIP_SET_WAKE,
60	61	};
61	62	EXPORT_SYMBOL_GPL(dummy_irq_chip);