Commit 9ed0a21714852909744fab9c88699286a5ece244

Authored by Fancy Fang
1 parent 095db161b2

MLK-21150-3 drm/bridge: sec-dsim: add a new property 'pref-rate'

Add a new property 'pref-rate' support which can be used to
assign a different clock frequency for the DPHY PLL reference
clock in the dtb file. And if this property does not exist,
the default clock frequency for the reference clock will be
used. And according to the spec, the DPHY PLL reference clk
frequency should be in [6MHz, 300MHz] range.

Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit a9fafe8108505f8a1580af898ff5fa9c26d03680)

Showing 2 changed files with 60 additions and 4 deletions Side-by-side Diff

Documentation/devicetree/bindings/display/bridge/sec_dsim.txt
... ... @@ -16,6 +16,9 @@
16 16 "pll-ref" - DSIM PHY PLL reference clock
17 17 - assigned-clocks: phandles to clocks that requires initial configuration
18 18 - assigned-clock-rates: rates of the clocks that requires initial configuration
  19 +- pref-clk: Assign DPHY PLL reference clock frequency. If not exists,
  20 + DSIM bridge driver will use the default lock frequency
  21 + which is 27MHz.
19 22 - port: input and output port nodes with endpoint definitions as
20 23 defined in Documentation/devicetree/bindings/graph.txt;
21 24 the input port should be connected to an encoder or a
drivers/gpu/drm/bridge/sec-dsim.c
... ... @@ -225,7 +225,7 @@
225 225 #define dsim_write(dsim, val, reg) writel(val, dsim->base + reg)
226 226  
227 227 /* fixed phy ref clk rate */
228   -#define PHY_REF_CLK 27000000
  228 +#define PHY_REF_CLK 27000
229 229  
230 230 #define MAX_MAIN_HRESOL 2047
231 231 #define MAX_MAIN_VRESOL 2047
... ... @@ -318,6 +318,7 @@
318 318 /* kHz clocks */
319 319 uint32_t pix_clk;
320 320 uint32_t bit_clk;
  321 + uint32_t pref_clk; /* phy ref clock rate in KHz */
321 322  
322 323 unsigned int lanes;
323 324 unsigned int channel; /* virtual channel */
... ... @@ -440,6 +441,58 @@
440 441 return NULL;
441 442 }
442 443  
  444 +static int sec_mipi_dsim_set_pref_rate(struct sec_mipi_dsim *dsim)
  445 +{
  446 + int ret;
  447 + uint32_t rate;
  448 + struct device *dev = dsim->dev;
  449 +
  450 + ret = of_property_read_u32(dev->of_node, "pref-rate", &rate);
  451 + if (ret < 0) {
  452 + dev_dbg(dev, "no valid rate assigned for pref clock\n");
  453 + dsim->pref_clk = PHY_REF_CLK;
  454 + } else {
  455 + if (unlikely(rate < 6000 || rate > 300000)) {
  456 + dev_warn(dev, "pref-rate get is invalid: %uKHz\n",
  457 + rate);
  458 + dsim->pref_clk = PHY_REF_CLK;
  459 + } else
  460 + dsim->pref_clk = rate;
  461 + }
  462 +
  463 +set_rate:
  464 + ret = clk_set_rate(dsim->clk_pllref,
  465 + ((unsigned long)dsim->pref_clk) * 1000);
  466 + if (ret) {
  467 + dev_err(dev, "failed to set pll ref clock rate\n");
  468 + return ret;
  469 + }
  470 +
  471 + rate = clk_get_rate(dsim->clk_pllref) / 1000;
  472 + if (unlikely(!rate)) {
  473 + dev_err(dev, "failed to get pll ref clock rate\n");
  474 + return -EINVAL;
  475 + }
  476 +
  477 + if (rate != dsim->pref_clk) {
  478 + if (unlikely(dsim->pref_clk == PHY_REF_CLK)) {
  479 + /* set default rate failed */
  480 + dev_err(dev, "no valid pll ref clock rate\n");
  481 + return -EINVAL;
  482 + }
  483 +
  484 + dev_warn(dev, "invalid assigned rate for pref: %uKHz\n",
  485 + dsim->pref_clk);
  486 + dev_warn(dev, "use default pref rate instead: %uKHz\n",
  487 + PHY_REF_CLK);
  488 +
  489 + dsim->pref_clk = PHY_REF_CLK;
  490 + goto set_rate;
  491 + }
  492 +
  493 + return 0;
  494 +}
  495 +
443 496 static const struct dsim_pll_pms *sec_mipi_dsim_get_pms(uint32_t bit_clk)
444 497 {
445 498 int i;
... ... @@ -1160,7 +1213,7 @@
1160 1213 if (WARN_ON(!pms))
1161 1214 return -EINVAL;
1162 1215  
1163   - ref_clk = PHY_REF_CLK / 1000;
  1216 + ref_clk = PHY_REF_CLK;
1164 1217 /* TODO: add PMS calculate and check
1165 1218 * Only support '1080p@60Hz' for now,
1166 1219 * add other modes support later
... ... @@ -1714,8 +1767,8 @@
1714 1767  
1715 1768 dev_info(dev, "version number is %#x\n", version);
1716 1769  
1717   - /* TODO: set pll ref clock rate to be fixed with 27MHz */
1718   - ret = clk_set_rate(dsim->clk_pllref, PHY_REF_CLK);
  1770 + /* set suitable rate for phy ref clock */
  1771 + ret = sec_mipi_dsim_set_pref_rate(dsim);
1719 1772 if (ret) {
1720 1773 dev_err(dev, "failed to set pll ref clock rate\n");
1721 1774 return ret;