Eric Lee / smarc-fsl-linux-kernel

Download as
Browse Code ยป

Commit a14a26aca610bbd09fb62fb9fd5dbf6b41321972

Authored by Ben Dooks
Committed by Russell King
1 parent 3ec20520dd

[ARM] 4515/1: S3C: Move uncompress code to plat-s3c 

Move the uncompress.h to plat-s3c

Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Showing 2 changed files with 166 additions and 131 deletions Side-by-side Diff

include/asm-arm/arch-s3c2410/uncompress.h
Diff comments   View file @ a14a26a
... ... @@ -13,154 +13,34 @@
13 13 #ifndef __ASM_ARCH_UNCOMPRESS_H
14 14 #define __ASM_ARCH_UNCOMPRESS_H
15 15  
16   -typedef unsigned int upf_t; /* cannot include linux/serial_core.h */
17   -
18   -/* defines for UART registers */
19   -#include "asm/plat-s3c/regs-serial.h"
20   -#include "asm/arch/regs-gpio.h"
21   -#include "asm/plat-s3c/regs-watchdog.h"
22   -
  16 +#include <asm/arch/regs-gpio.h>
23 17 #include <asm/arch/map.h>
24 18  
25 19 /* working in physical space... */
26 20 #undef S3C2410_GPIOREG
27   -#undef S3C2410_WDOGREG
28   -
29 21 #define S3C2410_GPIOREG(x) ((S3C24XX_PA_GPIO + (x)))
30   -#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
31 22  
  23 +#include <asm/plat-s3c/uncompress.h>
  24 +
32 25 /* how many bytes we allow into the FIFO at a time in FIFO mode */
33 26 #define FIFO_MAX (14)
34 27  
35   -#define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C_LOWLEVEL_UART_PORT)
36   -
37   -static __inline__ void
38   -uart_wr(unsigned int reg, unsigned int val)
  28 +static void arch_detect_cpu(void)
39 29 {
40   - volatile unsigned int *ptr;
  30 + unsigned int cpuid;
41 31  
42   - ptr = (volatile unsigned int *)(reg + uart_base);
43   - *ptr = val;
44   -}
45   -
46   -static __inline__ unsigned int
47   -uart_rd(unsigned int reg)
48   -{
49   - volatile unsigned int *ptr;
50   -
51   - ptr = (volatile unsigned int *)(reg + uart_base);
52   - return *ptr;
53   -}
54   -
55   -
56   -/* we can deal with the case the UARTs are being run
57   - * in FIFO mode, so that we don't hold up our execution
58   - * waiting for tx to happen...
59   -*/
60   -
61   -static void putc(int ch)
62   -{
63   - int cpuid = S3C2410_GSTATUS1_2410;
64   -
65   -#ifndef CONFIG_CPU_S3C2400
66 32 cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1);
67 33 cpuid &= S3C2410_GSTATUS1_IDMASK;
68   -#endif
69 34  
70   - if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
71   - int level;
72   -
73   - while (1) {
74   - level = uart_rd(S3C2410_UFSTAT);
75   -
76   - if (cpuid == S3C2410_GSTATUS1_2440 ||
77   - cpuid == S3C2410_GSTATUS1_2442) {
78   - level &= S3C2440_UFSTAT_TXMASK;
79   - level >>= S3C2440_UFSTAT_TXSHIFT;
80   - } else {
81   - level &= S3C2410_UFSTAT_TXMASK;
82   - level >>= S3C2410_UFSTAT_TXSHIFT;
83   - }
84   -
85   - if (level < FIFO_MAX)
86   - break;
87   - }
88   -
  35 + if (cpuid == S3C2410_GSTATUS1_2440 ||
  36 + cpuid == S3C2410_GSTATUS1_2442) {
  37 + fifo_mask = S3C2440_UFSTAT_TXMASK;
  38 + fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
89 39 } else {
90   - /* not using fifos */
91   -
92   - while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
93   - barrier();
  40 + fifo_mask = S3C2410_UFSTAT_TXMASK;
  41 + fifo_max = 15 << S3C2410_UFSTAT_TXSHIFT;
94 42 }
95   -
96   - /* write byte to transmission register */
97   - uart_wr(S3C2410_UTXH, ch);
98 43 }
99   -
100   -static inline void flush(void)
101   -{
102   -}
103   -
104   -#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)
105   -
106   -/* CONFIG_S3C2410_BOOT_WATCHDOG
107   - *
108   - * Simple boot-time watchdog setup, to reboot the system if there is
109   - * any problem with the boot process
110   -*/
111   -
112   -#ifdef CONFIG_S3C2410_BOOT_WATCHDOG
113   -
114   -#define WDOG_COUNT (0xff00)
115   -
116   -static inline void arch_decomp_wdog(void)
117   -{
118   - __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
119   -}
120   -
121   -static void arch_decomp_wdog_start(void)
122   -{
123   - __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
124   - __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
125   - __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
126   -}
127   -
128   -#else
129   -#define arch_decomp_wdog_start()
130   -#define arch_decomp_wdog()
131   -#endif
132   -
133   -#ifdef CONFIG_S3C2410_BOOT_ERROR_RESET
134   -
135   -static void arch_decomp_error(const char *x)
136   -{
137   - putstr("\n\n");
138   - putstr(x);
139   - putstr("\n\n -- System resetting\n");
140   -
141   - __raw_writel(0x4000, S3C2410_WTDAT);
142   - __raw_writel(0x4000, S3C2410_WTCNT);
143   - __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
144   -
145   - while(1);
146   -}
147   -
148   -#define arch_error arch_decomp_error
149   -#endif
150   -
151   -static void error(char *err);
152   -
153   -static void
154   -arch_decomp_setup(void)
155   -{
156   - /* we may need to setup the uart(s) here if we are not running
157   - * on an BAST... the BAST will have left the uarts configured
158   - * after calling linux.
159   - */
160   -
161   - arch_decomp_wdog_start();
162   -}
163   -
164 44  
165 45 #endif /* __ASM_ARCH_UNCOMPRESS_H */
include/asm-arm/plat-s3c/uncompress.h
Diff comments   View file @ a14a26a
  1 +/* linux/include/asm-arm/plat-s3c/uncompress.h
  2 + *
  3 + * Copyright 2003, 2007 Simtec Electronics
  4 + * http://armlinux.simtec.co.uk/
  5 + * Ben Dooks <ben@simtec.co.uk>
  6 + *
  7 + * S3C - uncompress code
  8 + *
  9 + * This program is free software; you can redistribute it and/or modify
  10 + * it under the terms of the GNU General Public License version 2 as
  11 + * published by the Free Software Foundation.
  12 +*/
  13 +
  14 +#ifndef __ASM_PLAT_UNCOMPRESS_H
  15 +#define __ASM_PLAT_UNCOMPRESS_H
  16 +
  17 +typedef unsigned int upf_t; /* cannot include linux/serial_core.h */
  18 +
  19 +/* uart setup */
  20 +
  21 +static unsigned int fifo_mask;
  22 +static unsigned int fifo_max;
  23 +
  24 +/* forward declerations */
  25 +
  26 +static void arch_detect_cpu(void);
  27 +
  28 +/* defines for UART registers */
  29 +
  30 +#include "asm/plat-s3c/regs-serial.h"
  31 +#include "asm/plat-s3c/regs-watchdog.h"
  32 +
  33 +/* working in physical space... */
  34 +#undef S3C2410_WDOGREG
  35 +#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
  36 +
  37 +/* how many bytes we allow into the FIFO at a time in FIFO mode */
  38 +#define FIFO_MAX (14)
  39 +
  40 +#define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C_LOWLEVEL_UART_PORT)
  41 +
  42 +static __inline__ void
  43 +uart_wr(unsigned int reg, unsigned int val)
  44 +{
  45 + volatile unsigned int *ptr;
  46 +
  47 + ptr = (volatile unsigned int *)(reg + uart_base);
  48 + *ptr = val;
  49 +}
  50 +
  51 +static __inline__ unsigned int
  52 +uart_rd(unsigned int reg)
  53 +{
  54 + volatile unsigned int *ptr;
  55 +
  56 + ptr = (volatile unsigned int *)(reg + uart_base);
  57 + return *ptr;
  58 +}
  59 +
  60 +/* we can deal with the case the UARTs are being run
  61 + * in FIFO mode, so that we don't hold up our execution
  62 + * waiting for tx to happen...
  63 +*/
  64 +
  65 +static void putc(int ch)
  66 +{
  67 + if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
  68 + int level;
  69 +
  70 + while (1) {
  71 + level = uart_rd(S3C2410_UFSTAT);
  72 + level &= fifo_mask;
  73 +
  74 + if (level < fifo_max)
  75 + break;
  76 + }
  77 +
  78 + } else {
  79 + /* not using fifos */
  80 +
  81 + while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
  82 + barrier();
  83 + }
  84 +
  85 + /* write byte to transmission register */
  86 + uart_wr(S3C2410_UTXH, ch);
  87 +}
  88 +
  89 +static inline void flush(void)
  90 +{
  91 +}
  92 +
  93 +#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)
  94 +
  95 +/* CONFIG_S3C2410_BOOT_WATCHDOG
  96 + *
  97 + * Simple boot-time watchdog setup, to reboot the system if there is
  98 + * any problem with the boot process
  99 +*/
  100 +
  101 +#ifdef CONFIG_S3C2410_BOOT_WATCHDOG
  102 +
  103 +#define WDOG_COUNT (0xff00)
  104 +
  105 +static inline void arch_decomp_wdog(void)
  106 +{
  107 + __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
  108 +}
  109 +
  110 +static void arch_decomp_wdog_start(void)
  111 +{
  112 + __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
  113 + __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
  114 + __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
  115 +}
  116 +
  117 +#else
  118 +#define arch_decomp_wdog_start()
  119 +#define arch_decomp_wdog()
  120 +#endif
  121 +
  122 +#ifdef CONFIG_S3C2410_BOOT_ERROR_RESET
  123 +
  124 +static void arch_decomp_error(const char *x)
  125 +{
  126 + putstr("\n\n");
  127 + putstr(x);
  128 + putstr("\n\n -- System resetting\n");
  129 +
  130 + __raw_writel(0x4000, S3C2410_WTDAT);
  131 + __raw_writel(0x4000, S3C2410_WTCNT);
  132 + __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
  133 +
  134 + while(1);
  135 +}
  136 +
  137 +#define arch_error arch_decomp_error
  138 +#endif
  139 +
  140 +static void error(char *err);
  141 +
  142 +static void
  143 +arch_decomp_setup(void)
  144 +{
  145 + /* we may need to setup the uart(s) here if we are not running
  146 + * on an BAST... the BAST will have left the uarts configured
  147 + * after calling linux.
  148 + */
  149 +
  150 + arch_detect_cpu();
  151 + arch_decomp_wdog_start();
  152 +}
  153 +
  154 +
  155 +#endif /* __ASM_PLAT_UNCOMPRESS_H */