Eric Lee / smarc-fsl-linux-kernel

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Commit a2a47ca36642e3995e982957bc42678cf11ca6ac

Authored by Rob Herring
1 parent 6f6f6a7029

ARM: __io abuse cleanup 

Several platforms incorrectly use __io() for casting to 'void __iomem *'.
This converts all of those uses to use the common IOMEM macro.

Reported-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Anton Vorontsov <cbouatmailru@gmail.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-sh@vger.kernel.org
Acked-by: Arnd Bergmann <arnd@arndb.de>

Showing 14 changed files with 36 additions and 36 deletions Side-by-side Diff

arch/arm/mach-cns3xxx/core.c
Diff comments   View file @ a2a47ca
... ... @@ -72,13 +72,13 @@
72 72 /* used by entry-macro.S */
73 73 void __init cns3xxx_init_irq(void)
74 74 {
75   - gic_init(0, 29, __io(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT),
76   - __io(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT));
  75 + gic_init(0, 29, IOMEM(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT),
  76 + IOMEM(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT));
77 77 }
78 78  
79 79 void cns3xxx_power_off(void)
80 80 {
81   - u32 __iomem *pm_base = __io(CNS3XXX_PM_BASE_VIRT);
  81 + u32 __iomem *pm_base = IOMEM(CNS3XXX_PM_BASE_VIRT);
82 82 u32 clkctrl;
83 83  
84 84 printk(KERN_INFO "powering system down...\n");
... ... @@ -237,7 +237,7 @@
237 237  
238 238 static void __init cns3xxx_timer_init(void)
239 239 {
240   - cns3xxx_tmr1 = __io(CNS3XXX_TIMER1_2_3_BASE_VIRT);
  240 + cns3xxx_tmr1 = IOMEM(CNS3XXX_TIMER1_2_3_BASE_VIRT);
241 241  
242 242 __cns3xxx_timer_init(IRQ_CNS3XXX_TIMER0);
243 243 }
arch/arm/mach-cns3xxx/devices.c
Diff comments   View file @ a2a47ca
... ... @@ -98,7 +98,7 @@
98 98  
99 99 void __init cns3xxx_sdhci_init(void)
100 100 {
101   - u32 __iomem *gpioa = __io(CNS3XXX_MISC_BASE_VIRT + 0x0014);
  101 + u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014);
102 102 u32 gpioa_pins = __raw_readl(gpioa);
103 103  
104 104 /* MMC/SD pins share with GPIOA */
arch/arm/mach-netx/generic.c
Diff comments   View file @ a2a47ca
... ... @@ -168,7 +168,7 @@
168 168 {
169 169 int irq;
170 170  
171   - vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0, 0);
  171 + vic_init(io_p2v(NETX_PA_VIC), 0, ~0, 0);
172 172  
173 173 for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) {
174 174 irq_set_chip_and_handler(irq, &netx_hif_chip,
arch/arm/mach-netx/include/mach/hardware.h
Diff comments   View file @ a2a47ca
... ... @@ -33,7 +33,7 @@
33 33 #define XMAC_MEM_SIZE 0x1000
34 34 #define SRAM_MEM_SIZE 0x8000
35 35  
36   -#define io_p2v(x) ((x) - NETX_IO_PHYS + NETX_IO_VIRT)
  36 +#define io_p2v(x) IOMEM((x) - NETX_IO_PHYS + NETX_IO_VIRT)
37 37 #define io_v2p(x) ((x) - NETX_IO_VIRT + NETX_IO_PHYS)
38 38  
39 39 #endif
arch/arm/mach-netx/include/mach/netx-regs.h
Diff comments   View file @ a2a47ca
... ... @@ -115,7 +115,7 @@
115 115 *********************************/
116 116  
117 117 /* Registers */
118   -#define NETX_SYSTEM_REG(ofs) __io(NETX_VA_SYSTEM + (ofs))
  118 +#define NETX_SYSTEM_REG(ofs) IOMEM(NETX_VA_SYSTEM + (ofs))
119 119 #define NETX_SYSTEM_BOO_SR NETX_SYSTEM_REG(0x00)
120 120 #define NETX_SYSTEM_IOC_CR NETX_SYSTEM_REG(0x04)
121 121 #define NETX_SYSTEM_IOC_MR NETX_SYSTEM_REG(0x08)
... ... @@ -185,7 +185,7 @@
185 185 *******************************/
186 186  
187 187 /* Registers */
188   -#define NETX_GPIO_REG(ofs) __io(NETX_VA_GPIO + (ofs))
  188 +#define NETX_GPIO_REG(ofs) IOMEM(NETX_VA_GPIO + (ofs))
189 189 #define NETX_GPIO_CFG(gpio) NETX_GPIO_REG(0x0 + ((gpio)<<2))
190 190 #define NETX_GPIO_THRESHOLD_CAPTURE(gpio) NETX_GPIO_REG(0x40 + ((gpio)<<2))
191 191 #define NETX_GPIO_COUNTER_CTRL(counter) NETX_GPIO_REG(0x80 + ((counter)<<2))
... ... @@ -230,7 +230,7 @@
230 230 *******************************/
231 231  
232 232 /* Registers */
233   -#define NETX_PIO_REG(ofs) __io(NETX_VA_PIO + (ofs))
  233 +#define NETX_PIO_REG(ofs) IOMEM(NETX_VA_PIO + (ofs))
234 234 #define NETX_PIO_INPIO NETX_PIO_REG(0x0)
235 235 #define NETX_PIO_OUTPIO NETX_PIO_REG(0x4)
236 236 #define NETX_PIO_OEPIO NETX_PIO_REG(0x8)
... ... @@ -240,7 +240,7 @@
240 240 *******************************/
241 241  
242 242 /* Registers */
243   -#define NETX_MIIMU __io(NETX_VA_MIIMU)
  243 +#define NETX_MIIMU IOMEM(NETX_VA_MIIMU)
244 244  
245 245 /* Bits */
246 246 #define MIIMU_SNRDY (1<<0)
... ... @@ -317,7 +317,7 @@
317 317 *******************************/
318 318  
319 319 /* Registers */
320   -#define NETX_PFIFO_REG(ofs) __io(NETX_VA_PFIFO + (ofs))
  320 +#define NETX_PFIFO_REG(ofs) IOMEM(NETX_VA_PFIFO + (ofs))
321 321 #define NETX_PFIFO_BASE(pfifo) NETX_PFIFO_REG(0x00 + ((pfifo)<<2))
322 322 #define NETX_PFIFO_BORDER_BASE(pfifo) NETX_PFIFO_REG(0x80 + ((pfifo)<<2))
323 323 #define NETX_PFIFO_RESET NETX_PFIFO_REG(0x100)
... ... @@ -334,7 +334,7 @@
334 334 *******************************/
335 335  
336 336 /* Registers */
337   -#define NETX_MEMCR_REG(ofs) __io(NETX_VA_MEMCR + (ofs))
  337 +#define NETX_MEMCR_REG(ofs) IOMEM(NETX_VA_MEMCR + (ofs))
338 338 #define NETX_MEMCR_SRAM_CTRL(cs) NETX_MEMCR_REG(0x0 + 4 * (cs)) /* SRAM for CS 0..2 */
339 339 #define NETX_MEMCR_SDRAM_CFG_CTRL NETX_MEMCR_REG(0x40)
340 340 #define NETX_MEMCR_SDRAM_TIMING_CTRL NETX_MEMCR_REG(0x44)
... ... @@ -355,7 +355,7 @@
355 355 *******************************/
356 356  
357 357 /* Registers */
358   -#define NETX_DPMAS_REG(ofs) __io(NETX_VA_DPMAS + (ofs))
  358 +#define NETX_DPMAS_REG(ofs) IOMEM(NETX_VA_DPMAS + (ofs))
359 359 #define NETX_DPMAS_SYS_STAT NETX_DPMAS_REG(0x4d8)
360 360 #define NETX_DPMAS_INT_STAT NETX_DPMAS_REG(0x4e0)
361 361 #define NETX_DPMAS_INT_EN NETX_DPMAS_REG(0x4f0)
... ... @@ -425,7 +425,7 @@
425 425 /*******************************
426 426 * I2C *
427 427 *******************************/
428   -#define NETX_I2C_REG(ofs) __io(NETX_VA_I2C, (ofs))
  428 +#define NETX_I2C_REG(ofs) IOMEM(NETX_VA_I2C, (ofs))
429 429 #define NETX_I2C_CTRL NETX_I2C_REG(0x0)
430 430 #define NETX_I2C_DATA NETX_I2C_REG(0x4)
431 431  
arch/arm/mach-realview/include/mach/hardware.h
Diff comments   View file @ a2a47ca
... ... @@ -37,7 +37,7 @@
37 37 #else
38 38 #define IO_ADDRESS(x) (x)
39 39 #endif
40   -#define __io_address(n) __io(IO_ADDRESS(n))
  40 +#define __io_address(n) IOMEM(IO_ADDRESS(n))
41 41  
42 42 #endif
arch/arm/mach-shmobile/board-ag5evm.c
Diff comments   View file @ a2a47ca
... ... @@ -615,7 +615,7 @@
615 615  
616 616 #ifdef CONFIG_CACHE_L2X0
617 617 /* Shared attribute override enable, 64K*8way */
618   - l2x0_init(__io(0xf0100000), 0x00460000, 0xc2000fff);
  618 + l2x0_init(IOMEM(0xf0100000), 0x00460000, 0xc2000fff);
619 619 #endif
620 620 sh73a0_add_standard_devices();
621 621 platform_add_devices(ag5evm_devices, ARRAY_SIZE(ag5evm_devices));
arch/arm/mach-shmobile/board-bonito.c
Diff comments   View file @ a2a47ca
... ... @@ -394,7 +394,7 @@
394 394  
395 395 #ifdef CONFIG_CACHE_L2X0
396 396 /* Early BRESP enable, Shared attribute override enable, 32K*8way */
397   - l2x0_init(__io(0xf0002000), 0x40440000, 0x82000fff);
  397 + l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
398 398 #endif
399 399  
400 400 r8a7740_add_standard_devices();
arch/arm/mach-shmobile/board-kota2.c
Diff comments   View file @ a2a47ca
... ... @@ -530,7 +530,7 @@
530 530  
531 531 #ifdef CONFIG_CACHE_L2X0
532 532 /* Early BRESP enable, Shared attribute override enable, 64K*8way */
533   - l2x0_init(__io(0xf0100000), 0x40460000, 0x82000fff);
  533 + l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
534 534 #endif
535 535 sh73a0_add_standard_devices();
536 536 platform_add_devices(kota2_devices, ARRAY_SIZE(kota2_devices));
arch/arm/mach-shmobile/intc-r8a7779.c
Diff comments   View file @ a2a47ca
... ... @@ -42,8 +42,8 @@
42 42  
43 43 void __init r8a7779_init_irq(void)
44 44 {
45   - void __iomem *gic_dist_base = __io(0xf0001000);
46   - void __iomem *gic_cpu_base = __io(0xf0000100);
  45 + void __iomem *gic_dist_base = IOMEM(0xf0001000);
  46 + void __iomem *gic_cpu_base = IOMEM(0xf0000100);
47 47  
48 48 /* use GIC to handle interrupts */
49 49 gic_init(0, 29, gic_dist_base, gic_cpu_base);
arch/arm/mach-shmobile/intc-sh73a0.c
Diff comments   View file @ a2a47ca
... ... @@ -419,8 +419,8 @@
419 419  
420 420 void __init sh73a0_init_irq(void)
421 421 {
422   - void __iomem *gic_dist_base = __io(0xf0001000);
423   - void __iomem *gic_cpu_base = __io(0xf0000100);
  422 + void __iomem *gic_dist_base = IOMEM(0xf0001000);
  423 + void __iomem *gic_cpu_base = IOMEM(0xf0000100);
424 424 void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
425 425 int k, n;
426 426  
arch/arm/mach-shmobile/smp-r8a7779.c
Diff comments   View file @ a2a47ca
... ... @@ -30,7 +30,7 @@
30 30 #include <asm/smp_twd.h>
31 31 #include <asm/hardware/gic.h>
32 32  
33   -#define AVECR 0xfe700040
  33 +#define AVECR IOMEM(0xfe700040)
34 34  
35 35 static struct r8a7779_pm_ch r8a7779_ch_cpu1 = {
36 36 .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
... ... @@ -140,7 +140,7 @@
140 140 scu_enable(scu_base_addr());
141 141  
142 142 /* Map the reset vector (in headsmp.S) */
143   - __raw_writel(__pa(shmobile_secondary_vector), __io(AVECR));
  143 + __raw_writel(__pa(shmobile_secondary_vector), AVECR);
144 144  
145 145 /* enable cache coherency on CPU0 */
146 146 modify_scu_cpu_psr(0, 3 << (cpu * 8));
arch/arm/mach-shmobile/smp-sh73a0.c
Diff comments   View file @ a2a47ca
... ... @@ -28,11 +28,11 @@
28 28 #include <asm/smp_twd.h>
29 29 #include <asm/hardware/gic.h>
30 30  
31   -#define WUPCR 0xe6151010
32   -#define SRESCR 0xe6151018
33   -#define PSTR 0xe6151040
34   -#define SBAR 0xe6180020
35   -#define APARMBAREA 0xe6f10020
  31 +#define WUPCR IOMEM(0xe6151010)
  32 +#define SRESCR IOMEM(0xe6151018)
  33 +#define PSTR IOMEM(0xe6151040)
  34 +#define SBAR IOMEM(0xe6180020)
  35 +#define APARMBAREA IOMEM(0xe6f10020)
36 36  
37 37 static void __iomem *scu_base_addr(void)
38 38 {
39 39  
... ... @@ -80,10 +80,10 @@
80 80 /* enable cache coherency */
81 81 modify_scu_cpu_psr(0, 3 << (cpu * 8));
82 82  
83   - if (((__raw_readw(__io(PSTR)) >> (4 * cpu)) & 3) == 3)
84   - __raw_writel(1 << cpu, __io(WUPCR)); /* wake up */
  83 + if (((__raw_readw(PSTR) >> (4 * cpu)) & 3) == 3)
  84 + __raw_writel(1 << cpu, WUPCR); /* wake up */
85 85 else
86   - __raw_writel(1 << cpu, __io(SRESCR)); /* reset */
  86 + __raw_writel(1 << cpu, SRESCR); /* reset */
87 87  
88 88 return 0;
89 89 }
... ... @@ -95,8 +95,8 @@
95 95 scu_enable(scu_base_addr());
96 96  
97 97 /* Map the reset vector (in headsmp.S) */
98   - __raw_writel(0, __io(APARMBAREA)); /* 4k */
99   - __raw_writel(__pa(shmobile_secondary_vector), __io(SBAR));
  98 + __raw_writel(0, APARMBAREA); /* 4k */
  99 + __raw_writel(__pa(shmobile_secondary_vector), SBAR);
100 100  
101 101 /* enable cache coherency on CPU0 */
102 102 modify_scu_cpu_psr(0, 3 << (cpu * 8));
arch/arm/mach-ux500/include/mach/hardware.h
Diff comments   View file @ a2a47ca
... ... @@ -23,7 +23,7 @@
23 23 (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL)
24 24  
25 25 /* typesafe io address */
26   -#define __io_address(n) __io(IO_ADDRESS(n))
  26 +#define __io_address(n) IOMEM(IO_ADDRESS(n))
27 27 /* Used by some plat-nomadik code */
28 28 #define io_p2v(n) __io_address(n)
29 29