Commit a7aea373b4ca428f1be2c1fedd2f26c8e3f2864d

Authored by Ira W. Snyder
Committed by Dan Williams
1 parent 07a2039b8e

fsldma: use PCI Read Multiple command

By default, the Freescale 83xx DMA controller uses the PCI Read Line
command when reading data over the PCI bus. Setting the controller to use
the PCI Read Multiple command instead allows the controller to read much
larger bursts of data, which provides a drastic speed increase.

The slowdown due to using PCI Read Line was only observed when a PCI-to-PCI
bridge was between the devices trying to communicate.

A simple test driver showed an increase from 4MB/sec to 116MB/sec when
performing DMA over the PCI bus. Using DMA to transfer between blocks of
local SDRAM showed no change in performance with this patch. The dmatest
driver was also used to verify the correctness of the transfers, and showed
no errors.

Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Acked-by: Timur Tabi <timur@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>

Showing 2 changed files with 9 additions and 2 deletions Side-by-side Diff

drivers/dma/fsldma.c
... ... @@ -12,6 +12,11 @@
12 12 * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc.
13 13 * The support for MPC8349 DMA contorller is also added.
14 14 *
  15 + * This driver instructs the DMA controller to issue the PCI Read Multiple
  16 + * command for PCI read operations, instead of using the default PCI Read Line
  17 + * command. Please be aware that this setting may result in read pre-fetching
  18 + * on some platforms.
  19 + *
15 20 * This is free software; you can redistribute it and/or modify
16 21 * it under the terms of the GNU General Public License as published by
17 22 * the Free Software Foundation; either version 2 of the License, or
18 23  
... ... @@ -49,9 +54,10 @@
49 54 case FSL_DMA_IP_83XX:
50 55 /* Set the channel to below modes:
51 56 * EOTIE - End-of-transfer interrupt enable
  57 + * PRC_RM - PCI read multiple
52 58 */
53   - DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EOTIE,
54   - 32);
  59 + DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EOTIE
  60 + | FSL_DMA_MR_PRC_RM, 32);
55 61 break;
56 62 }
57 63  
drivers/dma/fsldma.h
... ... @@ -38,6 +38,7 @@
38 38  
39 39 /* Special MR definition for MPC8349 */
40 40 #define FSL_DMA_MR_EOTIE 0x00000080
  41 +#define FSL_DMA_MR_PRC_RM 0x00000800
41 42  
42 43 #define FSL_DMA_SR_CH 0x00000020
43 44 #define FSL_DMA_SR_PE 0x00000010