Merge branch 'lpc32xx/drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/…

…arm/arm-soc into lpc32xx/tmp Conflicts: arch/arm/mach-lpc32xx/clock.c

Merge branch 'lpc32xx/drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/…
…arm/arm-soc into lpc32xx/tmp Conflicts: arch/arm/mach-lpc32xx/clock.c
Roland Stigge
2 parents 73d43d0064 678a0222ed
Showing 4 changed files Side-by-side Diff
arch/arm/mach-lpc32xx/clock.c
arch/arm/mach-lpc32xx/common.c
arch/arm/mach-lpc32xx/common.h
arch/arm/mach-lpc32xx/phy3250.c
@@ -721,6 +721,41 @@
 	.get_rate	= local_return_parent_rate,
 };
  
+static int adc_onoff_enable(struct clk *clk, int enable)
+{
+	u32 tmp;
+	u32 divider;
+
+	/* Use PERIPH_CLOCK */
+	tmp = __raw_readl(LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
+	tmp |= LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL;
+	/*
+	 * Set clock divider so that we have equal to or less than
+	 * 4.5MHz clock at ADC
+	 */
+	divider = clk->get_rate(clk) / 4500000 + 1;
+	tmp |= divider;
+	__raw_writel(tmp, LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
+
+	/* synchronize rate of this clock w/ actual HW setting */
+	clk->rate = clk->get_rate(clk->parent) / divider;
+
+	if (enable == 0)
+		__raw_writel(0, clk->enable_reg);
+	else
+		__raw_writel(clk->enable_mask, clk->enable_reg);
+
+	return 0;
+}
+
+static struct clk clk_adc = {
+	.parent		= &clk_pclk,
+	.enable		= adc_onoff_enable,
+	.enable_reg	= LPC32XX_CLKPWR_ADC_CLK_CTRL,
+	.enable_mask	= LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN,
+	.get_rate	= local_return_parent_rate,
+};
+
 static int mmc_onoff_enable(struct clk *clk, int enable)
 {
 	u32 tmp;
@@ -1057,6 +1092,7 @@
 	_REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand)
 	_REGISTER_CLOCK(NULL, "i2s0_ck", clk_i2s0)
 	_REGISTER_CLOCK(NULL, "i2s1_ck", clk_i2s1)
+	_REGISTER_CLOCK("lpc32xx-adc", NULL, clk_adc)
 	_REGISTER_CLOCK("ts-lpc32xx", NULL, clk_tsc)
 	_REGISTER_CLOCK("dev:mmc0", NULL, clk_mmc)
 	_REGISTER_CLOCK("lpc-net.0", NULL, clk_net)
@@ -138,6 +138,28 @@
 };
  
 /*
+ * ADC support
+ */
+static struct resource adc_resources[] = {
+	{
+		.start = LPC32XX_ADC_BASE,
+		.end = LPC32XX_ADC_BASE + SZ_4K - 1,
+		.flags = IORESOURCE_MEM,
+	}, {
+		.start = IRQ_LPC32XX_TS_IRQ,
+		.end = IRQ_LPC32XX_TS_IRQ,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device lpc32xx_adc_device = {
+	.name =  "lpc32xx-adc",
+	.id = -1,
+	.num_resources = ARRAY_SIZE(adc_resources),
+	.resource = adc_resources,
+};
+
+/*
  * Returns the unique ID for the device
  */
 void lpc32xx_get_uid(u32 devid[4])
@@ -29,6 +29,7 @@
 extern struct platform_device lpc32xx_i2c1_device;
 extern struct platform_device lpc32xx_i2c2_device;
 extern struct platform_device lpc32xx_tsc_device;
+extern struct platform_device lpc32xx_adc_device;
 extern struct platform_device lpc32xx_rtc_device;
  
 /*
@@ -278,6 +278,7 @@
 	&lpc32xx_i2c2_device,
 	&lpc32xx_watchdog_device,
 	&lpc32xx_gpio_led_device,
+	&lpc32xx_adc_device,
 };
  
 static struct amba_device *amba_devs[] __initdata = {
...	...	@@ -721,6 +721,41 @@
721	721	.get_rate = local_return_parent_rate,
722	722	};
723	723
	724	+static int adc_onoff_enable(struct clk *clk, int enable)
	725	+{
	726	+ u32 tmp;
	727	+ u32 divider;
	728	+
	729	+ /* Use PERIPH_CLOCK */
	730	+ tmp = __raw_readl(LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
	731	+ tmp \|= LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL;
	732	+ /*
	733	+ * Set clock divider so that we have equal to or less than
	734	+ * 4.5MHz clock at ADC
	735	+ */
	736	+ divider = clk->get_rate(clk) / 4500000 + 1;
	737	+ tmp \|= divider;
	738	+ __raw_writel(tmp, LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
	739	+
	740	+ /* synchronize rate of this clock w/ actual HW setting */
	741	+ clk->rate = clk->get_rate(clk->parent) / divider;
	742	+
	743	+ if (enable == 0)
	744	+ __raw_writel(0, clk->enable_reg);
	745	+ else
	746	+ __raw_writel(clk->enable_mask, clk->enable_reg);
	747	+
	748	+ return 0;
	749	+}
	750	+
	751	+static struct clk clk_adc = {
	752	+ .parent = &clk_pclk,
	753	+ .enable = adc_onoff_enable,
	754	+ .enable_reg = LPC32XX_CLKPWR_ADC_CLK_CTRL,
	755	+ .enable_mask = LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN,
	756	+ .get_rate = local_return_parent_rate,
	757	+};
	758	+
724	759	static int mmc_onoff_enable(struct clk *clk, int enable)
725	760	{
726	761	u32 tmp;
...	...	@@ -1057,6 +1092,7 @@
1057	1092	_REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand)
1058	1093	_REGISTER_CLOCK(NULL, "i2s0_ck", clk_i2s0)
1059	1094	_REGISTER_CLOCK(NULL, "i2s1_ck", clk_i2s1)
	1095	+ _REGISTER_CLOCK("lpc32xx-adc", NULL, clk_adc)
1060	1096	_REGISTER_CLOCK("ts-lpc32xx", NULL, clk_tsc)
1061	1097	_REGISTER_CLOCK("dev:mmc0", NULL, clk_mmc)
1062	1098	_REGISTER_CLOCK("lpc-net.0", NULL, clk_net)
...	...	@@ -138,6 +138,28 @@
138	138	};
139	139
140	140	/*
	141	+ * ADC support
	142	+ */
	143	+static struct resource adc_resources[] = {
	144	+ {
	145	+ .start = LPC32XX_ADC_BASE,
	146	+ .end = LPC32XX_ADC_BASE + SZ_4K - 1,
	147	+ .flags = IORESOURCE_MEM,
	148	+ }, {
	149	+ .start = IRQ_LPC32XX_TS_IRQ,
	150	+ .end = IRQ_LPC32XX_TS_IRQ,
	151	+ .flags = IORESOURCE_IRQ,
	152	+ },
	153	+};
	154	+
	155	+struct platform_device lpc32xx_adc_device = {
	156	+ .name = "lpc32xx-adc",
	157	+ .id = -1,
	158	+ .num_resources = ARRAY_SIZE(adc_resources),
	159	+ .resource = adc_resources,
	160	+};
	161	+
	162	+/*
141	163	* Returns the unique ID for the device
142	164	*/
143	165	void lpc32xx_get_uid(u32 devid[4])
...	...	@@ -29,6 +29,7 @@
29	29	extern struct platform_device lpc32xx_i2c1_device;
30	30	extern struct platform_device lpc32xx_i2c2_device;
31	31	extern struct platform_device lpc32xx_tsc_device;
	32	+extern struct platform_device lpc32xx_adc_device;
32	33	extern struct platform_device lpc32xx_rtc_device;
33	34
34	35	/*
...	...	@@ -278,6 +278,7 @@
278	278	&lpc32xx_i2c2_device,
279	279	&lpc32xx_watchdog_device,
280	280	&lpc32xx_gpio_led_device,
	281	+ &lpc32xx_adc_device,
281	282	};
282	283
283	284	static struct amba_device *amba_devs[] __initdata = {