[POWERPC] Spelling fixes: arch/ppc/

Spelling fixes in arch/ppc/. Signed-off-by: Simon Arlott <simon@fire.lp0.eu> Signed-off-by: Paul Mackerras <paulus@samba.org>

[POWERPC] Spelling fixes: arch/ppc/
Spelling fixes in arch/ppc/. Signed-off-by: Simon Arlott <simon@fire.lp0.eu> Signed-off-by: Paul Mackerras <paulus@samba.org>
Simon Arlott · Paul Mackerras
1 parent dab4d7984e
Showing 40 changed files with 67 additions and 67 deletions Side-by-side Diff
arch/ppc/4xx_io/serial_sicc.c
arch/ppc/8xx_io/commproc.c
arch/ppc/8xx_io/fec.c
arch/ppc/boot/lib/vreset.c
arch/ppc/boot/simple/m8xx_tty.c
arch/ppc/boot/simple/misc-embedded.c
arch/ppc/boot/simple/mpc52xx_tty.c
arch/ppc/boot/simple/mv64x60_tty.c
arch/ppc/boot/simple/rw4/stb.h
arch/ppc/kernel/traps.c
arch/ppc/mm/init.c
arch/ppc/platforms/4xx/bubinga.c
arch/ppc/platforms/4xx/ep405.c
arch/ppc/platforms/4xx/ibmnp405h.h
arch/ppc/platforms/4xx/sycamore.c
arch/ppc/platforms/4xx/walnut.c
arch/ppc/platforms/ev64360.c
arch/ppc/platforms/hdpu.c
arch/ppc/platforms/katana.c
arch/ppc/platforms/mbx.h
@@ -3,7 +3,7 @@
  *
  *  Based on drivers/char/serial_amba.c, by ARM Ltd.
  *
- *  Copyright 2001 IBM Crop.
+ *  Copyright 2001 IBM Corp.
  *  Author: IBM China Research Lab
  *            Yudong Yang <yangyud@cn.ibm.com>
  *            Yi Ge       <geyi@cn.ibm.com>
  
@@ -155,16 +155,16 @@
  
 /* serial port transmit command register */
  
-#define _TxCR_ET_MASK   0x80           /* transmiter enable mask */
+#define _TxCR_ET_MASK   0x80           /* transmitter enable mask */
 #define _TxCR_DME_MASK  0x60           /* dma mode mask */
 #define _TxCR_TIE_MASK  0x10           /* empty interrupt enable mask */
 #define _TxCR_EIE_MASK  0x08           /* error interrupt enable mask */
 #define _TxCR_SPE_MASK  0x04           /* stop/pause mask */
 #define _TxCR_TB_MASK   0x02           /* transmit break mask */
  
-#define _TxCR_ET_ENABLE _TxCR_ET_MASK  /* transmiter enabled */
-#define _TxCR_DME_DISABLE 0x00         /* transmiter disabled, TBR intr disabled */
-#define _TxCR_DME_TBR   0x20           /* transmiter disabled, TBR intr enabled */
+#define _TxCR_ET_ENABLE _TxCR_ET_MASK  /* transmitter enabled */
+#define _TxCR_DME_DISABLE 0x00         /* transmitter disabled, TBR intr disabled */
+#define _TxCR_DME_TBR   0x20           /* transmitter disabled, TBR intr enabled */
 #define _TxCR_DME_CHAN_2 0x40          /* dma enabled, destination chann 2 */
 #define _TxCR_DME_CHAN_3 0x60          /* dma enabled, destination chann 3 */
  
@@ -144,7 +144,7 @@
  
 	/* Set SDMA Bus Request priority 5.
 	 * On 860T, this also enables FEC priority 6.  I am not sure
-	 * this is what we realy want for some applications, but the
+	 * this is what we really want for some applications, but the
 	 * manual recommends it.
 	 * Bit 25, FAM can also be set to use FEC aggressive mode (860T).
 	 */
@@ -1878,7 +1878,7 @@
 	bdp--;
 	bdp->cbd_sc |= BD_SC_WRAP;
  
-	/* ...and the same for transmmit.
+	/* ...and the same for transmit.
 	*/
 	bdp = fep->tx_bd_base;
 	for (i=0; i<TX_RING_SIZE; i++) {
@@ -518,7 +518,7 @@
 	outb(0x3c6, 0xff);  /* MASK */
  
 	for ( i = 0; i < 0x10; i++)
-		writeAttr(i, AC[i], 0);  /* pallete */
+		writeAttr(i, AC[i], 0);  /* palette */
 	writeAttr(0x10, 0x0c, 0);    /* text mode */
 	writeAttr(0x11, 0x00, 0);    /* overscan color (border) */
 	writeAttr(0x12, 0x0f, 0);    /* plane enable */
 /* Minimal serial functions needed to send messages out the serial
  * port on the MBX console.
  *
- * The MBX uxes SMC1 for the serial port.  We reset the port and use
+ * The MBX uses SMC1 for the serial port.  We reset the port and use
  * only the first BD that EPPC-Bug set up as a character FIFO.
  *
  * Later versions (at least 1.4, maybe earlier) of the MBX EPPC-Bug
@@ -136,7 +136,7 @@
  
 	/*
 	 * We link ourself to an arbitrary low address.  When we run, we
-	 * relocate outself to that address.  __image_being points to
+	 * relocate ourself to that address.  __image_being points to
 	 * the part of the image where the zImage is. -- Tom
 	 */
 	zimage_start = (char *)(unsigned long)(&__image_begin);
@@ -33,7 +33,7 @@
  * rtc.  We read the decrementer change during one rtc tick
  * and multiply by 4 to get the system bus clock frequency. Since a
  * rtc tick is one seconds, and that's pretty long, we change the rtc
- * dividers temporarly to set them 64x faster ;)
+ * dividers temporarily to set them 64x faster ;)
  */
 static int
 mpc52xx_ipbfreq(void)
@@ -338,7 +338,7 @@
  
 	rdp = &rd[com_port][cur_rd[com_port]];
  
-	/* Go thru rcv desc's until empty looking for one with data (no error)*/
+	/* Go through rcv descs until empty looking for one with data (no error)*/
 	while (((rdp->cmd_stat & SDMA_DESC_CMDSTAT_O) == 0) &&
 		(loop_count++ < RX_NUM_DESC)) {
  
@@ -88,7 +88,7 @@
 /*----------------------------------------------------------------------------+
 | STB tasks, task stack sizes, and task priorities.  The actual task priority
 | is 1 more than the specified number since priority 0 is reserved (system
-| internaly adds 1 to supplied priority number).
+| internally adds 1 to supplied priority number).
 +----------------------------------------------------------------------------*/
 #define STB_IDLE_TASK_SS        (5* 1024)
 #define STB_IDLE_TASK_PRIO      0
@@ -577,7 +577,7 @@
 	 * ESR_DST (!?) or 0.  In the process of chasing this with the
 	 * hardware people - not sure if it can happen on any illegal
 	 * instruction or only on FP instructions, whether there is a
-	 * pattern to occurences etc. -dgibson 31/Mar/2003 */
+	 * pattern to occurrences etc. -dgibson 31/Mar/2003 */
 	if (!(reason & REASON_TRAP) && do_mathemu(regs) == 0) {
 		emulate_single_step(regs);
 		return;
@@ -860,7 +860,7 @@
 	spefscr = current->thread.spefscr;
 	fpexc_mode = current->thread.fpexc_mode;
  
-	/* Hardware does not neccessarily set sticky
+	/* Hardware does not necessarily set sticky
 	 * underflow/overflow/invalid flags */
 	if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
 		code = FPE_FLTOVF;
@@ -48,7 +48,7 @@
 #include "mmu_decl.h"
  
 #if defined(CONFIG_KERNEL_START_BOOL) || defined(CONFIG_LOWMEM_SIZE_BOOL)
-/* The ammount of lowmem must be within 0xF0000000 - KERNELBASE. */
+/* The amount of lowmem must be within 0xF0000000 - KERNELBASE. */
 #if (CONFIG_LOWMEM_SIZE > (0xF0000000 - KERNELBASE))
 #error "You must adjust CONFIG_LOWMEM_SIZE or CONFIG_START_KERNEL"
 #endif
@@ -197,7 +197,7 @@
 		    hose->first_busno, PCI_SLOT(hose->first_busno),
 		    PCI_FUNC(hose->first_busno), bar, bar_response);
 	}
-	/* end work arround */
+	/* end workaround */
  
 #ifdef DEBUG
 	printk("PCI bridge regs after fixup \n");
@@ -130,7 +130,7 @@
 		    hose->first_busno, PCI_SLOT(hose->first_busno),
 		    PCI_FUNC(hose->first_busno), bar, bar_response);
 	}
-	/* end work arround */
+	/* end workaround */
 #endif
 }
  
@@ -80,7 +80,7 @@
 #define DCRN_CPMFR_BASE	0x0B9
 #define DCRN_CPMER_BASE	0x0B8
  
-/* CPM Clocking & Power Mangement defines */
+/* CPM Clocking & Power Management defines */
 #define IBM_CPM_PCI		0x40000000	/* PCI */
 #define IBM_CPM_EMAC2	0x20000000	/* EMAC 2 MII */
 #define IBM_CPM_EMAC3	0x04000000	/* EMAC 3 MII */
@@ -225,7 +225,7 @@
 		    hose->first_busno, PCI_SLOT(hose->first_busno),
 		    PCI_FUNC(hose->first_busno), bar, bar_response);
 	}
-	/* end work arround */
+	/* end workaround */
  
 #ifdef DEBUG
 	printk("PCI bridge regs after fixup \n");
@@ -200,7 +200,7 @@
 		    hose->first_busno, PCI_SLOT(hose->first_busno),
 		    PCI_FUNC(hose->first_busno), bar, bar_response);
 	}
-	/* end work arround */
+	/* end work around */
  
 #ifdef DEBUG
 	printk("PCI bridge regs after fixup \n");
@@ -473,7 +473,7 @@
 	 * are non-zero, then we should use the board info from the bd_t
 	 * structure and the cmdline pointed to by r6 instead of the
 	 * information from birecs, if any.  Otherwise, use the information
-	 * from birecs as discovered by the preceeding call to
+	 * from birecs as discovered by the preceding call to
 	 * parse_bootinfo().  This rule should work with both PPCBoot, which
 	 * uses a bd_t board info structure, and the kernel boot wrapper,
 	 * which uses birecs.
@@ -144,7 +144,7 @@
  
 	/* Enable pipelining */
 	mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1 << 13));
-	/* Enable Snoop Pipelineing */
+	/* Enable Snoop Pipelining */
 	mv64x60_set_bits(&bh, MV64360_D_UNIT_CONTROL_HIGH, (1 << 24));
  
 	/*
@@ -880,7 +880,7 @@
 	 * are non-zero, then we should use the board info from the bd_t
 	 * structure and the cmdline pointed to by r6 instead of the
 	 * information from birecs, if any.  Otherwise, use the information
-	 * from birecs as discovered by the preceeding call to
+	 * from birecs as discovered by the preceding call to
 	 * parse_bootinfo().  This rule should work with both PPCBoot, which
 	 * uses a bd_t board info structure, and the kernel boot wrapper,
 	 * which uses birecs.
@@ -37,7 +37,7 @@
  
 /* Memory map for the MBX as configured by EPPC-Bug.  We could reprogram
  * The SIU and PCI bridge, and try to use larger MMU pages, but the
- * performance gain is not measureable and it certainly complicates the
+ * performance gain is not measurable and it certainly complicates the
  * generic MMU model.
  *
  * In a effort to minimize memory usage for embedded applications, any
@@ -69,7 +69,7 @@
  
 #define STD_COM_FLAGS ASYNC_BOOT_AUTOCONF
  
-/* All UART IRQ's are wire-OR'd to one MPIC IRQ */
+/* All UART IRQs are wire-OR'd to one MPIC IRQ */
 #define STD_SERIAL_PORT_DFNS \
         { 0, BASE_BAUD, MVME5100_SERIAL_1, \
 		MVME5100_SERIAL_IRQ, \
@@ -18,7 +18,7 @@
 #include <asm/io.h>
  
 /*
- * Due to limiations imposed by legacy hardware (primaryily IDE controllers),
+ * Due to limitations imposed by legacy hardware (primarily IDE controllers),
  * the PPLUS boards operate using a PReP address map.
  *
  * From Processor (physical) -> PCI:
@@ -589,9 +589,9 @@
 	{ 4, 1, 2, 3},  /* Buses 3, 7, 11 ... */
 };
  
-/* We have to turn on LEVEL mode for changed IRQ's */
-/* All PCI IRQ's need to be level mode, so this should be something
- * other than hard-coded as well... IRQ's are individually mappable
+/* We have to turn on LEVEL mode for changed IRQs */
+/* All PCI IRQs need to be level mode, so this should be something
+ * other than hard-coded as well... IRQs are individually mappable
  * to either edge or level.
  */
  
@@ -923,8 +923,8 @@
 	Motherboard_map_name = "IBM 6015/7020 (Sandalfoot/Sandalbow)";
 	Motherboard_map = ibm6015_pci_IRQ_map;
 	Motherboard_routes = ibm6015_pci_IRQ_routes;
-	*irq_edge_mask_lo = 0x00; /* irq's 0-7 all edge-triggered */
-	*irq_edge_mask_hi = 0xA0; /* irq's 13, 15 level-triggered */
+	*irq_edge_mask_lo = 0x00; /* IRQs 0-7 all edge-triggered */
+	*irq_edge_mask_hi = 0xA0; /* IRQs 13, 15 level-triggered */
 }
  
 void __init
@@ -933,8 +933,8 @@
 	Motherboard_map_name = "IBM Thinkpad 850/860";
 	Motherboard_map = Nobis_pci_IRQ_map;
 	Motherboard_routes = Nobis_pci_IRQ_routes;
-	*irq_edge_mask_lo = 0x00; /* irq's 0-7 all edge-triggered */
-	*irq_edge_mask_hi = 0xA0; /* irq's 13, 15 level-triggered */
+	*irq_edge_mask_lo = 0x00; /* IRQs 0-7 all edge-triggered */
+	*irq_edge_mask_hi = 0xA0; /* IRQs 13, 15 level-triggered */
 }
  
 void __init
@@ -943,8 +943,8 @@
 	Motherboard_map_name = "IBM 7248, PowerSeries 830/850 (Carolina)";
 	Motherboard_map = ibm8xx_pci_IRQ_map;
 	Motherboard_routes = ibm8xx_pci_IRQ_routes;
-	*irq_edge_mask_lo = 0x00; /* irq's 0-7 all edge-triggered */
-	*irq_edge_mask_hi = 0xA4; /* irq's 10, 13, 15 level-triggered */
+	*irq_edge_mask_lo = 0x00; /* IRQs 0-7 all edge-triggered */
+	*irq_edge_mask_hi = 0xA4; /* IRQs 10, 13, 15 level-triggered */
 }
  
 void __init
@@ -954,8 +954,8 @@
 	Motherboard_map = ibm43p_pci_IRQ_map;
 	Motherboard_routes = ibm43p_pci_IRQ_routes;
 	Motherboard_non0 = ibm43p_pci_map_non0;
-	*irq_edge_mask_lo = 0x00; /* irq's 0-7 all edge-triggered */
-	*irq_edge_mask_hi = 0xA0; /* irq's 13, 15 level-triggered */
+	*irq_edge_mask_lo = 0x00; /* IRQs 0-7 all edge-triggered */
+	*irq_edge_mask_hi = 0xA0; /* IRQs 13, 15 level-triggered */
 }
  
 void __init
@@ -593,7 +593,7 @@
 	PPC_DEVICE *audiodevice = NULL;
  
 	/*
-	 * Get the needed resource informations from residual data.
+	 * Get the needed resource information from residual data.
 	 *
 	 */
 	if (have_residual_data)
  
@@ -632,9 +632,9 @@
 	}
  
 	/*
-	 * Find a way to push these informations to the cs4232 driver
+	 * Find a way to push this information to the cs4232 driver
 	 * Give it out with printk, when not in cmd_line?
-	 * Append it to  cmd_line and boot_command_line?
+	 * Append it to cmd_line and boot_command_line?
 	 * Format is cs4232=io,irq,dma,dma2
 	 */
 }
@@ -16,7 +16,7 @@
 #define __ASM_PRPMC750_H__
  
 /*
- * Due to limiations imposed by legacy hardware (primaryily IDE controllers),
+ * Due to limitations imposed by legacy hardware (primarily IDE controllers),
  * the PrPMC750 carrier board operates using a PReP address map.
  *
  * From Processor (physical) -> PCI:
@@ -1371,7 +1371,7 @@
 	 * are non-zero, then we should use the board info from the bd_t
 	 * structure and the cmdline pointed to by r6 instead of the
 	 * information from birecs, if any.  Otherwise, use the information
-	 * from birecs as discovered by the preceeding call to
+	 * from birecs as discovered by the preceding call to
 	 * parse_bootinfo().  This rule should work with both PPCBoot, which
 	 * uses a bd_t board info structure, and the kernel boot wrapper,
 	 * which uses birecs.
@@ -54,7 +54,7 @@
  *
  *
  * Motorola has finally released a version of DINK32 that correctly
- * (seemingly) initalizes the memory controller correctly, regardless
+ * (seemingly) initializes the memory controller correctly, regardless
  * of the amount of memory in the system.  Once a method of determining
  * what version of DINK initializes the system for us, if applicable, is
  * found, we can hopefully stop hardcoding 32MB of RAM.
@@ -473,7 +473,7 @@
 arch_initcall(sandpoint_request_io);
  
 /*
- * Interrupt setup and service.  Interrrupts on the Sandpoint come
+ * Interrupt setup and service.  Interrupts on the Sandpoint come
  * from the four PCI slots plus the 8259 in the Winbond Super I/O (SIO).
  * The 8259 is cascaded from EPIC IRQ0, IRQ1-4 map to PCI slots 1-4,
  * IDE is on EPIC 7 and 8.
@@ -505,7 +505,7 @@
 	if (bp->bi_memsize)
 		return bp->bi_memsize;
  
-	/* DINK32 13.0 correctly initalizes things, so iff you use
+	/* DINK32 13.0 correctly initializes things, so iff you use
 	 * this you _should_ be able to change this instead of a
 	 * hardcoded value. */
 #if 0
@@ -677,7 +677,7 @@
 	 * are non-zero, then we should use the board info from the bd_t
 	 * structure and the cmdline pointed to by r6 instead of the
 	 * information from birecs, if any.  Otherwise, use the information
-	 * from birecs as discovered by the preceeding call to
+	 * from birecs as discovered by the preceding call to
 	 * parse_bootinfo().  This rule should work with both PPCBoot, which
 	 * uses a bd_t board info structure, and the kernel boot wrapper,
 	 * which uses birecs.
@@ -210,7 +210,7 @@
  * This assumes that PPCBug has initialized the memory controller (SMC)
  * on the Harrier correctly (i.e., it does no sanity checking).
  * It also assumes that the memory base registers are set to configure the
- * memory as contigous starting with "RAM A BASE", "RAM B BASE", etc.
+ * memory as contiguous starting with "RAM A BASE", "RAM B BASE", etc.
  * however, RAM base registers can be skipped (e.g. A, B, C are set,
  * D is skipped but E is set is okay).
  */
@@ -165,7 +165,7 @@
 				 processor_pci_mem_start + 
 				 hose->mem_space.start) | 0x0);
  
-	/* Map MPIC into vitual memory */
+	/* Map MPIC into virtual memory */
 	OpenPIC_Addr = ioremap(processor_mpic_base, HAWK_MPIC_SIZE);
  
 	return 0;
@@ -176,7 +176,7 @@
  * This assumes that PPCBug has initialized the memory controller (SMC)
  * on the Falcon/HAWK correctly (i.e., it does no sanity checking).
  * It also assumes that the memory base registers are set to configure the
- * memory as contigous starting with "RAM A BASE", "RAM B BASE", etc.
+ * memory as contiguous starting with "RAM A BASE", "RAM B BASE", etc.
  * however, RAM base registers can be skipped (e.g. A, B, C are set,
  * D is skipped but E is set is okay).
  */
@@ -197,7 +197,7 @@
 	   CPM high      	0b0000
 	   CPM middle           0b0001
 	   CPM low       	0b0010
-	   PCI reguest          0b0011
+	   PCI request          0b0011
 	   Reserved      	0b0100
 	   Reserved      	0b0101
 	   Internal Core     	0b0110
@@ -432,7 +432,7 @@
 			phys_eumb_base);
 	}
  
-	/* IRQ's are determined at runtime */
+	/* IRQs are determined at runtime */
 	ppc_sys_platform_devices[MPC10X_IIC1].resource[1].start = MPC10X_I2C_IRQ;
 	ppc_sys_platform_devices[MPC10X_IIC1].resource[1].end = MPC10X_I2C_IRQ;
 	ppc_sys_platform_devices[MPC10X_DMA0].resource[1].start = MPC10X_DMA0_IRQ;
@@ -646,7 +646,7 @@
 	openpic_set_sources(EPIC_IRQ_BASE, 3, OpenPIC_Addr + 0x11020);
 	/* Skip reserved space and map Message Unit Interrupt (I2O) */
 	openpic_set_sources(EPIC_IRQ_BASE + 3, 1, OpenPIC_Addr + 0x110C0);
-	/* Skip reserved space and map Serial Interupts */
+	/* Skip reserved space and map Serial Interrupts */
 	openpic_set_sources(EPIC_IRQ_BASE + 4, 2, OpenPIC_Addr + 0x11120);
  
 	openpic_init(NUM_8259_INTERRUPTS);
@@ -252,7 +252,7 @@
 	out_be32(&xlb->snoop_window, MPC52xx_PCI_TARGET_MEM | 0x1d);
  
 	/* Disable XLB pipelining */
-	/* (cfr errate 292. We could do this only just before ATA PIO
+	/* (cfr errata 292. We could do this only just before ATA PIO
 	    transaction and re-enable it after ...) */
 	out_be32(&xlb->config, in_be32(&xlb->config) | MPC52xx_XLB_CFG_PLDIS);
  
@@ -21,7 +21,7 @@
 #include <asm/irq.h>
 #include <asm/ppc_sys.h>
  
-/* We use offsets for IORESOURCE_MEM to do not set dependences at compile time.
+/* We use offsets for IORESOURCE_MEM to do not set dependencies at compile time.
  * They will get fixed up by mach_mpc8xx_fixup
  */
  
@@ -490,7 +490,7 @@
 /*
  * mv64x60_init()
  *
- * Initialze the bridge based on setting passed in via 'si'.  The bridge
+ * Initialize the bridge based on setting passed in via 'si'.  The bridge
  * handle, 'bh', will be set so that it can be used to make subsequent
  * calls to routines in this file.
  */
@@ -1704,7 +1704,7 @@
 /*
  * gt64260a_chip_specific_init()
  *
- * Implement errata work arounds for the GT64260A.
+ * Implement errata workarounds for the GT64260A.
  */
 static void __init
 gt64260a_chip_specific_init(struct mv64x60_handle *bh,
@@ -1776,7 +1776,7 @@
 /*
  * gt64260b_chip_specific_init()
  *
- * Implement errata work arounds for the GT64260B.
+ * Implement errata workarounds for the GT64260B.
  */
 static void __init
 gt64260b_chip_specific_init(struct mv64x60_handle *bh,
@@ -2316,7 +2316,7 @@
 /*
  * mv64360_chip_specific_init()
  *
- * Implement errata work arounds for the MV64360.
+ * Implement errata workarounds for the MV64360.
  */
 static void __init
 mv64360_chip_specific_init(struct mv64x60_handle *bh,
@@ -2336,7 +2336,7 @@
 /*
  * mv64460_chip_specific_init()
  *
- * Implement errata work arounds for the MV64460.
+ * Implement errata workarounds for the MV64460.
  */
 static void __init
 mv64460_chip_specific_init(struct mv64x60_handle *bh,
@@ -27,7 +27,7 @@
  *  device model.  The devices on the OCP bus are seeded by an
  *  an initial OCP device array created by the arch-specific
  *  Device entries can be added/removed/modified through OCP
- *  helper functions to accomodate system and  board-specific
+ *  helper functions to accommodate system and  board-specific
  *  parameters commonly found in embedded systems. OCP also
  *  provides a standard method for devices to describe extended
  *  attributes about themselves to the system.  A standard access
@@ -112,7 +112,7 @@
  
 	/*
 	 * Disable all external interrupts until they are
-	 * explicity requested.
+	 * explicitly requested.
 	 */
 	ppc_cached_irq_mask[0] = 0;
  
@@ -137,7 +137,7 @@
 	hose_a->pci_mem_offset = 0;
  
 	/* Setup bridge memory/IO ranges & resources
-	 * TODO: Handle firmwares setting up a legacy ISA mem base
+	 * TODO: Handle firmware setting up a legacy ISA mem base
 	 */
 	hose_a->io_space.start = PPC405_PCI_LOWER_IO;
 	hose_a->io_space.end = PPC405_PCI_UPPER_IO;
@@ -241,7 +241,7 @@
 }
  
 /*
- *   Returns the number of bytes left to be transfered.
+ *   Returns the number of bytes left to be transferred.
  *   After a DMA transfer, this should return zero.
  *   Reading this while a DMA transfer is still in progress will return
  *   unpredictable results.
@@ -349,7 +349,7 @@
  * @dev_instance: Pointer to interrupt-specific data
  *
  * Handles outbound message interrupts. Executes a register outbound
- * mailbox event handler and acks the interrupt occurence.
+ * mailbox event handler and acks the interrupt occurrence.
  */
 static irqreturn_t
 mpc85xx_rio_tx_handler(int irq, void *dev_instance)
@@ -516,7 +516,7 @@
  * @dev_instance: Pointer to interrupt-specific data
  *
  * Handles inbound message interrupts. Executes a registered inbound
- * mailbox event handler and acks the interrupt occurence.
+ * mailbox event handler and acks the interrupt occurrence.
  */
 static irqreturn_t
 mpc85xx_rio_rx_handler(int irq, void *dev_instance)
@@ -130,7 +130,7 @@
  
 	/*
 	 * Disable all external interrupts until they are
-	 * explicity requested.
+	 * explicitly requested.
 	 */
 	intc_out_be32(intc + IER, 0);
...	...	@@ -3,7 +3,7 @@
3	3	*
4	4	* Based on drivers/char/serial_amba.c, by ARM Ltd.
5	5	*
6		- * Copyright 2001 IBM Crop.
	6	+ * Copyright 2001 IBM Corp.
7	7	* Author: IBM China Research Lab
8	8	* Yudong Yang <yangyud@cn.ibm.com>
9	9	* Yi Ge <geyi@cn.ibm.com>
10	10
...	...	@@ -155,16 +155,16 @@
155	155
156	156	/* serial port transmit command register */
157	157
158		-#define _TxCR_ET_MASK 0x80 /* transmiter enable mask */
	158	+#define _TxCR_ET_MASK 0x80 /* transmitter enable mask */
159	159	#define _TxCR_DME_MASK 0x60 /* dma mode mask */
160	160	#define _TxCR_TIE_MASK 0x10 /* empty interrupt enable mask */
161	161	#define _TxCR_EIE_MASK 0x08 /* error interrupt enable mask */
162	162	#define _TxCR_SPE_MASK 0x04 /* stop/pause mask */
163	163	#define _TxCR_TB_MASK 0x02 /* transmit break mask */
164	164
165		-#define _TxCR_ET_ENABLE _TxCR_ET_MASK /* transmiter enabled */
166		-#define _TxCR_DME_DISABLE 0x00 /* transmiter disabled, TBR intr disabled */
167		-#define _TxCR_DME_TBR 0x20 /* transmiter disabled, TBR intr enabled */
	165	+#define _TxCR_ET_ENABLE _TxCR_ET_MASK /* transmitter enabled */
	166	+#define _TxCR_DME_DISABLE 0x00 /* transmitter disabled, TBR intr disabled */
	167	+#define _TxCR_DME_TBR 0x20 /* transmitter disabled, TBR intr enabled */
168	168	#define _TxCR_DME_CHAN_2 0x40 /* dma enabled, destination chann 2 */
169	169	#define _TxCR_DME_CHAN_3 0x60 /* dma enabled, destination chann 3 */
170	170
...	...	@@ -144,7 +144,7 @@
144	144
145	145	/* Set SDMA Bus Request priority 5.
146	146	* On 860T, this also enables FEC priority 6. I am not sure
147		- * this is what we realy want for some applications, but the
	147	+ * this is what we really want for some applications, but the
148	148	* manual recommends it.
149	149	* Bit 25, FAM can also be set to use FEC aggressive mode (860T).
150	150	*/
...	...	@@ -1878,7 +1878,7 @@
1878	1878	bdp--;
1879	1879	bdp->cbd_sc \|= BD_SC_WRAP;
1880	1880
1881		- /* ...and the same for transmmit.
	1881	+ /* ...and the same for transmit.
1882	1882	*/
1883	1883	bdp = fep->tx_bd_base;
1884	1884	for (i=0; i<TX_RING_SIZE; i++) {
...	...	@@ -518,7 +518,7 @@
518	518	outb(0x3c6, 0xff); /* MASK */
519	519
520	520	for ( i = 0; i < 0x10; i++)
521		- writeAttr(i, AC[i], 0); /* pallete */
	521	+ writeAttr(i, AC[i], 0); /* palette */
522	522	writeAttr(0x10, 0x0c, 0); /* text mode */
523	523	writeAttr(0x11, 0x00, 0); /* overscan color (border) */
524	524	writeAttr(0x12, 0x0f, 0); /* plane enable */
1	1	/* Minimal serial functions needed to send messages out the serial
2	2	* port on the MBX console.
3	3	*
4		- * The MBX uxes SMC1 for the serial port. We reset the port and use
	4	+ * The MBX uses SMC1 for the serial port. We reset the port and use
5	5	* only the first BD that EPPC-Bug set up as a character FIFO.
6	6	*
7	7	* Later versions (at least 1.4, maybe earlier) of the MBX EPPC-Bug
...	...	@@ -136,7 +136,7 @@
136	136
137	137	/*
138	138	* We link ourself to an arbitrary low address. When we run, we
139		- * relocate outself to that address. __image_being points to
	139	+ * relocate ourself to that address. __image_being points to
140	140	* the part of the image where the zImage is. -- Tom
141	141	*/
142	142	zimage_start = (char *)(unsigned long)(&__image_begin);
...	...	@@ -33,7 +33,7 @@
33	33	* rtc. We read the decrementer change during one rtc tick
34	34	* and multiply by 4 to get the system bus clock frequency. Since a
35	35	* rtc tick is one seconds, and that's pretty long, we change the rtc
36		- * dividers temporarly to set them 64x faster ;)
	36	+ * dividers temporarily to set them 64x faster ;)
37	37	*/
38	38	static int
39	39	mpc52xx_ipbfreq(void)
...	...	@@ -338,7 +338,7 @@
338	338
339	339	rdp = &rd[com_port][cur_rd[com_port]];
340	340
341		- /* Go thru rcv desc's until empty looking for one with data (no error)*/
	341	+ /* Go through rcv descs until empty looking for one with data (no error)*/
342	342	while (((rdp->cmd_stat & SDMA_DESC_CMDSTAT_O) == 0) &&
343	343	(loop_count++ < RX_NUM_DESC)) {
344	344
...	...	@@ -88,7 +88,7 @@
88	88	/*----------------------------------------------------------------------------+
89	89	\| STB tasks, task stack sizes, and task priorities. The actual task priority
90	90	\| is 1 more than the specified number since priority 0 is reserved (system
91		-\| internaly adds 1 to supplied priority number).
	91	+\| internally adds 1 to supplied priority number).
92	92	+----------------------------------------------------------------------------*/
93	93	#define STB_IDLE_TASK_SS (5* 1024)
94	94	#define STB_IDLE_TASK_PRIO 0
...	...	@@ -577,7 +577,7 @@
577	577	* ESR_DST (!?) or 0. In the process of chasing this with the
578	578	* hardware people - not sure if it can happen on any illegal
579	579	* instruction or only on FP instructions, whether there is a
580		- * pattern to occurences etc. -dgibson 31/Mar/2003 */
	580	+ * pattern to occurrences etc. -dgibson 31/Mar/2003 */
581	581	if (!(reason & REASON_TRAP) && do_mathemu(regs) == 0) {
582	582	emulate_single_step(regs);
583	583	return;
...	...	@@ -860,7 +860,7 @@
860	860	spefscr = current->thread.spefscr;
861	861	fpexc_mode = current->thread.fpexc_mode;
862	862
863		- /* Hardware does not neccessarily set sticky
	863	+ /* Hardware does not necessarily set sticky
864	864	* underflow/overflow/invalid flags */
865	865	if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
866	866	code = FPE_FLTOVF;