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Commit b0f70292053a0f68f406564a721a7a3f2d66b44f

Authored by Rafał Miłecki
Committed by John W. Linville
1 parent 35b8862369

ssb: SPROM: extract each core power info 

We already extract some basic info but it's incomplete, reads info
about the first core only. Used data structure doesn't allow easy
adding of more cores.
This patch adds new struct and array for storing power info. The plan
is to: switch all extractors (including the ones using NVRAM) to new
struct, switch drivers, then deprecate and finally drop old SSB fields.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

Showing 3 changed files with 81 additions and 1 deletions Side-by-side Diff

... ... @@ -523,7 +523,13 @@
523 523 static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
524 524 {
525 525 int i;
526   - u16 v;
  526 + u16 v, o;
  527 + u16 pwr_info_offset[] = {
  528 + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
  529 + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
  530 + };
  531 + BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
  532 + ARRAY_SIZE(out->core_pwr_info));
527 533  
528 534 /* extract the MAC address */
529 535 for (i = 0; i < 3; i++) {
... ... @@ -606,6 +612,38 @@
606 612 SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
607 613 memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
608 614 sizeof(out->antenna_gain.ghz5));
  615 +
  616 + /* Extract cores power info info */
  617 + for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
  618 + o = pwr_info_offset[i];
  619 + SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
  620 + SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
  621 + SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
  622 + SSB_SPROM8_2G_MAXP, 0);
  623 +
  624 + SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
  625 + SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
  626 + SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
  627 +
  628 + SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
  629 + SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
  630 + SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
  631 + SSB_SPROM8_5G_MAXP, 0);
  632 + SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
  633 + SSB_SPROM8_5GH_MAXP, 0);
  634 + SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
  635 + SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
  636 +
  637 + SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
  638 + SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
  639 + SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
  640 + SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
  641 + SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
  642 + SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
  643 + SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
  644 + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
  645 + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
  646 + }
609 647  
610 648 /* Extract FEM info */
611 649 SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
include/linux/ssb/ssb.h
Diff comments   View file @ b0f7029
... ... @@ -16,6 +16,12 @@
16 16 struct ssb_bus;
17 17 struct ssb_driver;
18 18  
  19 +struct ssb_sprom_core_pwr_info {
  20 + u8 itssi_2g, itssi_5g;
  21 + u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
  22 + u16 pa_2g[3], pa_5gl[3], pa_5g[3], pa_5gh[3];
  23 +};
  24 +
19 25 struct ssb_sprom {
20 26 u8 revision;
21 27 u8 il0mac[6]; /* MAC address for 802.11b/g */
... ... @@ -81,6 +87,8 @@
81 87 u16 boardflags2_lo; /* Board flags (bits 32-47) */
82 88 u16 boardflags2_hi; /* Board flags (bits 48-63) */
83 89 /* TODO store board flags in a single u64 */
  90 +
  91 + struct ssb_sprom_core_pwr_info core_pwr_info[4];
84 92  
85 93 /* Antenna gain values for up to 4 antennas
86 94 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
include/linux/ssb/ssb_regs.h
Diff comments   View file @ b0f7029
... ... @@ -449,6 +449,39 @@
449 449 #define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
450 450 #define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
451 451 #define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
  452 +
  453 +/* There are 4 blocks with power info sharing the same layout */
  454 +#define SSB_SROM8_PWR_INFO_CORE0 0x00C0
  455 +#define SSB_SROM8_PWR_INFO_CORE1 0x00E0
  456 +#define SSB_SROM8_PWR_INFO_CORE2 0x0100
  457 +#define SSB_SROM8_PWR_INFO_CORE3 0x0120
  458 +
  459 +#define SSB_SROM8_2G_MAXP_ITSSI 0x00
  460 +#define SSB_SPROM8_2G_MAXP 0x00FF
  461 +#define SSB_SPROM8_2G_ITSSI 0xFF00
  462 +#define SSB_SPROM8_2G_ITSSI_SHIFT 8
  463 +#define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */
  464 +#define SSB_SROM8_2G_PA_1 0x04
  465 +#define SSB_SROM8_2G_PA_2 0x06
  466 +#define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */
  467 +#define SSB_SPROM8_5G_MAXP 0x00FF
  468 +#define SSB_SPROM8_5G_ITSSI 0xFF00
  469 +#define SSB_SPROM8_5G_ITSSI_SHIFT 8
  470 +#define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */
  471 +#define SSB_SPROM8_5GH_MAXP 0x00FF
  472 +#define SSB_SPROM8_5GL_MAXP 0xFF00
  473 +#define SSB_SPROM8_5GL_MAXP_SHIFT 8
  474 +#define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */
  475 +#define SSB_SROM8_5G_PA_1 0x0E
  476 +#define SSB_SROM8_5G_PA_2 0x10
  477 +#define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */
  478 +#define SSB_SROM8_5GL_PA_1 0x14
  479 +#define SSB_SROM8_5GL_PA_2 0x16
  480 +#define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */
  481 +#define SSB_SROM8_5GH_PA_1 0x1A
  482 +#define SSB_SROM8_5GH_PA_2 0x1C
  483 +
  484 +/* TODO: Make it deprecated */
452 485 #define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
453 486 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
454 487 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
... ... @@ -473,6 +506,7 @@
473 506 #define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
474 507 #define SSB_SPROM8_PA1HIB1 0x00DA
475 508 #define SSB_SPROM8_PA1HIB2 0x00DC
  509 +
476 510 #define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
477 511 #define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
478 512 #define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */