Eric Lee / smarc-fsl-linux-kernel

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Commit b1cffebf1029c87e1f1984d48463ee21093a6bc7

Authored by Rob Herring
1 parent 428fef8ad8

ARM: GIC: remove direct use of gic_raise_softirq 

In preparation of moving gic code to drivers/irqchip, remove the direct
platform dependencies on gic_raise_softirq. Move the setup of
smp_cross_call into the gic code and use arch_send_wakeup_ipi_mask
function to trigger wake-up IPIs.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: David Brown <davidb@codeaurora.org>
Cc: Daniel Walker <dwalker@fifo99.com>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Olof Johansson <olof@lixom.net>

Showing 18 changed files with 33 additions and 57 deletions Side-by-side Diff

arch/arm/common/gic.c
Diff comments   View file @ b1cffeb
... ... @@ -617,6 +617,27 @@
617 617 }
618 618 #endif
619 619  
  620 +#ifdef CONFIG_SMP
  621 +void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
  622 +{
  623 + int cpu;
  624 + unsigned long map = 0;
  625 +
  626 + /* Convert our logical CPU mask into a physical one. */
  627 + for_each_cpu(cpu, mask)
  628 + map |= 1 << cpu_logical_map(cpu);
  629 +
  630 + /*
  631 + * Ensure that stores to Normal memory are visible to the
  632 + * other CPUs before issuing the IPI.
  633 + */
  634 + dsb();
  635 +
  636 + /* this always happens on GIC0 */
  637 + writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
  638 +}
  639 +#endif
  640 +
620 641 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
621 642 irq_hw_number_t hw)
622 643 {
... ... @@ -743,6 +764,9 @@
743 764 if (WARN_ON(!gic->domain))
744 765 return;
745 766  
  767 +#ifdef CONFIG_SMP
  768 + set_smp_cross_call(gic_raise_softirq);
  769 +#endif
746 770 gic_chip.flags |= gic_arch_extn.flags;
747 771 gic_dist_init(gic);
748 772 gic_cpu_init(gic);
... ... @@ -755,27 +779,6 @@
755 779  
756 780 gic_cpu_init(&gic_data[gic_nr]);
757 781 }
758   -
759   -#ifdef CONFIG_SMP
760   -void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
761   -{
762   - int cpu;
763   - unsigned long map = 0;
764   -
765   - /* Convert our logical CPU mask into a physical one. */
766   - for_each_cpu(cpu, mask)
767   - map |= gic_cpu_map[cpu];
768   -
769   - /*
770   - * Ensure that stores to Normal memory are visible to the
771   - * other CPUs before issuing the IPI.
772   - */
773   - dsb();
774   -
775   - /* this always happens on GIC0 */
776   - writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
777   -}
778   -#endif
779 782  
780 783 #ifdef CONFIG_OF
781 784 static int gic_cnt __initdata = 0;
arch/arm/include/asm/hardware/gic.h
Diff comments   View file @ b1cffeb
... ... @@ -40,7 +40,6 @@
40 40 void gic_secondary_init(unsigned int);
41 41 void gic_handle_irq(struct pt_regs *regs);
42 42 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
43   -void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
44 43  
45 44 static inline void gic_init(unsigned int nr, int start,
46 45 void __iomem *dist , void __iomem *cpu)
arch/arm/kernel/smp.c
Diff comments   View file @ b1cffeb
... ... @@ -416,7 +416,8 @@
416 416  
417 417 void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
418 418 {
419   - smp_cross_call = fn;
  419 + if (!smp_cross_call)
  420 + smp_cross_call = fn;
420 421 }
421 422  
422 423 void arch_send_call_function_ipi_mask(const struct cpumask *mask)
arch/arm/mach-exynos/platsmp.c
Diff comments   View file @ b1cffeb
... ... @@ -149,7 +149,7 @@
149 149  
150 150 __raw_writel(virt_to_phys(exynos4_secondary_startup),
151 151 cpu_boot_reg(phys_cpu));
152   - gic_raise_softirq(cpumask_of(cpu), 0);
  152 + arch_send_wakeup_ipi_mask(cpumask_of(cpu));
153 153  
154 154 if (pen_release == -1)
155 155 break;
... ... @@ -190,8 +190,6 @@
190 190  
191 191 for (i = 0; i < ncores; i++)
192 192 set_cpu_possible(i, true);
193   -
194   - set_smp_cross_call(gic_raise_softirq);
195 193 }
196 194  
197 195 static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
arch/arm/mach-highbank/platsmp.c
Diff comments   View file @ b1cffeb
... ... @@ -33,7 +33,7 @@
33 33 static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)
34 34 {
35 35 highbank_set_cpu_jump(cpu, secondary_startup);
36   - gic_raise_softirq(cpumask_of(cpu), 0);
  36 + arch_send_wakeup_ipi_mask(cpumask_of(cpu));
37 37 return 0;
38 38 }
39 39  
... ... @@ -56,8 +56,6 @@
56 56  
57 57 for (i = 0; i < ncores; i++)
58 58 set_cpu_possible(i, true);
59   -
60   - set_smp_cross_call(gic_raise_softirq);
61 59 }
62 60  
63 61 static void __init highbank_smp_prepare_cpus(unsigned int max_cpus)
arch/arm/mach-imx/platsmp.c
Diff comments   View file @ b1cffeb
... ... @@ -71,8 +71,6 @@
71 71  
72 72 for (i = 0; i < ncores; i++)
73 73 set_cpu_possible(i, true);
74   -
75   - set_smp_cross_call(gic_raise_softirq);
76 74 }
77 75  
78 76 void imx_smp_prepare(void)
arch/arm/mach-msm/platsmp.c
Diff comments   View file @ b1cffeb
... ... @@ -115,7 +115,7 @@
115 115 * the boot monitor to read the system wide flags register,
116 116 * and branch to the address found there.
117 117 */
118   - gic_raise_softirq(cpumask_of(cpu), 0);
  118 + arch_send_wakeup_ipi_mask(cpumask_of(cpu));
119 119  
120 120 timeout = jiffies + (1 * HZ);
121 121 while (time_before(jiffies, timeout)) {
... ... @@ -153,8 +153,6 @@
153 153  
154 154 for (i = 0; i < ncores; i++)
155 155 set_cpu_possible(i, true);
156   -
157   - set_smp_cross_call(gic_raise_softirq);
158 156 }
159 157  
160 158 static void __init msm_smp_prepare_cpus(unsigned int max_cpus)
arch/arm/mach-omap2/omap-smp.c
Diff comments   View file @ b1cffeb
... ... @@ -157,7 +157,7 @@
157 157 booted = true;
158 158 }
159 159  
160   - gic_raise_softirq(cpumask_of(cpu), 0);
  160 + arch_send_wakeup_ipi_mask(cpumask_of(cpu));
161 161  
162 162 /*
163 163 * Now the secondary core is starting up let it run its
... ... @@ -231,8 +231,6 @@
231 231  
232 232 for (i = 0; i < ncores; i++)
233 233 set_cpu_possible(i, true);
234   -
235   - set_smp_cross_call(gic_raise_softirq);
236 234 }
237 235  
238 236 static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
arch/arm/mach-realview/platsmp.c
Diff comments   View file @ b1cffeb
... ... @@ -14,7 +14,6 @@
14 14 #include <linux/io.h>
15 15  
16 16 #include <mach/hardware.h>
17   -#include <asm/hardware/gic.h>
18 17 #include <asm/mach-types.h>
19 18 #include <asm/smp_scu.h>
20 19  
... ... @@ -59,8 +58,6 @@
59 58  
60 59 for (i = 0; i < ncores; i++)
61 60 set_cpu_possible(i, true);
62   -
63   - set_smp_cross_call(gic_raise_softirq);
64 61 }
65 62  
66 63 static void __init realview_smp_prepare_cpus(unsigned int max_cpus)
arch/arm/mach-shmobile/platsmp.c
Diff comments   View file @ b1cffeb
... ... @@ -26,7 +26,5 @@
26 26  
27 27 for (i = 0; i < ncores; i++)
28 28 set_cpu_possible(i, true);
29   -
30   - set_smp_cross_call(gic_raise_softirq);
31 29 }
arch/arm/mach-shmobile/smp-emev2.c
Diff comments   View file @ b1cffeb
... ... @@ -100,7 +100,7 @@
100 100 /* Tell ROM loader about our vector (in headsmp.S) */
101 101 emev2_set_boot_vector(__pa(shmobile_secondary_vector));
102 102  
103   - gic_raise_softirq(cpumask_of(cpu), 0);
  103 + arch_send_wakeup_ipi_mask(cpumask_of(cpu));
104 104 return 0;
105 105 }
106 106  
arch/arm/mach-socfpga/platsmp.c
Diff comments   View file @ b1cffeb
... ... @@ -83,8 +83,6 @@
83 83  
84 84 for (i = 0; i < ncores; i++)
85 85 set_cpu_possible(i, true);
86   -
87   - set_smp_cross_call(gic_raise_softirq);
88 86 }
89 87  
90 88 static void __init socfpga_smp_prepare_cpus(unsigned int max_cpus)
arch/arm/mach-spear13xx/platsmp.c
Diff comments   View file @ b1cffeb
... ... @@ -104,8 +104,6 @@
104 104  
105 105 for (i = 0; i < ncores; i++)
106 106 set_cpu_possible(i, true);
107   -
108   - set_smp_cross_call(gic_raise_softirq);
109 107 }
110 108  
111 109 static void __init spear13xx_smp_prepare_cpus(unsigned int max_cpus)
arch/arm/mach-tegra/platsmp.c
Diff comments   View file @ b1cffeb
... ... @@ -159,8 +159,6 @@
159 159  
160 160 for (i = 0; i < ncores; i++)
161 161 set_cpu_possible(i, true);
162   -
163   - set_smp_cross_call(gic_raise_softirq);
164 162 }
165 163  
166 164 static void __init tegra_smp_prepare_cpus(unsigned int max_cpus)
arch/arm/mach-ux500/platsmp.c
Diff comments   View file @ b1cffeb
... ... @@ -91,7 +91,7 @@
91 91 */
92 92 write_pen_release(cpu_logical_map(cpu));
93 93  
94   - gic_raise_softirq(cpumask_of(cpu), 0);
  94 + arch_send_wakeup_ipi_mask(cpumask_of(cpu));
95 95  
96 96 timeout = jiffies + (1 * HZ);
97 97 while (time_before(jiffies, timeout)) {
... ... @@ -155,8 +155,6 @@
155 155  
156 156 for (i = 0; i < ncores; i++)
157 157 set_cpu_possible(i, true);
158   -
159   - set_smp_cross_call(gic_raise_softirq);
160 158 }
161 159  
162 160 static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
arch/arm/mach-vexpress/ct-ca9x4.c
Diff comments   View file @ b1cffeb
... ... @@ -182,8 +182,6 @@
182 182  
183 183 for (i = 0; i < ncores; ++i)
184 184 set_cpu_possible(i, true);
185   -
186   - set_smp_cross_call(gic_raise_softirq);
187 185 }
188 186  
189 187 static void __init ct_ca9x4_smp_enable(unsigned int max_cpus)
arch/arm/mach-vexpress/platsmp.c
Diff comments   View file @ b1cffeb
... ... @@ -128,8 +128,6 @@
128 128  
129 129 for (i = 0; i < ncores; ++i)
130 130 set_cpu_possible(i, true);
131   -
132   - set_smp_cross_call(gic_raise_softirq);
133 131 }
134 132  
135 133 static void __init vexpress_dt_smp_prepare_cpus(unsigned int max_cpus)
arch/arm/plat-versatile/platsmp.c
Diff comments   View file @ b1cffeb
... ... @@ -79,7 +79,7 @@
79 79 * the boot monitor to read the system wide flags register,
80 80 * and branch to the address found there.
81 81 */
82   - gic_raise_softirq(cpumask_of(cpu), 0);
  82 + arch_send_wakeup_ipi_mask(cpumask_of(cpu));
83 83  
84 84 timeout = jiffies + (1 * HZ);
85 85 while (time_before(jiffies, timeout)) {