Commit bebd676186979b874bd801f47f7473f021b535bb

Authored by Eric Lee
1 parent e1a2ce3a20

Add i.MX7 solo core support

Showing 2 changed files with 25 additions and 131 deletions Inline Diff

arch/arm/boot/dts/imx7s-smarcfimx7.dts
1 /* 1 /*
2 * Copyright (C) 2015 Embedian, Inc. 2 * Copyright (C) 2015 Embedian, Inc.
3 * 3 *
4 * This file is dual-licensed: you can use it either under the terms 4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual 5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a 6 * licensing only applies to this file, and not this project as a
7 * whole. 7 * whole.
8 * 8 *
9 * a) This file is free software; you can redistribute it and/or 9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as 10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the 11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version. 12 * License, or (at your option) any later version.
13 * 13 *
14 * This file is distributed in the hope that it will be useful, 14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details. 17 * GNU General Public License for more details.
18 * 18 *
19 * Or, alternatively, 19 * Or, alternatively,
20 * 20 *
21 * b) Permission is hereby granted, free of charge, to any person 21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation 22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without 23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use, 24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or 25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the 26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following 27 * Software is furnished to do so, subject to the following
28 * conditions: 28 * conditions:
29 * 29 *
30 * The above copyright notice and this permission notice shall be 30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software. 31 * included in all copies or substantial portions of the Software.
32 * 32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE. 40 * OTHER DEALINGS IN THE SOFTWARE.
41 */ 41 */
42 42
43 /dts-v1/; 43 /dts-v1/;
44 44
45 #include "imx7solo.dtsi" 45 #include "imx7solo.dtsi"
46 46
47 / { 47 / {
48 model = "Embedian i.MX7S SMARC 2.0 Module"; 48 model = "Embedian i.MX7S SMARC 2.0 Module";
49 compatible = "fsl,imx7s-smarcfimx7", "fsl,imx7s"; 49 compatible = "fsl,imx7s-smarcfimx7", "fsl,imx7s";
50 50
51 memory { 51 memory {
52 reg = <0x80000000 0x40000000>; 52 reg = <0x80000000 0x40000000>;
53 }; 53 };
54 54
55 regulators { 55 regulators {
56 compatible = "simple-bus"; 56 compatible = "simple-bus";
57 #address-cells = <1>; 57 #address-cells = <1>;
58 #size-cells = <0>; 58 #size-cells = <0>;
59 59
60 reg_usb_otg1_vbus: regulator@0 { 60 reg_usb_otg1_vbus: regulator@0 {
61 compatible = "regulator-fixed"; 61 compatible = "regulator-fixed";
62 reg = <0>; 62 reg = <0>;
63 regulator-name = "usb_otg1_vbus"; 63 regulator-name = "usb_otg1_vbus";
64 regulator-min-microvolt = <5000000>; 64 regulator-min-microvolt = <5000000>;
65 regulator-max-microvolt = <5000000>; 65 regulator-max-microvolt = <5000000>;
66 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; 66 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
67 enable-active-high; 67 enable-active-high;
68 }; 68 };
69 69
70 reg_usb_otg2_vbus: regulator@1 { 70 reg_usb_otg2_vbus: regulator@1 {
71 compatible = "regulator-fixed"; 71 compatible = "regulator-fixed";
72 reg = <1>; 72 reg = <1>;
73 regulator-name = "usb_otg2_vbus"; 73 regulator-name = "usb_otg2_vbus";
74 regulator-min-microvolt = <5000000>; 74 regulator-min-microvolt = <5000000>;
75 regulator-max-microvolt = <5000000>; 75 regulator-max-microvolt = <5000000>;
76 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; 76 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
77 enable-active-high; 77 enable-active-high;
78 }; 78 };
79 79
80 reg_sd1_vmmc: regulator@3 { 80 reg_sd1_vmmc: regulator@3 {
81 compatible = "regulator-fixed"; 81 compatible = "regulator-fixed";
82 regulator-name = "VDD_SD1"; 82 regulator-name = "VDD_SD1";
83 regulator-min-microvolt = <3300000>; 83 regulator-min-microvolt = <3300000>;
84 regulator-max-microvolt = <3300000>; 84 regulator-max-microvolt = <3300000>;
85 startup-delay-us = <70000>; 85 startup-delay-us = <70000>;
86 off-on-delay = <20000>; 86 off-on-delay = <20000>;
87 enable-active-high; 87 enable-active-high;
88 }; 88 };
89 89
90 reg_aud_3v3: regulator@4 { 90 reg_aud_3v3: regulator@4 {
91 compatible = "regulator-fixed"; 91 compatible = "regulator-fixed";
92 reg = <4>; 92 reg = <4>;
93 regulator-name = "aud-3v3"; 93 regulator-name = "aud-3v3";
94 regulator-min-microvolt = <3300000>; 94 regulator-min-microvolt = <3300000>;
95 regulator-max-microvolt = <3300000>; 95 regulator-max-microvolt = <3300000>;
96 }; 96 };
97 97
98 reg_vref_1v8: regulator@5 { 98 reg_vref_1v8: regulator@5 {
99 compatible = "regulator-fixed"; 99 compatible = "regulator-fixed";
100 reg = <5>; 100 reg = <5>;
101 regulator-name = "vref-1v8"; 101 regulator-name = "vref-1v8";
102 regulator-min-microvolt = <1800000>; 102 regulator-min-microvolt = <1800000>;
103 regulator-max-microvolt = <1800000>; 103 regulator-max-microvolt = <1800000>;
104 }; 104 };
105 105
106 }; 106 };
107 107
108 backlight { 108 backlight {
109 compatible = "pwm-backlight"; 109 compatible = "pwm-backlight";
110 enable-gpios = <&gpio6 17 GPIO_ACTIVE_HIGH>; /* Backlight Enable Pin*/ 110 enable-gpios = <&gpio6 17 GPIO_ACTIVE_HIGH>; /* Backlight Enable Pin*/
111 pwms = <&pwm2 0 5000000>; 111 pwms = <&pwm2 0 5000000>;
112 brightness-levels = <0 4 8 16 32 64 128 255>; 112 brightness-levels = <0 4 8 16 32 64 128 255>;
113 default-brightness-level = <7>; 113 default-brightness-level = <7>;
114 status = "okay"; 114 status = "okay";
115 }; 115 };
116 116
117 pxp_v4l2_out { 117 pxp_v4l2_out {
118 compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; 118 compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
119 status = "okay"; 119 status = "okay";
120 }; 120 };
121 121
122 sound { 122 sound {
123 compatible = "fsl,imx7d-smarcfimx7-sgtl5000", 123 compatible = "fsl,imx7d-smarcfimx7-sgtl5000",
124 "fsl,imx-audio-sgtl5000"; 124 "fsl,imx-audio-sgtl5000";
125 model = "sgtl5000-audio"; 125 model = "sgtl5000-audio";
126 cpu-dai = <&sai1>; 126 cpu-dai = <&sai1>;
127 audio-codec = <&codec>; 127 audio-codec = <&codec>;
128 codec-master; 128 codec-master;
129 audio-routing = 129 audio-routing =
130 "LINE_IN", "Line In Jack", 130 "LINE_IN", "Line In Jack",
131 "MIC_IN", "Mic Jack", 131 "MIC_IN", "Mic Jack",
132 "Mic Jack", "Mic Bias", 132 "Mic Jack", "Mic Bias",
133 "Headphone Jack", "HP_OUT"; 133 "Headphone Jack", "HP_OUT";
134 }; 134 };
135 }; 135 };
136 136
137 &cpu0 { 137 &cpu0 {
138 arm-supply = <&sw1a_reg>; 138 arm-supply = <&sw1a_reg>;
139 }; 139 };
140 140
141 /* SPI0 */ 141 /* SPI0 */
142 &ecspi1 { 142 &ecspi1 {
143 fsl,spi-num-chipselects = <2>; 143 fsl,spi-num-chipselects = <2>;
144 cs-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>, <&gpio4 0 GPIO_ACTIVE_HIGH>; 144 cs-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>, <&gpio4 0 GPIO_ACTIVE_HIGH>;
145 pinctrl-names = "default"; 145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; 146 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
147 status = "okay"; 147 status = "okay";
148 148
149 spidev1: spidev@0 { 149 spidev1: spidev@0 {
150 compatible = "spidev"; 150 compatible = "spidev";
151 spi-max-frequency = <24000000>; 151 spi-max-frequency = <24000000>;
152 reg = <0>; 152 reg = <0>;
153 }; 153 };
154 spidev2: spidev@1 { 154 spidev2: spidev@1 {
155 compatible = "spidev"; 155 compatible = "spidev";
156 spi-max-frequency = <24000000>; 156 spi-max-frequency = <24000000>;
157 reg = <1>; 157 reg = <1>;
158 }; 158 };
159 }; 159 };
160 160
161 /* SPINOR */ 161 /* SPINOR */
162 &ecspi2 { 162 &ecspi2 {
163 fsl,spi-num-chipselects = <1>; 163 fsl,spi-num-chipselects = <1>;
164 pinctrl-names = "default"; 164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; 165 pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
166 cs-gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; 166 cs-gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>;
167 status = "okay"; 167 status = "okay";
168 168
169 flash: mx25u3235f@0 { 169 flash: mx25u3235f@0 {
170 #address-cells = <1>; 170 #address-cells = <1>;
171 #size-cells = <1>; 171 #size-cells = <1>;
172 compatible = "macronix,mx25u3235f", "jedec,spi-nor"; 172 compatible = "macronix,mx25u3235f", "jedec,spi-nor";
173 spi-max-frequency = <24000000>; 173 spi-max-frequency = <24000000>;
174 reg = <0>; 174 reg = <0>;
175 partition@0 { 175 partition@0 {
176 label = "U-Boot"; 176 label = "U-Boot";
177 reg = <0x0 0x100000>; 177 reg = <0x0 0x100000>;
178 }; 178 };
179 179
180 partition@100000 { 180 partition@100000 {
181 label = "U-Boot Environment"; 181 label = "U-Boot Environment";
182 reg = <0x100000 0x080000>; 182 reg = <0x100000 0x080000>;
183 }; 183 };
184 184
185 partition@180000 { 185 partition@180000 {
186 label = "Flattened Device Tree"; 186 label = "Flattened Device Tree";
187 reg = <0x180000 0x200000>; 187 reg = <0x180000 0x200000>;
188 }; 188 };
189 189
190 }; 190 };
191 }; 191 };
192 192
193 /* ECSPI */ 193 /* ECSPI */
194 &ecspi3 { 194 &ecspi3 {
195 fsl,spi-num-chipselects = <2>; 195 fsl,spi-num-chipselects = <2>;
196 pinctrl-names = "default"; 196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>; 197 pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
198 cs-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>, <&gpio5 9 GPIO_ACTIVE_HIGH>; 198 cs-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>, <&gpio5 9 GPIO_ACTIVE_HIGH>;
199 status = "okay"; 199 status = "okay";
200 200
201 spidev3: spidev@0 { 201 spidev3: spidev@0 {
202 compatible = "spidev"; 202 compatible = "spidev";
203 spi-max-frequency = <24000000>; 203 spi-max-frequency = <24000000>;
204 reg = <0>; 204 reg = <0>;
205 }; 205 };
206 spidev4: spidev@4 { 206 spidev4: spidev@4 {
207 compatible = "spidev"; 207 compatible = "spidev";
208 spi-max-frequency = <24000000>; 208 spi-max-frequency = <24000000>;
209 reg = <1>; 209 reg = <1>;
210 }; 210 };
211 }; 211 };
212 212
213 &clks { 213 &clks {
214 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>; 214 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
215 assigned-clock-rates = <884736000>; 215 assigned-clock-rates = <884736000>;
216 }; 216 };
217 217
218 &csi1 {
219 csi-mux-mipi = <&gpr 0x14 4>;
220 status = "okay";
221
222 port {
223 csi_ep: endpoint {
224 remote-endpoint = <&csi_mipi_ep>;
225 };
226 };
227 };
228
229 &epxp {
230 status = "okay";
231 };
232
233 &fec1 { 218 &fec1 {
234 pinctrl-names = "default"; 219 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_enet1>; 220 pinctrl-0 = <&pinctrl_enet1>;
236 assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_SRC>, 221 assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_SRC>,
237 <&clks IMX7D_ENET_AXI_ROOT_SRC>, 222 <&clks IMX7D_ENET_AXI_ROOT_SRC>,
238 <&clks IMX7D_ENET1_TIME_ROOT_SRC>, 223 <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
239 <&clks IMX7D_ENET1_TIME_ROOT_CLK>, 224 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
240 <&clks IMX7D_ENET_AXI_ROOT_CLK>; 225 <&clks IMX7D_ENET_AXI_ROOT_CLK>;
241 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_25M_CLK>, 226 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_25M_CLK>,
242 <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, 227 <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
243 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; 228 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
244 assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>; 229 assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>;
245 phy-mode = "rgmii-id"; 230 phy-mode = "rgmii-id";
246 phy-handle = <&ethphy0>; 231 phy-handle = <&ethphy0>;
247 fsl,magic-packet; 232 fsl,magic-packet;
248 status = "okay"; 233 status = "okay";
249 234
250 mdio { 235 mdio {
251 #address-cells = <1>; 236 #address-cells = <1>;
252 #size-cells = <0>; 237 #size-cells = <0>;
253 238
254 ethphy0: ethernet-phy@6 { 239 ethphy0: ethernet-phy@6 {
255 compatible = "ethernet-phy-ieee802.3-c22"; 240 compatible = "ethernet-phy-ieee802.3-c22";
256 reg = <0x6>; 241 reg = <0x6>;
257 }; 242 };
258
259 ethphy1: ethernet-phy@7 {
260 compatible = "ethernet-phy-ieee802.3-c22";
261 reg = <0x7>;
262 };
263 }; 243 };
264 };
265
266 &mipi_csi {
267 clock-frequency = <240000000>;
268 status = "okay";
269 port {
270 csi_mipi_ep: endpoint1 {
271 remote-endpoint = <&csi_ep>;
272 data-lanes = <2>;
273 csis-hs-settle = <13>;
274 csis-clk-settle = <2>;
275 csis-wclk;
276 };
277 };
278 }; 244 };
279 245
280 &flexcan1 { 246 &flexcan1 {
281 pinctrl-names = "default"; 247 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_flexcan1>; 248 pinctrl-0 = <&pinctrl_flexcan1>;
283 xceiver-supply = <&reg_vref_1v8>; 249 xceiver-supply = <&reg_vref_1v8>;
284 status = "okay"; 250 status = "okay";
285 }; 251 };
286 252
287 &flexcan2 { 253 &flexcan2 {
288 pinctrl-names = "default"; 254 pinctrl-names = "default";
289 pinctrl-0 = <&pinctrl_flexcan2>; 255 pinctrl-0 = <&pinctrl_flexcan2>;
290 xceiver-supply = <&reg_vref_1v8>; 256 xceiver-supply = <&reg_vref_1v8>;
291 status = "okay"; 257 status = "okay";
292 }; 258 };
293 259
294 &i2c1 { 260 &i2c1 {
295 clock-frequency = <100000>; 261 clock-frequency = <100000>;
296 pinctrl-names = "default"; 262 pinctrl-names = "default";
297 pinctrl-0 = <&pinctrl_i2c1>; 263 pinctrl-0 = <&pinctrl_i2c1>;
298 status = "okay"; 264 status = "okay";
299 265
300 pmic: pfuze3000@08 { 266 pmic: pfuze3000@08 {
301 compatible = "fsl,pfuze3000"; 267 compatible = "fsl,pfuze3000";
302 reg = <0x08>; 268 reg = <0x08>;
303 269
304 regulators { 270 regulators {
305 sw1a_reg: sw1a { 271 sw1a_reg: sw1a {
306 regulator-min-microvolt = <700000>; 272 regulator-min-microvolt = <700000>;
307 regulator-max-microvolt = <3300000>; 273 regulator-max-microvolt = <3300000>;
308 regulator-boot-on; 274 regulator-boot-on;
309 regulator-always-on; 275 regulator-always-on;
310 regulator-ramp-delay = <6250>; 276 regulator-ramp-delay = <6250>;
311 }; 277 };
312 278
313 /* use sw1c_reg to align with pfuze100/pfuze200 */ 279 /* use sw1c_reg to align with pfuze100/pfuze200 */
314 sw1c_reg: sw1b { 280 sw1c_reg: sw1b {
315 regulator-min-microvolt = <700000>; 281 regulator-min-microvolt = <700000>;
316 regulator-max-microvolt = <1475000>; 282 regulator-max-microvolt = <1475000>;
317 regulator-boot-on; 283 regulator-boot-on;
318 regulator-always-on; 284 regulator-always-on;
319 regulator-ramp-delay = <6250>; 285 regulator-ramp-delay = <6250>;
320 }; 286 };
321 287
322 sw2_reg: sw2 { 288 sw2_reg: sw2 {
323 regulator-min-microvolt = <1500000>; 289 regulator-min-microvolt = <1500000>;
324 regulator-max-microvolt = <1850000>; 290 regulator-max-microvolt = <1850000>;
325 regulator-boot-on; 291 regulator-boot-on;
326 regulator-always-on; 292 regulator-always-on;
327 }; 293 };
328 294
329 sw3a_reg: sw3 { 295 sw3a_reg: sw3 {
330 regulator-min-microvolt = <900000>; 296 regulator-min-microvolt = <900000>;
331 regulator-max-microvolt = <1650000>; 297 regulator-max-microvolt = <1650000>;
332 regulator-boot-on; 298 regulator-boot-on;
333 regulator-always-on; 299 regulator-always-on;
334 }; 300 };
335 301
336 swbst_reg: swbst { 302 swbst_reg: swbst {
337 regulator-min-microvolt = <5000000>; 303 regulator-min-microvolt = <5000000>;
338 regulator-max-microvolt = <5150000>; 304 regulator-max-microvolt = <5150000>;
339 }; 305 };
340 306
341 snvs_reg: vsnvs { 307 snvs_reg: vsnvs {
342 regulator-min-microvolt = <1000000>; 308 regulator-min-microvolt = <1000000>;
343 regulator-max-microvolt = <3000000>; 309 regulator-max-microvolt = <3000000>;
344 regulator-boot-on; 310 regulator-boot-on;
345 regulator-always-on; 311 regulator-always-on;
346 }; 312 };
347 313
348 vref_reg: vrefddr { 314 vref_reg: vrefddr {
349 regulator-boot-on; 315 regulator-boot-on;
350 regulator-always-on; 316 regulator-always-on;
351 }; 317 };
352 318
353 vgen1_reg: vldo1 { 319 vgen1_reg: vldo1 {
354 regulator-min-microvolt = <1800000>; 320 regulator-min-microvolt = <1800000>;
355 regulator-max-microvolt = <3300000>; 321 regulator-max-microvolt = <3300000>;
356 regulator-always-on; 322 regulator-always-on;
357 }; 323 };
358 324
359 vgen2_reg: vldo2 { 325 vgen2_reg: vldo2 {
360 regulator-min-microvolt = <800000>; 326 regulator-min-microvolt = <800000>;
361 regulator-max-microvolt = <1550000>; 327 regulator-max-microvolt = <1550000>;
362 regulator-always-on; 328 regulator-always-on;
363 }; 329 };
364 330
365 vgen3_reg: vccsd { 331 vgen3_reg: vccsd {
366 regulator-min-microvolt = <2850000>; 332 regulator-min-microvolt = <2850000>;
367 regulator-max-microvolt = <3300000>; 333 regulator-max-microvolt = <3300000>;
368 regulator-always-on; 334 regulator-always-on;
369 }; 335 };
370 336
371 vgen4_reg: v33 { 337 vgen4_reg: v33 {
372 regulator-min-microvolt = <2850000>; 338 regulator-min-microvolt = <2850000>;
373 regulator-max-microvolt = <3300000>; 339 regulator-max-microvolt = <3300000>;
374 regulator-always-on; 340 regulator-always-on;
375 }; 341 };
376 342
377 vgen5_reg: vldo3 { 343 vgen5_reg: vldo3 {
378 regulator-min-microvolt = <1800000>; 344 regulator-min-microvolt = <1800000>;
379 regulator-max-microvolt = <3300000>; 345 regulator-max-microvolt = <3300000>;
380 regulator-always-on; 346 regulator-always-on;
381 }; 347 };
382 348
383 vgen6_reg: vldo4 { 349 vgen6_reg: vldo4 {
384 regulator-min-microvolt = <1800000>; 350 regulator-min-microvolt = <1800000>;
385 regulator-max-microvolt = <3300000>; 351 regulator-max-microvolt = <3300000>;
386 regulator-always-on; 352 regulator-always-on;
387 }; 353 };
388 }; 354 };
389 }; 355 };
390 356
391 s35390a: s35390a@30 { 357 s35390a: s35390a@30 {
392 compatible = "s35390a"; 358 compatible = "s35390a";
393 reg = <0x30>; 359 reg = <0x30>;
394 }; 360 };
395 361
396 cape_eeprom0: cape_eeprom@57 { 362 cape_eeprom0: cape_eeprom@57 {
397 compatible = "at,24c256"; 363 compatible = "at,24c256";
398 reg = <0x57>; 364 reg = <0x57>;
399 }; 365 };
400 366
401 codec: sgtl5000@0a { 367 codec: sgtl5000@0a {
402 compatible = "fsl,sgtl5000"; 368 compatible = "fsl,sgtl5000";
403 reg = <0x0a>; 369 reg = <0x0a>;
404 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; 370 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
405 clock-names = "mclk"; 371 clock-names = "mclk";
406 pinctrl-names = "default"; 372 pinctrl-names = "default";
407 pinctrl-0 = <&pinctrl_sai1_mclk>; 373 pinctrl-0 = <&pinctrl_sai1_mclk>;
408 VDDA-supply = <&reg_aud_3v3>; 374 VDDA-supply = <&reg_aud_3v3>;
409 VDDIO-supply = <&reg_vref_1v8>; 375 VDDIO-supply = <&reg_vref_1v8>;
410 assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>, 376 assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>,
411 <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; 377 <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
412 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; 378 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
413 assigned-clock-rates = <0>, <12288000>; 379 assigned-clock-rates = <0>, <12288000>;
414 }; 380 };
415 }; 381 };
416 382
417 &i2c2 { 383 &i2c2 {
418 clock-frequency = <100000>; 384 clock-frequency = <100000>;
419 pinctrl-names = "default"; 385 pinctrl-names = "default";
420 pinctrl-0 = <&pinctrl_i2c2>; 386 pinctrl-0 = <&pinctrl_i2c2>;
421 status = "okay"; 387 status = "okay";
422 388
423 baseboard_eeprom: baseboard_eeprom@50 { 389 baseboard_eeprom: baseboard_eeprom@50 {
424 compatible = "at,24c256"; 390 compatible = "at,24c256";
425 reg = <0x50>; 391 reg = <0x50>;
426 }; 392 };
427 }; 393 };
428 394
429 &i2c3 { 395 &i2c3 {
430 clock-frequency = <100000>; 396 clock-frequency = <100000>;
431 pinctrl-names = "default"; 397 pinctrl-names = "default";
432 pinctrl-0 = <&pinctrl_i2c3>; 398 pinctrl-0 = <&pinctrl_i2c3>;
433 status = "okay"; 399 status = "okay";
434 }; 400 };
435 401
436 &i2c4 { 402 &i2c4 {
437 clock-frequency = <100000>; 403 clock-frequency = <100000>;
438 pinctrl-names = "default"; 404 pinctrl-names = "default";
439 pinctrl-0 = <&pinctrl_i2c4>; 405 pinctrl-0 = <&pinctrl_i2c4>;
440 status = "okay"; 406 status = "okay";
441 }; 407 };
442 408
443 &lcdif { 409 &lcdif {
444 pinctrl-names = "default"; 410 pinctrl-names = "default";
445 pinctrl-0 = <&pinctrl_lcdif>; 411 pinctrl-0 = <&pinctrl_lcdif>;
446 enable-gpios = <&gpio3 4 0>; /* Enable LCD_VDD_EN pin */ 412 enable-gpios = <&gpio3 4 0>; /* Enable LCD_VDD_EN pin */
447 display = <&display0>; 413 display = <&display0>;
448 status = "okay"; 414 status = "okay";
449 415
450 display0: display@0 { 416 display0: display@0 {
451 bits-per-pixel = <32>; 417 bits-per-pixel = <32>;
452 bus-width = <24>; 418 bus-width = <24>;
453 419
454 display-timings { 420 display-timings {
455 native-mode = <&timing0>; 421 native-mode = <&timing0>;
456 /*timing0: g070vw01 {*/ 422 /*timing0: g070vw01 {*/
457 timing0: timing0 { 423 timing0: timing0 {
458 clock-frequency = <33300000>; 424 clock-frequency = <33300000>;
459 hactive = <800>; 425 hactive = <800>;
460 vactive = <480>; 426 vactive = <480>;
461 hfront-porch = <64>; 427 hfront-porch = <64>;
462 hback-porch = <64>; 428 hback-porch = <64>;
463 hsync-len = <128>; 429 hsync-len = <128>;
464 vback-porch = <12>; 430 vback-porch = <12>;
465 vfront-porch = <4>; 431 vfront-porch = <4>;
466 vsync-len = <12>; 432 vsync-len = <12>;
467 hsync-active = <0>; 433 hsync-active = <0>;
468 vsync-active = <0>; 434 vsync-active = <0>;
469 de-active = <1>; 435 de-active = <1>;
470 pixelclk-active = <0>; 436 pixelclk-active = <0>;
471 }; 437 };
472 }; 438 };
473 }; 439 };
474 }; 440 };
475 441
476 &sai1 { 442 &sai1 {
477 pinctrl-names = "default"; 443 pinctrl-names = "default";
478 pinctrl-0 = <&pinctrl_sai1>; 444 pinctrl-0 = <&pinctrl_sai1>;
479 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, 445 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
480 <&clks IMX7D_SAI1_ROOT_CLK>; 446 <&clks IMX7D_SAI1_ROOT_CLK>;
481 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; 447 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
482 assigned-clock-rates = <0>, <36864000>; 448 assigned-clock-rates = <0>, <36864000>;
483 status = "okay"; 449 status = "okay";
484 }; 450 };
485 451
486 &sdma { 452 &sdma {
487 status = "okay"; 453 status = "okay";
488 }; 454 };
489 455
490 /* GPIO5 configure as pwm1, to use GPIO5 as GPIO disabled this pin */ 456 /* GPIO5 configure as pwm1, to use GPIO5 as GPIO disabled this pin */
491 457
492 &pwm1 { 458 &pwm1 {
493 pinctrl-names = "default"; 459 pinctrl-names = "default";
494 pinctrl-0 = <&pinctrl_pwm1>; 460 pinctrl-0 = <&pinctrl_pwm1>;
495 status = "okay"; 461 status = "okay";
496 }; 462 };
497 463
498 &pwm2 { 464 &pwm2 {
499 pinctrl-names = "default"; 465 pinctrl-names = "default";
500 pinctrl-0 = <&pinctrl_pwm2>; 466 pinctrl-0 = <&pinctrl_pwm2>;
501 status = "okay"; 467 status = "okay";
502 }; 468 };
503 469
504 &iomuxc_lpsr { 470 &iomuxc_lpsr {
505 pinctrl-names = "default"; 471 pinctrl-names = "default";
506 pinctrl-0 = <&pinctrl_hog_2 &pinctrl_usbotg2_pwr_2>; 472 pinctrl-0 = <&pinctrl_hog_2 &pinctrl_usbotg2_pwr_2>;
507 473
508 imx7d-smarcfimx7 { 474 imx7d-smarcfimx7 {
509 pinctrl_hog_2: hoggrp-2 { 475 pinctrl_hog_2: hoggrp-2 {
510 fsl,pins = < 476 fsl,pins = <
511 MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14 477 MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14
512 >; 478 >;
513 }; 479 };
514 480
515 pinctrl_pwm1: pwm1grp { 481 pinctrl_pwm1: pwm1grp {
516 fsl,pins = < 482 fsl,pins = <
517 MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x30 483 MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x30
518 >; 484 >;
519 }; 485 };
520 486
521 pinctrl_pwm2: pwm2grp { 487 pinctrl_pwm2: pwm2grp {
522 fsl,pins = < 488 fsl,pins = <
523 MX7D_PAD_GPIO1_IO02__PWM2_OUT 0x30 489 MX7D_PAD_GPIO1_IO02__PWM2_OUT 0x30
524 >; 490 >;
525 }; 491 };
526 492
527 pinctrl_usbotg2_pwr_2: usbotg2-2 { 493 pinctrl_usbotg2_pwr_2: usbotg2-2 {
528 fsl,pins = < 494 fsl,pins = <
529 MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x14 495 MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x14
530 >; 496 >;
531 }; 497 };
532 498
533 pinctrl_enet2_epdc0_en: enet2_epdc0_grp { 499 pinctrl_enet2_epdc0_en: enet2_epdc0_grp {
534 fsl,pins = < 500 fsl,pins = <
535 MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x59 501 MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x59
536 >; 502 >;
537 }; 503 };
538 504
539 pinctrl_sai3_mclk: sai3grp_mclk { 505 pinctrl_sai3_mclk: sai3grp_mclk {
540 fsl,pins = < 506 fsl,pins = <
541 MX7D_PAD_GPIO1_IO03__SAI3_MCLK 0x1f 507 MX7D_PAD_GPIO1_IO03__SAI3_MCLK 0x1f
542 >; 508 >;
543 }; 509 };
544 510
545 pinctrl_wdog: wdoggrp { 511 pinctrl_wdog: wdoggrp {
546 fsl,pins = < 512 fsl,pins = <
547 MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B 0x74 513 MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B 0x74
548 >; 514 >;
549 }; 515 };
550 }; 516 };
551 }; 517 };
552 518
553 /* SER0/UART6 */ 519 /* SER0/UART6 */
554 &uart6 { 520 &uart6 {
555 pinctrl-names = "default"; 521 pinctrl-names = "default";
556 pinctrl-0 = <&pinctrl_uart6>; 522 pinctrl-0 = <&pinctrl_uart6>;
557 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; 523 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
558 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 524 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
559 fsl,uart-has-rtscts; 525 fsl,uart-has-rtscts;
560 status = "okay"; 526 status = "okay";
561 }; 527 };
562 528
563 /* SER1/UART2 */ 529 /* SER1/UART2 */
564 &uart2 { 530 &uart2 {
565 pinctrl-names = "default"; 531 pinctrl-names = "default";
566 pinctrl-0 = <&pinctrl_uart2>; 532 pinctrl-0 = <&pinctrl_uart2>;
567 assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; 533 assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
568 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; 534 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
569 status = "okay"; 535 status = "okay";
570 }; 536 };
571 537
572 /* SER2/UART7 */ 538 /* SER2/UART7 */
573 &uart7 { 539 &uart7 {
574 pinctrl-names = "default"; 540 pinctrl-names = "default";
575 pinctrl-0 = <&pinctrl_uart7>; 541 pinctrl-0 = <&pinctrl_uart7>;
576 assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>; 542 assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
577 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; 543 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
578 fsl,uart-has-rtscts; 544 fsl,uart-has-rtscts;
579 status = "okay"; 545 status = "okay";
580 }; 546 };
581 547
582 /* SER3/UART3 */ 548 /* SER3/UART3 */
583 &uart3 { 549 &uart3 {
584 pinctrl-names = "default"; 550 pinctrl-names = "default";
585 pinctrl-0 = <&pinctrl_uart3>; 551 pinctrl-0 = <&pinctrl_uart3>;
586 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; 552 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
587 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 553 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
588 status = "okay"; 554 status = "okay";
589 }; 555 };
590 556
591 &usbotg1 { 557 &usbotg1 {
592 vbus-supply = <&reg_usb_otg1_vbus>; 558 vbus-supply = <&reg_usb_otg1_vbus>;
593 gpios = <&gpio1 4 2>; 559 gpios = <&gpio1 4 2>;
594 srp-disable; 560 srp-disable;
595 hnp-disable; 561 hnp-disable;
596 adp-disable; 562 adp-disable;
597 status = "okay"; 563 status = "okay";
598 }; 564 };
599 565
600 &usdhc1 { 566 &usdhc1 {
601 pinctrl-names = "default"; 567 pinctrl-names = "default";
602 pinctrl-0 = <&pinctrl_usdhc1>; 568 pinctrl-0 = <&pinctrl_usdhc1>;
603 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 569 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
604 wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; 570 wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
605 no-1-8-v; 571 no-1-8-v;
606 vmmc-supply = <&reg_sd1_vmmc>; 572 vmmc-supply = <&reg_sd1_vmmc>;
607 enable-sdio-wakeup; 573 enable-sdio-wakeup;
608 keep-power-in-suspend; 574 keep-power-in-suspend;
609 status = "okay"; 575 status = "okay";
610 }; 576 };
611 577
612 &usdhc3 { 578 &usdhc3 {
613 pinctrl-names = "default"; 579 pinctrl-names = "default";
614 pinctrl-0 = <&pinctrl_usdhc3>; 580 pinctrl-0 = <&pinctrl_usdhc3>;
615 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; 581 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
616 assigned-clock-rates = <400000000>; 582 assigned-clock-rates = <400000000>;
617 bus-width = <8>; 583 bus-width = <8>;
618 fsl,tuning-step = <2>; 584 fsl,tuning-step = <2>;
619 non-removable; 585 non-removable;
620 status = "okay"; 586 status = "okay";
621 }; 587 };
622 588
623 &wdog1 { 589 &wdog1 {
624 pinctrl-names = "default"; 590 pinctrl-names = "default";
625 pinctrl-0 = <&pinctrl_wdog>; 591 pinctrl-0 = <&pinctrl_wdog>;
626 fsl,ext-reset-output; 592 fsl,ext-reset-output;
627 /*fsl,wdog_b;*/ 593 /*fsl,wdog_b;*/
628 }; 594 };
629 595
630 &iomuxc { 596 &iomuxc {
631 pinctrl-names = "default"; 597 pinctrl-names = "default";
632 pinctrl-0 = <&pinctrl_hog_1>; 598 pinctrl-0 = <&pinctrl_hog_1>;
633 599
634 imx7d-smarcfimx7 { 600 imx7d-smarcfimx7 {
635 601
636 pinctrl_hog_1: hoggrp-1 { 602 pinctrl_hog_1: hoggrp-1 {
637 fsl,pins = < 603 fsl,pins = <
638 MX7D_PAD_SD2_CMD__GPIO5_IO13 0x80000000 /* lvds channel select */ 604 MX7D_PAD_SD2_CMD__GPIO5_IO13 0x80000000 /* lvds channel select */
639 MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x80000000 /* pcie_wake# */ 605 MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x80000000 /* pcie_wake# */
640 MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x80000000 /* GPIO0 */ 606 MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x80000000 /* GPIO0 */
641 MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x80000000 /* GPIO1 */ 607 MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x80000000 /* GPIO1 */
642 MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x80000000 /* GPIO2 */ 608 MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x80000000 /* GPIO2 */
643 MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x80000000 /* GPIO3 */ 609 MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x80000000 /* GPIO3 */
644 MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x80000000 /* GPIO4 */ 610 MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x80000000 /* GPIO4 */
645 MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x80000000 /* GPIO6 */ 611 MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x80000000 /* GPIO6 */
646 MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x80000000 /* GPIO7 */ 612 MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x80000000 /* GPIO7 */
647 MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x80000000 /* GPIO8 */ 613 MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x80000000 /* GPIO8 */
648 MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x80000000 /* GPIO9 */ 614 MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x80000000 /* GPIO9 */
649 MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x80000000 /* GPIO10 */ 615 MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x80000000 /* GPIO10 */
650 MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x80000000 /* GPIO11 */ 616 MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x80000000 /* GPIO11 */
651 MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x80000000 /* SLEEP# */ 617 MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x80000000 /* SLEEP# */
652 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x80000000 /* CHARGER_PRSNT# */ 618 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x80000000 /* CHARGER_PRSNT# */
653 MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x80000000 /* CHARGING# */ 619 MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x80000000 /* CHARGING# */
654 MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x80000000 /* CARRIER_STBY# */ 620 MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x80000000 /* CARRIER_STBY# */
655 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x80000000 /* BATLOW# */ 621 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x80000000 /* BATLOW# */
656 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x80000000 /* SDIO_PWR_EN */ 622 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x80000000 /* SDIO_PWR_EN */
657 MX7D_PAD_LCD_RESET__GPIO3_IO4 0x80000000 /* LCD POWER */ 623 MX7D_PAD_LCD_RESET__GPIO3_IO4 0x80000000 /* LCD POWER */
658 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x80000000 /* RESET_OUT# */ 624 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x80000000 /* RESET_OUT# */
659 MX7D_PAD_ENET1_COL__GPIO7_IO15 0x80000000 /* ENET1_INT# */ 625 MX7D_PAD_ENET1_COL__GPIO7_IO15 0x80000000 /* ENET1_INT# */
660 MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x80000000 /* ENET2_INT# */ 626 MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x80000000 /* ENET2_INT# */
661 MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x80000000 /* WDT_TIME_OUT# */ 627 MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x80000000 /* WDT_TIME_OUT# */
662 MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x5d /* eMMC_Reset# */ 628 MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x5d /* eMMC_Reset# */
663 >; 629 >;
664 }; 630 };
665 631
666 pinctrl_ecspi1_cs: ecspi1_cs_grp { 632 pinctrl_ecspi1_cs: ecspi1_cs_grp {
667 fsl,pins = < 633 fsl,pins = <
668 MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x14 634 MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x14
669 MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x14 635 MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x14
670 >; 636 >;
671 }; 637 };
672 638
673 pinctrl_ecspi1: ecspi1grp { 639 pinctrl_ecspi1: ecspi1grp {
674 fsl,pins = < 640 fsl,pins = <
675 MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2 641 MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2
676 MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2 642 MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2
677 MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2 643 MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2
678 >; 644 >;
679 }; 645 };
680 646
681 pinctrl_ecspi2_cs: ecspi2_cs_grp { 647 pinctrl_ecspi2_cs: ecspi2_cs_grp {
682 fsl,pins = < 648 fsl,pins = <
683 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x14 649 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x14
684 >; 650 >;
685 }; 651 };
686 652
687 pinctrl_ecspi2: ecspi2grp { 653 pinctrl_ecspi2: ecspi2grp {
688 fsl,pins = < 654 fsl,pins = <
689 MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x2 655 MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x2
690 MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x2 656 MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x2
691 MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x2 657 MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x2
692 >; 658 >;
693 }; 659 };
694 660
695 pinctrl_ecspi3_cs: ecspi3_cs_grp { 661 pinctrl_ecspi3_cs: ecspi3_cs_grp {
696 fsl,pins = < 662 fsl,pins = <
697 MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 0x14 663 MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 0x14
698 MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x14 664 MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x14
699 >; 665 >;
700 }; 666 };
701 667
702 pinctrl_ecspi3: ecspi3grp { 668 pinctrl_ecspi3: ecspi3grp {
703 fsl,pins = < 669 fsl,pins = <
704 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2 670 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2
705 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2 671 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2
706 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2 672 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2
707 >; 673 >;
708 }; 674 };
709 675
710 pinctrl_enet1: enet1grp { 676 pinctrl_enet1: enet1grp {
711 fsl,pins = < 677 fsl,pins = <
712 MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 678 MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3
713 MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 679 MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3
714 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 680 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
715 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 681 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
716 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 682 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
717 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 683 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
718 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 684 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
719 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 685 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
720 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 686 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
721 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 687 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
722 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 688 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
723 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 689 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
724 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 690 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
725 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 691 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
726 >; 692 >;
727 }; 693 };
728 694
729 pinctrl_enet2: enet2grp { 695 pinctrl_enet2: enet2grp {
730 fsl,pins = < 696 fsl,pins = <
731 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 697 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1
732 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 698 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1
733 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 699 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1
734 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 700 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1
735 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 701 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1
736 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 702 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1
737 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 703 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1
738 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 704 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1
739 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 705 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1
740 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 706 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1
741 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 707 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1
742 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 708 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1
743 >; 709 >;
744 }; 710 };
745 711
746 pinctrl_epdc0: epdcgrp0 { 712 pinctrl_epdc0: epdcgrp0 {
747 fsl,pins = < 713 fsl,pins = <
748 MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x2 714 MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x2
749 MX7D_PAD_EPDC_DATA01__EPDC_DATA1 0x2 715 MX7D_PAD_EPDC_DATA01__EPDC_DATA1 0x2
750 MX7D_PAD_EPDC_DATA02__EPDC_DATA2 0x2 716 MX7D_PAD_EPDC_DATA02__EPDC_DATA2 0x2
751 MX7D_PAD_EPDC_DATA03__EPDC_DATA3 0x2 717 MX7D_PAD_EPDC_DATA03__EPDC_DATA3 0x2
752 MX7D_PAD_EPDC_DATA04__EPDC_DATA4 0x2 718 MX7D_PAD_EPDC_DATA04__EPDC_DATA4 0x2
753 MX7D_PAD_EPDC_DATA05__EPDC_DATA5 0x2 719 MX7D_PAD_EPDC_DATA05__EPDC_DATA5 0x2
754 MX7D_PAD_EPDC_DATA06__EPDC_DATA6 0x2 720 MX7D_PAD_EPDC_DATA06__EPDC_DATA6 0x2
755 MX7D_PAD_EPDC_DATA07__EPDC_DATA7 0x2 721 MX7D_PAD_EPDC_DATA07__EPDC_DATA7 0x2
756 MX7D_PAD_EPDC_DATA08__EPDC_DATA8 0x2 722 MX7D_PAD_EPDC_DATA08__EPDC_DATA8 0x2
757 MX7D_PAD_EPDC_DATA09__EPDC_DATA9 0x2 723 MX7D_PAD_EPDC_DATA09__EPDC_DATA9 0x2
758 MX7D_PAD_EPDC_DATA10__EPDC_DATA10 0x2 724 MX7D_PAD_EPDC_DATA10__EPDC_DATA10 0x2
759 MX7D_PAD_EPDC_DATA11__EPDC_DATA11 0x2 725 MX7D_PAD_EPDC_DATA11__EPDC_DATA11 0x2
760 MX7D_PAD_EPDC_DATA12__EPDC_DATA12 0x2 726 MX7D_PAD_EPDC_DATA12__EPDC_DATA12 0x2
761 MX7D_PAD_EPDC_DATA13__EPDC_DATA13 0x2 727 MX7D_PAD_EPDC_DATA13__EPDC_DATA13 0x2
762 MX7D_PAD_EPDC_DATA14__EPDC_DATA14 0x2 728 MX7D_PAD_EPDC_DATA14__EPDC_DATA14 0x2
763 MX7D_PAD_EPDC_DATA15__EPDC_DATA15 0x2 729 MX7D_PAD_EPDC_DATA15__EPDC_DATA15 0x2
764 MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK 0x2 730 MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK 0x2
765 MX7D_PAD_EPDC_SDLE__EPDC_SDLE 0x2 731 MX7D_PAD_EPDC_SDLE__EPDC_SDLE 0x2
766 MX7D_PAD_EPDC_SDOE__EPDC_SDOE 0x2 732 MX7D_PAD_EPDC_SDOE__EPDC_SDOE 0x2
767 MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR 0x2 733 MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR 0x2
768 MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 0x2 734 MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 0x2
769 MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 0x2 735 MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 0x2
770 MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK 0x2 736 MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK 0x2
771 MX7D_PAD_EPDC_GDOE__EPDC_GDOE 0x2 737 MX7D_PAD_EPDC_GDOE__EPDC_GDOE 0x2
772 MX7D_PAD_EPDC_GDRL__EPDC_GDRL 0x2 738 MX7D_PAD_EPDC_GDRL__EPDC_GDRL 0x2
773 MX7D_PAD_EPDC_GDSP__EPDC_GDSP 0x2 739 MX7D_PAD_EPDC_GDSP__EPDC_GDSP 0x2
774 >; 740 >;
775 }; 741 };
776 742
777 pinctrl_flexcan1: flexcan1grp { 743 pinctrl_flexcan1: flexcan1grp {
778 fsl,pins = < 744 fsl,pins = <
779 MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x59 745 MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x59
780 MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x59 746 MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x59
781 >; 747 >;
782 }; 748 };
783 749
784 pinctrl_flexcan2: flexcan2grp { 750 pinctrl_flexcan2: flexcan2grp {
785 fsl,pins = < 751 fsl,pins = <
786 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 752 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59
787 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59 753 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59
788 >; 754 >;
789 }; 755 };
790 756
791 pinctrl_i2c1: i2c1grp { 757 pinctrl_i2c1: i2c1grp {
792 fsl,pins = < 758 fsl,pins = <
793 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f 759 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
794 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f 760 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
795 >; 761 >;
796 }; 762 };
797 763
798 pinctrl_i2c2: i2c2grp { 764 pinctrl_i2c2: i2c2grp {
799 fsl,pins = < 765 fsl,pins = <
800 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f 766 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
801 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f 767 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
802 >; 768 >;
803 }; 769 };
804 770
805 771
806 pinctrl_i2c3: i2c3grp { 772 pinctrl_i2c3: i2c3grp {
807 fsl,pins = < 773 fsl,pins = <
808 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f 774 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
809 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f 775 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
810 >; 776 >;
811 }; 777 };
812 778
813 pinctrl_i2c4: i2c4grp { 779 pinctrl_i2c4: i2c4grp {
814 fsl,pins = < 780 fsl,pins = <
815 MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f 781 MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f
816 MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f 782 MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f
817 >; 783 >;
818 }; 784 };
819 785
820 pinctrl_lcdif: lcdifgrp { 786 pinctrl_lcdif: lcdifgrp {
821 fsl,pins = < 787 fsl,pins = <
822 MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 788 MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
823 MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 789 MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
824 MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 790 MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
825 MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 791 MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
826 MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 792 MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
827 MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 793 MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
828 MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 794 MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
829 MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 795 MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
830 MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 796 MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
831 MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 797 MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
832 MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 798 MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
833 MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 799 MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
834 MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 800 MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
835 MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 801 MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
836 MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 802 MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
837 MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 803 MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
838 MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 804 MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
839 MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 805 MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
840 MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 806 MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
841 MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 807 MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
842 MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 808 MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
843 MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 809 MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
844 MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 810 MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79
845 MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 811 MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
846 MX7D_PAD_LCD_CLK__LCD_CLK 0x79 812 MX7D_PAD_LCD_CLK__LCD_CLK 0x79
847 MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 813 MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79
848 MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 814 MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79
849 MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 815 MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79
850 >; 816 >;
851 }; 817 };
852 818
853 pinctrl_sai1: sai1grp { 819 pinctrl_sai1: sai1grp {
854 fsl,pins = < 820 fsl,pins = <
855 MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f 821 MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f
856 MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f 822 MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f
857 MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30 823 MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30
858 MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f 824 MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f
859 >; 825 >;
860 }; 826 };
861 827
862 pinctrl_sai1_mclk: sai1grp_mclk { 828 pinctrl_sai1_mclk: sai1grp_mclk {
863 fsl,pins = < 829 fsl,pins = <
864 MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f 830 MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
865 >; 831 >;
866 }; 832 };
867 833
868 pinctrl_sai2: sai2grp { 834 pinctrl_sai2: sai2grp {
869 fsl,pins = < 835 fsl,pins = <
870 MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f 836 MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f
871 MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f 837 MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f
872 MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30 838 MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30
873 MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f 839 MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f
874 >; 840 >;
875 }; 841 };
876 842
877 pinctrl_sai3: sai3grp { 843 pinctrl_sai3: sai3grp {
878 fsl,pins = < 844 fsl,pins = <
879 MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f 845 MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f
880 MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f 846 MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f
881 MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30 847 MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30
882 >; 848 >;
883 }; 849 };
884 850
885 pinctrl_uart1: uart1grp { 851 pinctrl_uart1: uart1grp {
886 fsl,pins = < 852 fsl,pins = <
887 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 853 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
888 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 854 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
889 >; 855 >;
890 }; 856 };
891 857
892 pinctrl_uart2: uart2grp { 858 pinctrl_uart2: uart2grp {
893 fsl,pins = < 859 fsl,pins = <
894 MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79 860 MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79
895 MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79 861 MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79
896 >; 862 >;
897 }; 863 };
898 864
899 pinctrl_uart3: uart3grp { 865 pinctrl_uart3: uart3grp {
900 fsl,pins = < 866 fsl,pins = <
901 MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 867 MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79
902 MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 868 MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79
903 >; 869 >;
904 }; 870 };
905 871
906 pinctrl_uart5: uart5grp { 872 pinctrl_uart5: uart5grp {
907 fsl,pins = < 873 fsl,pins = <
908 MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79 874 MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79
909 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79 875 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79
910 >; 876 >;
911 }; 877 };
912 878
913 pinctrl_uart5dte: uart5dtegrp { 879 pinctrl_uart5dte: uart5dtegrp {
914 fsl,pins = < 880 fsl,pins = <
915 MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX 0x79 881 MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX 0x79
916 MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX 0x79 882 MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX 0x79
917 >; 883 >;
918 }; 884 };
919 885
920 pinctrl_uart6: uart6grp { 886 pinctrl_uart6: uart6grp {
921 fsl,pins = < 887 fsl,pins = <
922 MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x79 888 MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x79
923 MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x79 889 MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x79
924 MX7D_PAD_EPDC_DATA10__UART6_DTE_CTS 0x79 890 MX7D_PAD_EPDC_DATA10__UART6_DTE_CTS 0x79
925 MX7D_PAD_EPDC_DATA11__UART6_DTE_RTS 0x79 891 MX7D_PAD_EPDC_DATA11__UART6_DTE_RTS 0x79
926 >; 892 >;
927 }; 893 };
928 894
929 pinctrl_uart7: uart7grp { 895 pinctrl_uart7: uart7grp {
930 fsl,pins = < 896 fsl,pins = <
931 MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x79 897 MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x79
932 MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x79 898 MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x79
933 MX7D_PAD_EPDC_DATA14__UART7_DTE_CTS 0x79 899 MX7D_PAD_EPDC_DATA14__UART7_DTE_CTS 0x79
934 MX7D_PAD_EPDC_DATA15__UART7_DTE_RTS 0x79 900 MX7D_PAD_EPDC_DATA15__UART7_DTE_RTS 0x79
935 >; 901 >;
936 }; 902 };
937 903
938 pinctrl_usdhc1_gpio: usdhc1_gpiogrp { 904 pinctrl_usdhc1_gpio: usdhc1_gpiogrp {
939 fsl,pins = < 905 fsl,pins = <
940 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ 906 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
941 MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ 907 MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
942 >; 908 >;
943 }; 909 };
944 910
945 pinctrl_usbotg2_pwr_1: usbotg2-1 { 911 pinctrl_usbotg2_pwr_1: usbotg2-1 {
946 fsl,pins = < 912 fsl,pins = <
947 MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 913 MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14
948 >; 914 >;
949 }; 915 };
950 916
951 pinctrl_usdhc1: usdhc1grp { 917 pinctrl_usdhc1: usdhc1grp {
952 fsl,pins = < 918 fsl,pins = <
953 MX7D_PAD_SD1_CMD__SD1_CMD 0x59 919 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
954 MX7D_PAD_SD1_CLK__SD1_CLK 0x19 920 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
955 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 921 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
956 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 922 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
957 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 923 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
958 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 924 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
959 925
960 >; 926 >;
961 }; 927 };
962 928
963 pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { 929 pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
964 fsl,pins = < 930 fsl,pins = <
965 MX7D_PAD_SD1_CMD__SD1_CMD 0x5a 931 MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
966 MX7D_PAD_SD1_CLK__SD1_CLK 0x1a 932 MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
967 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a 933 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
968 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a 934 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
969 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a 935 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
970 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a 936 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
971 >; 937 >;
972 }; 938 };
973 939
974 pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { 940 pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
975 fsl,pins = < 941 fsl,pins = <
976 MX7D_PAD_SD1_CMD__SD1_CMD 0x5b 942 MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
977 MX7D_PAD_SD1_CLK__SD1_CLK 0x1b 943 MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
978 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b 944 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
979 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b 945 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
980 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b 946 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
981 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b 947 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
982 >; 948 >;
983 }; 949 };
984 950
985 pinctrl_usdhc2: usdhc2grp { 951 pinctrl_usdhc2: usdhc2grp {
986 fsl,pins = < 952 fsl,pins = <
987 MX7D_PAD_SD2_CMD__SD2_CMD 0x59 953 MX7D_PAD_SD2_CMD__SD2_CMD 0x59
988 MX7D_PAD_SD2_CLK__SD2_CLK 0x19 954 MX7D_PAD_SD2_CLK__SD2_CLK 0x19
989 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 955 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
990 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 956 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
991 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 957 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
992 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 958 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
993 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x59 /* WL_REG_ON */ 959 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x59 /* WL_REG_ON */
994 >; 960 >;
995 }; 961 };
996 962
997 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { 963 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
998 fsl,pins = < 964 fsl,pins = <
999 MX7D_PAD_SD2_CMD__SD2_CMD 0x5a 965 MX7D_PAD_SD2_CMD__SD2_CMD 0x5a
1000 MX7D_PAD_SD2_CLK__SD2_CLK 0x1a 966 MX7D_PAD_SD2_CLK__SD2_CLK 0x1a
1001 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a 967 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a
1002 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a 968 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a
1003 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a 969 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a
1004 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a 970 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a
1005 >; 971 >;
1006 }; 972 };
1007 973
1008 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { 974 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
1009 fsl,pins = < 975 fsl,pins = <
1010 MX7D_PAD_SD2_CMD__SD2_CMD 0x5b 976 MX7D_PAD_SD2_CMD__SD2_CMD 0x5b
1011 MX7D_PAD_SD2_CLK__SD2_CLK 0x1b 977 MX7D_PAD_SD2_CLK__SD2_CLK 0x1b
1012 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b 978 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b
1013 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b 979 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b
1014 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b 980 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b
1015 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b 981 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b
1016 >; 982 >;
1017 }; 983 };
1018 984
1019 985
1020 pinctrl_usdhc3: usdhc3grp { 986 pinctrl_usdhc3: usdhc3grp {
1021 fsl,pins = < 987 fsl,pins = <
1022 MX7D_PAD_SD3_CMD__SD3_CMD 0x59 988 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
1023 MX7D_PAD_SD3_CLK__SD3_CLK 0x19 989 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
1024 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 990 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
1025 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 991 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
1026 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 992 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
1027 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 993 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
1028 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 994 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
1029 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 995 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
1030 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 996 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
1031 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 997 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
1032 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 998 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
1033 >; 999 >;
1034 }; 1000 };
1035 1001
1036 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { 1002 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
1037 fsl,pins = < 1003 fsl,pins = <
1038 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a 1004 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
1039 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a 1005 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
1040 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a 1006 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
1041 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a 1007 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
1042 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a 1008 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
1043 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a 1009 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
1044 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a 1010 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
1045 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a 1011 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
1046 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a 1012 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
1047 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a 1013 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
1048 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a 1014 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
1049 >; 1015 >;
1050 }; 1016 };
1051 1017
1052 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { 1018 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
1053 fsl,pins = < 1019 fsl,pins = <
1054 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b 1020 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
1055 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b 1021 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
1056 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b 1022 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
1057 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b 1023 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
1058 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b 1024 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
1059 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b 1025 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
1060 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b 1026 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
1061 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b 1027 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
1062 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b 1028 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
1063 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b 1029 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
1064 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b 1030 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
1065 >; 1031 >;
1066 }; 1032 };
1067 }; 1033 };
1068 }; 1034 };
1069 1035
arch/arm/boot/dts/imx7solo.dtsi
1 /* 1 /*
2 * Copyright 2015-2016 Freescale Semiconductor, Inc. 2 * Copyright 2015-2016 Freescale Semiconductor, Inc.
3 * Copyright 2016 Toradex AG 3 * Copyright 2016 Toradex AG
4 * Copyright 2017 NXP. 4 * Copyright 2017-2018 NXP
5 * 5 *
6 * This file is dual-licensed: you can use it either under the terms 6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a 8 * licensing only applies to this file, and not this project as a
9 * whole. 9 * whole.
10 * 10 *
11 * a) This file is free software; you can redistribute it and/or 11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the 13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version. 14 * License, or (at your option) any later version.
15 * 15 *
16 * This file is distributed in the hope that it will be useful, 16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details. 19 * GNU General Public License for more details.
20 * 20 *
21 * Or, alternatively, 21 * Or, alternatively,
22 * 22 *
23 * b) Permission is hereby granted, free of charge, to any person 23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation 24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without 25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use, 26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or 27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the 28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following 29 * Software is furnished to do so, subject to the following
30 * conditions: 30 * conditions:
31 * 31 *
32 * The above copyright notice and this permission notice shall be 32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software. 33 * included in all copies or substantial portions of the Software.
34 * 34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE. 42 * OTHER DEALINGS IN THE SOFTWARE.
43 */ 43 */
44 44
45 #include "imx7s.dtsi" 45 #include "imx7s.dtsi"
46 46
47 / { 47 / {
48 cpus { 48 cpus {
49 cpu0: cpu@0 { 49 cpu0: cpu@0 {
50 operating-points = < 50 operating-points = <
51 /* KHz uV */ 51 /* KHz uV */
52 1200000 1225000
52 996000 1075000 53 996000 1075000
53 792000 975000 54 792000 975000
54 >; 55 >;
55 clock-frequency = <996000000>; 56 clock-frequency = <996000000>;
56 }; 57 };
57 }; 58 };
58 59
59 reserved-memory { 60 reserved-memory {
60 #address-cells = <1>; 61 #address-cells = <1>;
61 #size-cells = <1>; 62 #size-cells = <1>;
62 ranges; 63 ranges;
63 64
64 /* global autoconfigured region for contiguous allocations */ 65 /* global autoconfigured region for contiguous allocations */
65 linux,cma { 66 linux,cma {
66 compatible = "shared-dma-pool"; 67 compatible = "shared-dma-pool";
67 reusable; 68 reusable;
68 size = <0x14000000>; 69 size = <0x6400000>;
69 linux,cma-default; 70 linux,cma-default;
70 }; 71 };
71 }; 72 };
72 73
73 soc { 74 soc {
74 busfreq { 75 busfreq {
75 compatible = "fsl,imx_busfreq"; 76 compatible = "fsl,imx_busfreq";
76 fsl,max_ddr_freq = <533000000>; 77 fsl,max_ddr_freq = <533000000>;
77 clocks = <&clks IMX7D_OSC_24M_CLK>, <&clks IMX7D_MAIN_AXI_ROOT_SRC>, 78 clocks = <&clks IMX7D_OSC_24M_CLK>, <&clks IMX7D_MAIN_AXI_ROOT_SRC>,
78 <&clks IMX7D_AHB_CHANNEL_ROOT_SRC>, <&clks IMX7D_PLL_SYS_PFD0_392M_CLK>, 79 <&clks IMX7D_AHB_CHANNEL_ROOT_SRC>, <&clks IMX7D_PLL_SYS_PFD0_392M_CLK>,
79 <&clks IMX7D_DRAM_ROOT_SRC>, <&clks IMX7D_DRAM_ALT_ROOT_SRC>, 80 <&clks IMX7D_DRAM_ROOT_SRC>, <&clks IMX7D_DRAM_ALT_ROOT_SRC>,
80 <&clks IMX7D_PLL_DRAM_MAIN_CLK>, <&clks IMX7D_DRAM_ALT_ROOT_CLK>, 81 <&clks IMX7D_PLL_DRAM_MAIN_CLK>, <&clks IMX7D_DRAM_ALT_ROOT_CLK>,
81 <&clks IMX7D_PLL_SYS_PFD2_270M_CLK>, <&clks IMX7D_PLL_SYS_PFD1_332M_CLK>, 82 <&clks IMX7D_PLL_SYS_PFD2_270M_CLK>, <&clks IMX7D_PLL_SYS_PFD1_332M_CLK>,
82 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>, <&clks IMX7D_MAIN_AXI_ROOT_DIV>; 83 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>, <&clks IMX7D_MAIN_AXI_ROOT_DIV>;
83 clock-names = "osc", "axi_sel", "ahb_sel", "pfd0_392m", "dram_root", "dram_alt_sel", 84 clock-names = "osc", "axi_sel", "ahb_sel", "pfd0_392m", "dram_root", "dram_alt_sel",
84 "pll_dram", "dram_alt_root", "pfd2_270m", "pfd1_332m", "ahb", "axi"; 85 "pll_dram", "dram_alt_root", "pfd2_270m", "pfd1_332m", "ahb", "axi";
85 interrupts = <0 112 0x04>, <0 113 0x04>; 86 interrupts = <0 112 0x04>, <0 113 0x04>;
86 interrupt-names = "irq_busfreq_0", "irq_busfreq_1"; 87 interrupt-names = "irq_busfreq_0", "irq_busfreq_1";
87 }; 88 };
88 89
89 caam_sm: caam-sm@00100000 { 90 caam_sm: caam-sm@00100000 {
90 compatible = "fsl,imx7d-caam-sm", "fsl,imx6q-caam-sm"; 91 compatible = "fsl,imx7d-caam-sm", "fsl,imx6q-caam-sm";
91 reg = <0x00100000 0x3fff>; 92 reg = <0x00100000 0x3fff>;
92 }; 93 };
93 94
94 irq_sec_vio: caam_secvio { 95 irq_sec_vio: caam_secvio {
95 compatible = "fsl,imx7d-caam-secvio", "fsl,imx6q-caam-secvio"; 96 compatible = "fsl,imx7d-caam-secvio", "fsl,imx6q-caam-secvio";
96 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 97 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
97 jtag-tamper = "disabled"; 98 jtag-tamper = "disabled";
98 watchdog-tamper = "enabled"; 99 watchdog-tamper = "enabled";
99 internal-boot-tamper = "enabled"; 100 internal-boot-tamper = "enabled";
100 external-pin-tamper = "disabled"; 101 external-pin-tamper = "disabled";
101 }; 102 };
102 103
103 pmu { 104 pmu {
104 compatible = "arm,cortex-a7-pmu"; 105 compatible = "arm,cortex-a7-pmu";
105 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 106 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
106 status = "disabled"; 107 status = "disabled";
107 }; 108 };
108 109
109 ocrams_ddr: sram@00900000 { 110 ocrams_ddr: sram@00900000 {
110 compatible = "fsl,ddr-lpm-sram"; 111 compatible = "fsl,ddr-lpm-sram";
111 reg = <0x00900000 0x1000>; 112 reg = <0x00900000 0x1000>;
112 clocks = <&clks IMX7D_OCRAM_CLK>; 113 clocks = <&clks IMX7D_OCRAM_CLK>;
113 }; 114 };
114 115
115 ocram: sram@901000 { 116 ocram: sram@901000 {
116 compatible = "mmio-sram"; 117 compatible = "mmio-sram";
117 reg = <0x00901000 0x1f000>; 118 reg = <0x00901000 0x1f000>;
118 clocks = <&clks IMX7D_OCRAM_CLK>; 119 clocks = <&clks IMX7D_OCRAM_CLK>;
119 }; 120 };
120 121
121 ocrams: sram@00180000 { 122 ocrams: sram@00180000 {
122 compatible = "fsl,lpm-sram"; 123 compatible = "fsl,lpm-sram";
123 reg = <0x00180000 0x8000>; 124 reg = <0x00180000 0x8000>;
124 clocks = <&clks IMX7D_OCRAM_S_CLK>; 125 clocks = <&clks IMX7D_OCRAM_S_CLK>;
125 status = "disabled"; 126 status = "disabled";
126 }; 127 };
127 128
128 ocrams_mf: sram-mf@00900000 { 129 ocrams_mf: sram-mf@00900000 {
129 compatible = "fsl,mega-fast-sram"; 130 compatible = "fsl,mega-fast-sram";
130 reg = <0x00900000 0x20000>; 131 reg = <0x00900000 0x20000>;
131 clocks = <&clks IMX7D_OCRAM_CLK>; 132 clocks = <&clks IMX7D_OCRAM_CLK>;
132 }; 133 };
133 134
135 ocram_optee {
136 compatible = "fsl,optee-lpm-sram";
137 reg = <0x00180000 0x8000>;
138 overw_reg = <&ocrams_ddr 0x00904000 0x1000>,
139 <&ocram 0x00905000 0x1b000>,
140 <&ocrams 0x00900000 0x4000>;
141 overw_clock = <&ocrams &clks IMX7D_OCRAM_CLK>;
142 };
143
134 dma_apbh: dma-apbh@33000000 { 144 dma_apbh: dma-apbh@33000000 {
135 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 145 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
136 reg = <0x33000000 0x2000>; 146 reg = <0x33000000 0x2000>;
137 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 147 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
138 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
139 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 150 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
141 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 151 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
142 #dma-cells = <1>; 152 #dma-cells = <1>;
143 dma-channels = <4>; 153 dma-channels = <4>;
144 clocks = <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 154 clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
145 <&clks IMX7D_NAND_ROOT_CLK>;
146 clock-names = "dma_apbh_bch", "dma_apbh_io";
147 }; 155 };
148 156
149 gpmi: gpmi-nand@33002000{ 157 gpmi: gpmi-nand@33002000{
150 compatible = "fsl,imx7d-gpmi-nand"; 158 compatible = "fsl,imx7d-gpmi-nand";
151 #address-cells = <1>; 159 #address-cells = <1>;
152 #size-cells = <1>; 160 #size-cells = <1>;
153 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 161 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
154 reg-names = "gpmi-nand", "bch"; 162 reg-names = "gpmi-nand", "bch";
155 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 163 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
156 interrupt-names = "bch"; 164 interrupt-names = "bch";
157 clocks = <&clks IMX7D_NAND_ROOT_CLK>, 165 clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
158 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>; 166 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
159 clock-names = "gpmi_io", "gpmi_bch_apb"; 167 clock-names = "gpmi_io", "gpmi_bch_apb";
160 dmas = <&dma_apbh 0>; 168 dmas = <&dma_apbh 0>;
161 dma-names = "rx-tx"; 169 dma-names = "rx-tx";
162 status = "disabled"; 170 status = "disabled";
163 }; 171 };
164
165 pcie: pcie@0x33800000 {
166 compatible = "fsl,imx7d-pcie", "snps,dw-pcie";
167 reg = <0x33800000 0x4000>, <0x4ff00000 0x80000>;
168 reg-names = "dbi", "config";
169 #address-cells = <3>;
170 #size-cells = <2>;
171 device_type = "pci";
172 ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000 /* downstream I/O 64KB */
173 0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
174 num-lanes = <1>;
175 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
176 interrupt-names = "msi";
177 #interrupt-cells = <1>;
178 interrupt-map-mask = <0 0 0 0x7>;
179 interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
180 <0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
181 <0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
182 <0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
183 clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
184 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
185 <&clks IMX7D_PCIE_PHY_ROOT_CLK>;
186 clock-names = "pcie", "pcie_bus", "pcie_phy";
187 pcie-phy-supply = <&reg_1p0d>;
188 fsl,max-link-speed = <2>;
189 status = "disabled";
190 };
191 }; 172 };
192 }; 173 };
193 174
194 &aips1 { 175 &aips1 {
195 kpp: kpp@30320000 { 176 kpp: kpp@30320000 {
196 compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp"; 177 compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
197 reg = <0x30320000 0x10000>; 178 reg = <0x30320000 0x10000>;
198 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 179 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
199 clocks = <&clks IMX7D_CLK_DUMMY>; 180 clocks = <&clks IMX7D_CLK_DUMMY>;
200 status = "disabled"; 181 status = "disabled";
201 }; 182 };
202 183
203 mqs: mqs { 184 mqs: mqs {
204 compatible = "fsl,imx6sx-mqs"; 185 compatible = "fsl,imx6sx-mqs";
205 gpr = <&gpr>; 186 gpr = <&gpr>;
206 status = "disabled"; 187 status = "disabled";
207 }; 188 };
208 189
209 ocotp: ocotp-ctrl@30350000 { 190 ocotp: ocotp-ctrl@30350000 {
210 compatible = "fsl,imx7d-ocotp", "syscon"; 191 compatible = "fsl,imx7d-ocotp", "syscon";
211 reg = <0x30350000 0x10000>; 192 reg = <0x30350000 0x10000>;
212 clocks = <&clks IMX7D_OCOTP_CLK>; 193 clocks = <&clks IMX7D_OCOTP_CLK>;
213 status = "okay"; 194 status = "okay";
214 }; 195 };
215 196
216 tempmon: tempmon { 197 tempmon: tempmon {
217 compatible = "fsl,imx7d-tempmon"; 198 compatible = "fsl,imx7d-tempmon";
218 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 199 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
219 fsl,tempmon =<&anatop>; 200 fsl,tempmon =<&anatop>;
220 fsl,tempmon-data = <&ocotp>; 201 fsl,tempmon-data = <&ocotp>;
221 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; 202 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
222 }; 203 };
223 204
224 caam_snvs: caam-snvs@30370000 { 205 caam_snvs: caam-snvs@30370000 {
225 compatible = "fsl,imx6q-caam-snvs"; 206 compatible = "fsl,imx6q-caam-snvs";
226 reg = <0x30370000 0x10000>; 207 reg = <0x30370000 0x10000>;
227 }; 208 };
228 iomuxc_lpsr_gpr: lpsr-gpr@30270000 { 209 iomuxc_lpsr_gpr: lpsr-gpr@30270000 {
229 compatible = "fsl,imx7d-lpsr-gpr"; 210 compatible = "fsl,imx7d-lpsr-gpr";
230 reg = <0x30270000 0x10000>; 211 reg = <0x30270000 0x10000>;
231 }; 212 };
232 }; 213 };
233 214
234 &aips2 { 215 &aips2 {
235 flextimer1: flextimer@30640000 { 216 flextimer1: flextimer@30640000 {
236 compatible = "fsl,imx7d-flextimer"; 217 compatible = "fsl,imx7d-flextimer";
237 reg = <0x30640000 0x10000>; 218 reg = <0x30640000 0x10000>;
238 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 219 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
239 status = "disabled"; 220 status = "disabled";
240 }; 221 };
241 222
242 flextimer2: flextimer@30650000 { 223 flextimer2: flextimer@30650000 {
243 compatible = "fsl,imx7d-flextimer"; 224 compatible = "fsl,imx7d-flextimer";
244 reg = <0x30650000 0x10000>; 225 reg = <0x30650000 0x10000>;
245 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 226 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
246 status = "disabled"; 227 status = "disabled";
247 }; 228 };
248 229
249 system_counter_rd: system-counter-rd@306a0000 { 230 system_counter_rd: system-counter-rd@306a0000 {
250 compatible = "fsl,imx7d-system-counter-rd"; 231 compatible = "fsl,imx7d-system-counter-rd";
251 reg = <0x306a0000 0x10000>; 232 reg = <0x306a0000 0x10000>;
252 status = "disabled"; 233 status = "disabled";
253 }; 234 };
254 235
255 system_counter_cmp: system-counter-cmp@306b0000 { 236 system_counter_cmp: system-counter-cmp@306b0000 {
256 compatible = "fsl,imx7d-system-counter-cmp"; 237 compatible = "fsl,imx7d-system-counter-cmp";
257 reg = <0x306b0000 0x10000>; 238 reg = <0x306b0000 0x10000>;
258 status = "disabled"; 239 status = "disabled";
259 }; 240 };
260 241
261 system_counter_ctrl: system-counter-ctrl@306c0000 { 242 system_counter_ctrl: system-counter-ctrl@306c0000 {
262 compatible = "fsl,imx7d-system-counter-ctrl"; 243 compatible = "fsl,imx7d-system-counter-ctrl";
263 reg = <0x306c0000 0x10000>; 244 reg = <0x306c0000 0x10000>;
264 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 245 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
265 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 246 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
266 status = "disabled"; 247 status = "disabled";
267 }; 248 };
268 249
269 pcie_phy: pcie-phy@306d0000 {
270 compatible = "fsl,imx-pcie-phy";
271 reg = <0x306d0000 0x10000>;
272 status = "disabled";
273 };
274
275 epdc: epdc@306f0000 { 250 epdc: epdc@306f0000 {
276 compatible = "fsl,imx7d-epdc"; 251 compatible = "fsl,imx7d-epdc";
277 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 252 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
278 reg = <0x306f0000 0x10000>; 253 reg = <0x306f0000 0x10000>;
279 clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_EPDC_PIXEL_ROOT_CLK>; 254 clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_EPDC_PIXEL_ROOT_CLK>;
280 clock-names = "epdc_axi", "epdc_pix"; 255 clock-names = "epdc_axi", "epdc_pix";
281 epdc-ram = <&gpr 0x4 30>; 256 epdc-ram = <&gpr 0x4 30>;
282 status = "disabled"; 257 status = "disabled";
283 }; 258 };
284 259
285 epxp: epxp@30700000 {
286 compatible = "fsl,imx7d-pxp-dma";
287 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
289 reg = <0x30700000 0x10000>;
290 clocks = <&clks IMX7D_PXP_IPG_CLK>, <&clks IMX7D_PXP_AXI_CLK>;
291 clock-names = "pxp_ipg", "pxp_axi";
292 status = "disabled";
293 };
294
295 csi1: csi@30710000 {
296 compatible = "fsl,imx7d-csi", "fsl,imx6s-csi";
297 reg = <0x30710000 0x10000>;
298 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&clks IMX7D_CLK_DUMMY>,
300 <&clks IMX7D_CSI_MCLK_ROOT_CLK>,
301 <&clks IMX7D_CLK_DUMMY>;
302 clock-names = "disp-axi", "csi_mclk", "disp_dcic";
303 status = "disabled";
304 };
305
306 mipi_csi: mipi-csi@30750000 {
307 compatible = "fsl,imx7d-mipi-csi";
308 reg = <0x30750000 0x10000>;
309 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
311 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
312 clock-names = "mipi_clk", "phy_clk";
313 mipi-phy-supply = <&reg_1p0d>;
314 csis-phy-reset = <&src 0x28 2>;
315 bus-width = <4>;
316 status = "disabled";
317 };
318
319 mipi_dsi: mipi-dsi@30760000 { 260 mipi_dsi: mipi-dsi@30760000 {
320 compatible = "fsl,imx7d-mipi-dsi"; 261 compatible = "fsl,imx7d-mipi-dsi";
321 reg = <0x30760000 0x10000>; 262 reg = <0x30760000 0x10000>;
322 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 263 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&clks IMX7D_MIPI_DSI_ROOT_CLK>, 264 clocks = <&clks IMX7D_MIPI_DSI_ROOT_CLK>,
324 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; 265 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
325 clock-names = "mipi_cfg_clk", "mipi_pllref_clk"; 266 clock-names = "mipi_cfg_clk", "mipi_pllref_clk";
326 mipi-phy-supply = <&reg_1p0d>; 267 mipi-phy-supply = <&reg_1p0d>;
327 status = "disabled"; 268 status = "disabled";
328 }; 269 };
329 270
330 ddrc: ddrc@307a0000 { 271 ddrc: ddrc@307a0000 {
331 compatible = "fsl,imx7-ddrc"; 272 compatible = "fsl,imx7-ddrc";
332 reg = <0x307a0000 0x10000>; 273 reg = <0x307a0000 0x10000>;
333 }; 274 };
334 }; 275 };
335 276
336 &aips3 { 277 &aips3 {
337 fec2: ethernet@30bf0000 {
338 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
339 reg = <0x30bf0000 0x10000>;
340 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
342 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>,
344 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
345 <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
346 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
347 <&clks IMX7D_ENET_PHY_REF_ROOT_DIV>;
348 clock-names = "ipg", "ahb", "ptp",
349 "enet_clk_ref", "enet_out";
350 fsl,num-tx-queues=<3>;
351 fsl,num-rx-queues=<3>;
352 status = "disabled";
353 };
354
355 crypto: caam@30900000 { 278 crypto: caam@30900000 {
356 compatible = "fsl,imx7d-caam", "fsl,sec-v4.0"; 279 compatible = "fsl,imx7d-caam", "fsl,sec-v4.0";
357 #address-cells = <1>; 280 #address-cells = <1>;
358 #size-cells = <1>; 281 #size-cells = <1>;
359 reg = <0x30900000 0x40000>; 282 reg = <0x30900000 0x40000>;
360 ranges = <0 0x30900000 0x40000>; 283 ranges = <0 0x30900000 0x40000>;
361 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 284 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&clks IMX7D_CAAM_CLK>, 285 clocks = <&clks IMX7D_CAAM_CLK>,
363 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; 286 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
364 clock-names = "ipg", "aclk"; 287 clock-names = "ipg", "aclk";
288
289 sec_ctrl: ctrl@0 {
290 /* CAAM Page 0 only accessible */
291 /* by secure world */
292 compatible = "fsl,sec-v4.0-ctrl";
293 reg = <0x30900000 0x1000>;
294 secure-status = "okay";
295 status = "disabled";
296 };
297
365 sec_jr0: jr0@1000 { 298 sec_jr0: jr0@1000 {
366 compatible = "fsl,sec-v4.0-job-ring"; 299 compatible = "fsl,sec-v4.0-job-ring";
367 reg = <0x1000 0x1000>; 300 reg = <0x1000 0x1000>;
368 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 301 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
369 }; 302 };
370 303
371 sec_jr1: jr1@2000 { 304 sec_jr1: jr1@2000 {
372 compatible = "fsl,sec-v4.0-job-ring"; 305 compatible = "fsl,sec-v4.0-job-ring";
373 reg = <0x2000 0x1000>; 306 reg = <0x2000 0x1000>;
374 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 307 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
375 }; 308 };
376 309
377 sec_jr2: jr2@3000 { 310 sec_jr2: jr2@3000 {
378 compatible = "fsl,sec-v4.0-job-ring"; 311 compatible = "fsl,sec-v4.0-job-ring";
379 reg = <0x3000 0x1000>; 312 reg = <0x3000 0x1000>;
380 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 313 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
381 }; 314 };
382 }; 315 };
383 316
384 mu: mu@30aa0000 { 317 mu: mu@30aa0000 {
385 compatible = "fsl,imx7d-mu", "fsl,imx6sx-mu"; 318 compatible = "fsl,imx7d-mu", "fsl,imx6sx-mu";
386 reg = <0x30aa0000 0x10000>; 319 reg = <0x30aa0000 0x10000>;
387 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 320 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&clks IMX7D_MU_ROOT_CLK>; 321 clocks = <&clks IMX7D_MU_ROOT_CLK>;
389 clock-names = "mu"; 322 clock-names = "mu";
390 status = "okay"; 323 status = "okay";
391 }; 324 };
392 325
393 rpmsg: rpmsg{ 326 rpmsg: rpmsg{
394 compatible = "fsl,imx7d-rpmsg"; 327 compatible = "fsl,imx7d-rpmsg";
395 status = "disabled"; 328 status = "disabled";
396 }; 329 };
397 330
398 sema4: sema4@30ac0000 { 331 sema4: sema4@30ac0000 {
399 compatible = "fsl,imx7d-sema4"; 332 compatible = "fsl,imx7d-sema4";
400 reg = <0x30ac0000 0x10000>; 333 reg = <0x30ac0000 0x10000>;
401 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 334 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&clks IMX7D_SEMA4_HS_ROOT_CLK>; 335 clocks = <&clks IMX7D_SEMA4_HS_ROOT_CLK>;
403 clock-names = "sema4"; 336 clock-names = "sema4";
404 status = "okay"; 337 status = "okay";
405 }; 338 };
406 339
407 sim1: sim@30b90000 { 340 sim1: sim@30b90000 {
408 compatible = "fsl,imx7d-sim"; 341 compatible = "fsl,imx7d-sim";
409 reg = <0x30b90000 0x10000>; 342 reg = <0x30b90000 0x10000>;
410 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 343 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
411 clocks = <&clks IMX7D_SIM1_ROOT_CLK>; 344 clocks = <&clks IMX7D_SIM1_ROOT_CLK>;
412 clock-names = "sim"; 345 clock-names = "sim";
413 status = "disabled"; 346 status = "disabled";
414 }; 347 };
415 348
416 sim2: sim@30ba0000 { 349 sim2: sim@30ba0000 {
417 compatible = "fsl,imx7d-sim"; 350 compatible = "fsl,imx7d-sim";
418 reg = <0x30ba0000 0x10000>; 351 reg = <0x30ba0000 0x10000>;
419 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 352 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
420 status = "disabled"; 353 status = "disabled";
421 }; 354 };
422 355
423 qspi1: qspi@30bb0000 { 356 qspi1: qspi@30bb0000 {
424 #address-cells = <1>; 357 #address-cells = <1>;
425 #size-cells = <0>; 358 #size-cells = <0>;
426 compatible = "fsl,imx7d-qspi"; 359 compatible = "fsl,imx7d-qspi";
427 reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>; 360 reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>;
428 reg-names = "QuadSPI", "QuadSPI-memory"; 361 reg-names = "QuadSPI", "QuadSPI-memory";
429 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 362 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&clks IMX7D_QSPI_ROOT_CLK>, 363 clocks = <&clks IMX7D_QSPI_ROOT_CLK>,