Commit bebd676186979b874bd801f47f7473f021b535bb

Authored by Eric Lee
1 parent e1a2ce3a20

Add i.MX7 solo core support

Showing 2 changed files with 25 additions and 131 deletions Side-by-side Diff

arch/arm/boot/dts/imx7s-smarcfimx7.dts
... ... @@ -215,21 +215,6 @@
215 215 assigned-clock-rates = <884736000>;
216 216 };
217 217  
218   -&csi1 {
219   - csi-mux-mipi = <&gpr 0x14 4>;
220   - status = "okay";
221   -
222   - port {
223   - csi_ep: endpoint {
224   - remote-endpoint = <&csi_mipi_ep>;
225   - };
226   - };
227   -};
228   -
229   -&epxp {
230   - status = "okay";
231   -};
232   -
233 218 &fec1 {
234 219 pinctrl-names = "default";
235 220 pinctrl-0 = <&pinctrl_enet1>;
236 221  
... ... @@ -255,26 +240,7 @@
255 240 compatible = "ethernet-phy-ieee802.3-c22";
256 241 reg = <0x6>;
257 242 };
258   -
259   - ethphy1: ethernet-phy@7 {
260   - compatible = "ethernet-phy-ieee802.3-c22";
261   - reg = <0x7>;
262   - };
263 243 };
264   -};
265   -
266   -&mipi_csi {
267   - clock-frequency = <240000000>;
268   - status = "okay";
269   - port {
270   - csi_mipi_ep: endpoint1 {
271   - remote-endpoint = <&csi_ep>;
272   - data-lanes = <2>;
273   - csis-hs-settle = <13>;
274   - csis-clk-settle = <2>;
275   - csis-wclk;
276   - };
277   - };
278 244 };
279 245  
280 246 &flexcan1 {
arch/arm/boot/dts/imx7solo.dtsi
1 1 /*
2 2 * Copyright 2015-2016 Freescale Semiconductor, Inc.
3 3 * Copyright 2016 Toradex AG
4   - * Copyright 2017 NXP.
  4 + * Copyright 2017-2018 NXP
5 5 *
6 6 * This file is dual-licensed: you can use it either under the terms
7 7 * of the GPL or the X11 license, at your option. Note that this dual
... ... @@ -49,6 +49,7 @@
49 49 cpu0: cpu@0 {
50 50 operating-points = <
51 51 /* KHz uV */
  52 + 1200000 1225000
52 53 996000 1075000
53 54 792000 975000
54 55 >;
... ... @@ -65,7 +66,7 @@
65 66 linux,cma {
66 67 compatible = "shared-dma-pool";
67 68 reusable;
68   - size = <0x14000000>;
  69 + size = <0x6400000>;
69 70 linux,cma-default;
70 71 };
71 72 };
... ... @@ -131,6 +132,15 @@
131 132 clocks = <&clks IMX7D_OCRAM_CLK>;
132 133 };
133 134  
  135 + ocram_optee {
  136 + compatible = "fsl,optee-lpm-sram";
  137 + reg = <0x00180000 0x8000>;
  138 + overw_reg = <&ocrams_ddr 0x00904000 0x1000>,
  139 + <&ocram 0x00905000 0x1b000>,
  140 + <&ocrams 0x00900000 0x4000>;
  141 + overw_clock = <&ocrams &clks IMX7D_OCRAM_CLK>;
  142 + };
  143 +
134 144 dma_apbh: dma-apbh@33000000 {
135 145 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
136 146 reg = <0x33000000 0x2000>;
... ... @@ -141,9 +151,7 @@
141 151 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
142 152 #dma-cells = <1>;
143 153 dma-channels = <4>;
144   - clocks = <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
145   - <&clks IMX7D_NAND_ROOT_CLK>;
146   - clock-names = "dma_apbh_bch", "dma_apbh_io";
  154 + clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
147 155 };
148 156  
149 157 gpmi: gpmi-nand@33002000{
150 158  
... ... @@ -154,40 +162,13 @@
154 162 reg-names = "gpmi-nand", "bch";
155 163 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
156 164 interrupt-names = "bch";
157   - clocks = <&clks IMX7D_NAND_ROOT_CLK>,
158   - <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>;
  165 + clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
  166 + <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
159 167 clock-names = "gpmi_io", "gpmi_bch_apb";
160 168 dmas = <&dma_apbh 0>;
161 169 dma-names = "rx-tx";
162 170 status = "disabled";
163 171 };
164   -
165   - pcie: pcie@0x33800000 {
166   - compatible = "fsl,imx7d-pcie", "snps,dw-pcie";
167   - reg = <0x33800000 0x4000>, <0x4ff00000 0x80000>;
168   - reg-names = "dbi", "config";
169   - #address-cells = <3>;
170   - #size-cells = <2>;
171   - device_type = "pci";
172   - ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000 /* downstream I/O 64KB */
173   - 0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
174   - num-lanes = <1>;
175   - interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
176   - interrupt-names = "msi";
177   - #interrupt-cells = <1>;
178   - interrupt-map-mask = <0 0 0 0x7>;
179   - interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
180   - <0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
181   - <0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
182   - <0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
183   - clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
184   - <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
185   - <&clks IMX7D_PCIE_PHY_ROOT_CLK>;
186   - clock-names = "pcie", "pcie_bus", "pcie_phy";
187   - pcie-phy-supply = <&reg_1p0d>;
188   - fsl,max-link-speed = <2>;
189   - status = "disabled";
190   - };
191 172 };
192 173 };
193 174  
... ... @@ -266,12 +247,6 @@
266 247 status = "disabled";
267 248 };
268 249  
269   - pcie_phy: pcie-phy@306d0000 {
270   - compatible = "fsl,imx-pcie-phy";
271   - reg = <0x306d0000 0x10000>;
272   - status = "disabled";
273   - };
274   -
275 250 epdc: epdc@306f0000 {
276 251 compatible = "fsl,imx7d-epdc";
277 252 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
... ... @@ -282,40 +257,6 @@
282 257 status = "disabled";
283 258 };
284 259  
285   - epxp: epxp@30700000 {
286   - compatible = "fsl,imx7d-pxp-dma";
287   - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
288   - <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
289   - reg = <0x30700000 0x10000>;
290   - clocks = <&clks IMX7D_PXP_IPG_CLK>, <&clks IMX7D_PXP_AXI_CLK>;
291   - clock-names = "pxp_ipg", "pxp_axi";
292   - status = "disabled";
293   - };
294   -
295   - csi1: csi@30710000 {
296   - compatible = "fsl,imx7d-csi", "fsl,imx6s-csi";
297   - reg = <0x30710000 0x10000>;
298   - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
299   - clocks = <&clks IMX7D_CLK_DUMMY>,
300   - <&clks IMX7D_CSI_MCLK_ROOT_CLK>,
301   - <&clks IMX7D_CLK_DUMMY>;
302   - clock-names = "disp-axi", "csi_mclk", "disp_dcic";
303   - status = "disabled";
304   - };
305   -
306   - mipi_csi: mipi-csi@30750000 {
307   - compatible = "fsl,imx7d-mipi-csi";
308   - reg = <0x30750000 0x10000>;
309   - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
310   - clocks = <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
311   - <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
312   - clock-names = "mipi_clk", "phy_clk";
313   - mipi-phy-supply = <&reg_1p0d>;
314   - csis-phy-reset = <&src 0x28 2>;
315   - bus-width = <4>;
316   - status = "disabled";
317   - };
318   -
319 260 mipi_dsi: mipi-dsi@30760000 {
320 261 compatible = "fsl,imx7d-mipi-dsi";
321 262 reg = <0x30760000 0x10000>;
... ... @@ -334,24 +275,6 @@
334 275 };
335 276  
336 277 &aips3 {
337   - fec2: ethernet@30bf0000 {
338   - compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
339   - reg = <0x30bf0000 0x10000>;
340   - interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
341   - <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
342   - <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
343   - clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>,
344   - <&clks IMX7D_ENET_AXI_ROOT_CLK>,
345   - <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
346   - <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
347   - <&clks IMX7D_ENET_PHY_REF_ROOT_DIV>;
348   - clock-names = "ipg", "ahb", "ptp",
349   - "enet_clk_ref", "enet_out";
350   - fsl,num-tx-queues=<3>;
351   - fsl,num-rx-queues=<3>;
352   - status = "disabled";
353   - };
354   -
355 278 crypto: caam@30900000 {
356 279 compatible = "fsl,imx7d-caam", "fsl,sec-v4.0";
357 280 #address-cells = <1>;
... ... @@ -362,6 +285,16 @@
362 285 clocks = <&clks IMX7D_CAAM_CLK>,
363 286 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
364 287 clock-names = "ipg", "aclk";
  288 +
  289 + sec_ctrl: ctrl@0 {
  290 + /* CAAM Page 0 only accessible */
  291 + /* by secure world */
  292 + compatible = "fsl,sec-v4.0-ctrl";
  293 + reg = <0x30900000 0x1000>;
  294 + secure-status = "okay";
  295 + status = "disabled";
  296 + };
  297 +
365 298 sec_jr0: jr0@1000 {
366 299 compatible = "fsl,sec-v4.0-job-ring";
367 300 reg = <0x1000 0x1000>;
... ... @@ -441,9 +374,5 @@
441 374 status = "disabled";
442 375 };
443 376  
444   -};
445   -
446   -&usbphynop3 {
447   - vcc-supply = <&reg_1p2>;
448 377 };