Resurrect Cobalt support for 2.6.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Resurrect Cobalt support for 2.6.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Ralf Baechle
1 parent 049b13c358
Showing 14 changed files with 276 additions and 223 deletions Side-by-side Diff
arch/mips/Makefile
arch/mips/cobalt/Makefile
arch/mips/cobalt/int-handler.S
arch/mips/cobalt/irq.c
arch/mips/cobalt/promcon.c
arch/mips/cobalt/reset.c
arch/mips/cobalt/setup.c
arch/mips/pci/fixup-cobalt.c
arch/mips/pci/ops-gt64111.c
drivers/char/lcd.c
drivers/char/lcd.h
include/asm-mips/cobalt/cobalt.h
include/asm-mips/cobalt/mach-gt64120.h
include/asm-mips/serial.h
@@ -323,6 +323,7 @@
 # Cobalt Server
 #
 core-$(CONFIG_MIPS_COBALT)	+= arch/mips/cobalt/
+cflags-$(CONFIG_MIPS_COBALT)	+= -Iinclude/asm-mips/cobalt
 load-$(CONFIG_MIPS_COBALT)	+= 0xffffffff80080000
  
 #
@@ -2,7 +2,7 @@
 # Makefile for the Cobalt micro systems family specific parts of the kernel
 #
  
-obj-y	 := irq.o int-handler.o reset.o setup.o promcon.o
+obj-y	 := irq.o int-handler.o reset.o setup.o
  
 EXTRA_AFLAGS := $(CFLAGS)
@@ -18,8 +18,8 @@
 		SAVE_ALL
 		CLI
  
-		la	ra, ret_from_irq
-		move	a1, sp
+		PTR_LA	ra, ret_from_irq
+		move	a0, sp
 		j	cobalt_irq
  
 		END(cobalt_handle_int)
@@ -10,6 +10,8 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
  
 #include <asm/i8259.h>
 #include <asm/irq_cpu.h>
@@ -25,8 +27,8 @@
  * the CPU interrupt lines, and ones that come in on the via chip. The CPU
  * mappings are:
  *
- *    16,  - Software interrupt 0 (unused)	IE_SW0
- *    17   - Software interrupt 1 (unused)	IE_SW0
+ *    16   - Software interrupt 0 (unused)	IE_SW0
+ *    17   - Software interrupt 1 (unused)	IE_SW1
  *    18   - Galileo chip (timer)		IE_IRQ0
  *    19   - Tulip 0 + NCR SCSI			IE_IRQ1
  *    20   - Tulip 1				IE_IRQ2
  
  
  
  
  
  
  
  
  
  
  
  
  
  
@@ -42,62 +44,95 @@
  *    15  - IDE1
  */
  
-asmlinkage void cobalt_irq(struct pt_regs *regs)
+static inline void galileo_irq(struct pt_regs *regs)
 {
-	unsigned int pending = read_c0_status() & read_c0_cause();
+	unsigned int mask, pending, devfn;
  
-	if (pending & CAUSEF_IP2) {			/* int 18 */
-		unsigned long irq_src = GALILEO_INL(GT_INTRCAUSE_OFS);
+	mask = GALILEO_INL(GT_INTRMASK_OFS);
+	pending = GALILEO_INL(GT_INTRCAUSE_OFS) & mask;
  
-		/* Check for timer irq ... */
-		if (irq_src & GALILEO_T0EXP) {
-			/* Clear the int line */
-			GALILEO_OUTL(0, GT_INTRCAUSE_OFS);
-			do_IRQ(COBALT_TIMER_IRQ, regs);
-		}
-		return;
-	}
+	if (pending & GALILEO_INTR_T0EXP) {
  
-	if (pending & CAUSEF_IP6) {			/* int 22 */
-		int irq = i8259_irq();
+		GALILEO_OUTL(~GALILEO_INTR_T0EXP, GT_INTRCAUSE_OFS);
+		do_IRQ(COBALT_GALILEO_IRQ, regs);
  
-		if (irq >= 0)
-			do_IRQ(irq, regs);
-		return;
-	}
+	} else if (pending & GALILEO_INTR_RETRY_CTR) {
  
-	if (pending & CAUSEF_IP3) {			/* int 19 */
-		do_IRQ(COBALT_ETH0_IRQ, regs);
-		return;
-	}
+		devfn = GALILEO_INL(GT_PCI0_CFGADDR_OFS) >> 8;
+		GALILEO_OUTL(~GALILEO_INTR_RETRY_CTR, GT_INTRCAUSE_OFS);
+		printk(KERN_WARNING "Galileo: PCI retry count exceeded (%02x.%u)\n",
+			PCI_SLOT(devfn), PCI_FUNC(devfn));
  
-	if (pending & CAUSEF_IP4) {			/* int 20 */
-		do_IRQ(COBALT_ETH1_IRQ, regs);
-		return;
-	}
+	} else {
  
-	if (pending & CAUSEF_IP5) {			/* int 21 */
-		do_IRQ(COBALT_SERIAL_IRQ, regs);
-		return;
+		GALILEO_OUTL(mask & ~pending, GT_INTRMASK_OFS);
+		printk(KERN_WARNING "Galileo: masking unexpected interrupt %08x\n", pending);
 	}
+}
  
-	if (pending & CAUSEF_IP7) {			/* int 23 */
-		do_IRQ(COBALT_QUBE_SLOT_IRQ, regs);
-		return;
-	}
+static inline void via_pic_irq(struct pt_regs *regs)
+{
+	int irq;
+
+	irq = i8259_irq();
+	if (irq >= 0)
+		do_IRQ(irq, regs);
 }
  
+asmlinkage void cobalt_irq(struct pt_regs *regs)
+{
+	unsigned pending;
+
+	pending = read_c0_status() & read_c0_cause();
+
+	if (pending & CAUSEF_IP2)			/* COBALT_GALILEO_IRQ (18) */
+
+		galileo_irq(regs);
+
+	else if (pending & CAUSEF_IP6)			/* COBALT_VIA_IRQ (22) */
+
+		via_pic_irq(regs);
+
+	else if (pending & CAUSEF_IP3)			/* COBALT_ETH0_IRQ (19) */
+
+		do_IRQ(COBALT_CPU_IRQ + 3, regs);
+
+	else if (pending & CAUSEF_IP4)			/* COBALT_ETH1_IRQ (20) */
+
+		do_IRQ(COBALT_CPU_IRQ + 4, regs);
+
+	else if (pending & CAUSEF_IP5)			/* COBALT_SERIAL_IRQ (21) */
+
+		do_IRQ(COBALT_CPU_IRQ + 5, regs);
+
+	else if (pending & CAUSEF_IP7)			/* IRQ 23 */
+
+		do_IRQ(COBALT_CPU_IRQ + 7, regs);
+}
+
+static struct irqaction irq_via = {
+	no_action, 0, { { 0, } }, "cascade", NULL, NULL
+};
+
 void __init arch_init_irq(void)
 {
+	/*
+	 * Mask all Galileo interrupts. The Galileo
+	 * handler is set in cobalt_timer_setup()
+	 */
+	GALILEO_OUTL(0, GT_INTRMASK_OFS);
+
 	set_except_vector(0, cobalt_handle_int);
  
 	init_i8259_irqs();				/*  0 ... 15 */
-	mips_cpu_irq_init(16);				/* 16 ... 23 */
+	mips_cpu_irq_init(COBALT_CPU_IRQ);		/* 16 ... 23 */
  
 	/*
 	 * Mask all cpu interrupts
 	 *  (except IE4, we already masked those at VIA level)
 	 */
 	change_c0_status(ST0_IM, IE_IRQ4);
+
+	setup_irq(COBALT_VIA_IRQ, &irq_via);
 }
-/*
- * PROM console for Cobalt Raq2
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995, 1996, 1997 by Ralf Baechle
- * Copyright (C) 2001 by Liam Davies (ldavies@agile.tv)
- *
- */
-
-#include <linux/init.h>
-#include <linux/console.h>
-#include <linux/kdev_t.h>
-#include <linux/serial_reg.h>
-
-#include <asm/delay.h>
-#include <asm/serial.h>
-#include <asm/io.h>
-
-static unsigned long port = 0xc800000;
-
-static __inline__ void ns16550_cons_put_char(char ch, unsigned long ioaddr)
-{
-	char lsr;
-
-	do {
-		lsr = inb(ioaddr + UART_LSR);
-	} while ((lsr & (UART_LSR_TEMT | UART_LSR_THRE)) != (UART_LSR_TEMT | UART_LSR_THRE));
-	outb(ch, ioaddr + UART_TX);
-}
-
-static __inline__ char ns16550_cons_get_char(unsigned long ioaddr)
-{
-	while ((inb(ioaddr + UART_LSR) & UART_LSR_DR) == 0)
-		udelay(1);
-	return inb(ioaddr + UART_RX);
-}
-
-void ns16550_console_write(struct console *co, const char *s, unsigned count)
-{
-	char lsr, ier;
-	unsigned i;
-
-	ier = inb(port + UART_IER);
-	outb(0x00, port + UART_IER);
-	for (i=0; i < count; i++, s++) {
-
-		if(*s == '\n')
-			ns16550_cons_put_char('\r', port);
-		ns16550_cons_put_char(*s, port);
-	}
-
-	do {
-		lsr = inb(port + UART_LSR);
-   	} while ((lsr & (UART_LSR_TEMT | UART_LSR_THRE)) != (UART_LSR_TEMT | UART_LSR_THRE));
-
-	outb(ier, port + UART_IER);
-}
-
-char getDebugChar(void)
-{
-	return ns16550_cons_get_char(port);
-}
-
-void putDebugChar(char kgdb_char)
-{
-	ns16550_cons_put_char(kgdb_char, port);
-}
-
-static struct console ns16550_console = {
-    .name	= "prom",
-    .setup	= NULL,
-    .write	= ns16550_console_write,
-    .flags	= CON_PRINTBUFFER,
-    .index	= -1,
-};
-
-static int __init ns16550_setup_console(void)
-{
-	register_console(&ns16550_console);
-
-	return 0;
-}
-
-console_initcall(ns16550_setup_console);
@@ -16,46 +16,43 @@
 #include <asm/reboot.h>
 #include <asm/system.h>
 #include <asm/mipsregs.h>
+#include <asm/cobalt/cobalt.h>
  
-void cobalt_machine_restart(char *command)
+void cobalt_machine_halt(void)
 {
-	*(volatile char *)0xbc000000 = 0x0f;
+	int state, last, diff;
+	unsigned long mark;
  
 	/*
-	 * Ouch, we're still alive ... This time we take the silver bullet ...
-	 * ... and find that we leave the hardware in a state in which the
-	 * kernel in the flush locks up somewhen during of after the PCI
-	 * detection stuff.
+	 * turn off bar on Qube, flash power off LED on RaQ (0.5Hz)
+	 *
+	 * restart if ENTER and SELECT are pressed
 	 */
-	set_c0_status(ST0_BEV | ST0_ERL);
-	change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
-	flush_cache_all();
-	write_c0_wired(0);
-	__asm__ __volatile__(
-		"jr\t%0"
-		:
-		: "r" (0xbfc00000));
-}
  
-extern int led_state;
-#define kLED            0xBC000000
-#define LEDSet(x)       (*(volatile unsigned char *) kLED) = (( unsigned char)x)
+	last = COBALT_KEY_PORT;
  
-void cobalt_machine_halt(void)
-{
-	int mark;
+	for (state = 0;;) {
  
-	/* Blink our cute? little LED (number 3)... */
-	while (1) {
-		led_state = led_state | ( 1 << 3 );
-		LEDSet(led_state);
-		mark = jiffies;
-		while (jiffies<(mark+HZ));
-		led_state = led_state & ~( 1 << 3 );
-		LEDSet(led_state);
-		mark = jiffies;
-		while (jiffies<(mark+HZ));
+		state ^= COBALT_LED_POWER_OFF;
+		COBALT_LED_PORT = state;
+
+		diff = COBALT_KEY_PORT ^ last;
+		last ^= diff;
+
+		if((diff & (COBALT_KEY_ENTER | COBALT_KEY_SELECT)) && !(~last & (COBALT_KEY_ENTER | COBALT_KEY_SELECT)))
+			COBALT_LED_PORT = COBALT_LED_RESET;
+
+		for (mark = jiffies; jiffies - mark < HZ;)
+			;
 	}
+}
+
+void cobalt_machine_restart(char *command)
+{
+	COBALT_LED_PORT = COBALT_LED_RESET;
+
+	/* we should never get here */
+	cobalt_machine_halt();
 }
  
 /*
@@ -13,6 +13,8 @@
 #include <linux/interrupt.h>
 #include <linux/pci.h>
 #include <linux/init.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
  
 #include <asm/bootinfo.h>
 #include <asm/time.h>
@@ -21,6 +23,7 @@
 #include <asm/processor.h>
 #include <asm/reboot.h>
 #include <asm/gt64120.h>
+#include <asm/serial.h>
  
 #include <asm/cobalt/cobalt.h>
  
  
  
  
  
  
  
@@ -30,45 +33,44 @@
  
 int cobalt_board_id;
  
-static char my_cmdline[CL_SIZE] = {
- "console=ttyS0,115200 "
-#ifdef CONFIG_IP_PNP
- "ip=on "
-#endif
-#ifdef CONFIG_ROOT_NFS
- "root=/dev/nfs "
-#else
- "root=/dev/hda1 "
-#endif
- };
-
 const char *get_system_type(void)
 {
+	switch (cobalt_board_id) {
+		case COBALT_BRD_ID_QUBE1:
+			return "Cobalt Qube";
+		case COBALT_BRD_ID_RAQ1:
+			return "Cobalt RaQ";
+		case COBALT_BRD_ID_QUBE2:
+			return "Cobalt Qube2";
+		case COBALT_BRD_ID_RAQ2:
+			return "Cobalt RaQ2";
+	}
 	return "MIPS Cobalt";
 }
  
 static void __init cobalt_timer_setup(struct irqaction *irq)
 {
-	/* Load timer value for 150 Hz */
-	GALILEO_OUTL(500000, GT_TC0_OFS);
+	/* Load timer value for 1KHz (TCLK is 50MHz) */
+	GALILEO_OUTL(50*1000*1000 / 1000, GT_TC0_OFS);
  
-	/* Register our timer interrupt */
-	setup_irq(COBALT_TIMER_IRQ, irq);
+	/* Enable timer */
+	GALILEO_OUTL(GALILEO_ENTC0 | GALILEO_SELTC0, GT_TC_CONTROL_OFS);
  
-	/* Enable timer ints */
-	GALILEO_OUTL((GALILEO_ENTC0 | GALILEO_SELTC0), GT_TC_CONTROL_OFS);
-	/* Unmask timer int */
-	GALILEO_OUTL(0x100, GT_INTRMASK_OFS);
+	/* Register interrupt */
+	setup_irq(COBALT_GALILEO_IRQ, irq);
+
+	/* Enable interrupt */
+	GALILEO_OUTL(GALILEO_INTR_T0EXP | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS);
 }
  
 extern struct pci_ops gt64111_pci_ops;
  
 static struct resource cobalt_mem_resource = {
-	"GT64111 PCI MEM", GT64111_IO_BASE, 0xffffffffUL, IORESOURCE_MEM
+	"PCI memory", GT64111_MEM_BASE, GT64111_MEM_END, IORESOURCE_MEM
 };
  
 static struct resource cobalt_io_resource = {
-	"GT64111 IO MEM", 0x00001000UL, 0x0fffffffUL, IORESOURCE_IO
+	"PCI I/O", 0x1000, 0xffff, IORESOURCE_IO
 };
  
 static struct resource cobalt_io_resources[] = {
  
@@ -86,11 +88,12 @@
 	.mem_resource	= &cobalt_mem_resource,
 	.mem_offset	= 0,
 	.io_resource	= &cobalt_io_resource,
-	.io_offset	= 0x00001000UL - GT64111_IO_BASE
+	.io_offset	= 0 - GT64111_IO_BASE
 };
  
 void __init plat_setup(void)
 {
+	static struct uart_port uart;
 	unsigned int devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0);
 	int i;
  
  
@@ -100,8 +103,11 @@
  
 	board_timer_setup = cobalt_timer_setup;
  
-        set_io_port_base(KSEG1ADDR(GT64111_IO_BASE));
+        set_io_port_base(CKSEG1ADDR(GT64111_IO_BASE));
  
+	/* I/O port resource must include UART and LCD/buttons */
+	ioport_resource.end = 0x0fffffff;
+
 	/*
 	 * This is a prom style console. We just poke at the
 	 *  UART to make it talk.
  
  
  
  
  
@@ -120,25 +126,61 @@
         cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8);
         cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id);
  
+	printk("Cobalt board ID: %d\n", cobalt_board_id);
+
 #ifdef CONFIG_PCI
 	register_pci_controller(&cobalt_pci_controller);
 #endif
+
+#ifdef CONFIG_SERIAL_8250
+	if (cobalt_board_id > COBALT_BRD_ID_RAQ1) {
+
+		uart.line	= 0;
+		uart.type	= PORT_UNKNOWN;
+		uart.uartclk	= 18432000;
+		uart.irq	= COBALT_SERIAL_IRQ;
+		uart.flags	= STD_COM_FLAGS;
+		uart.iobase	= 0xc800000;
+		uart.iotype	= UPIO_PORT;
+
+		early_serial_setup(&uart);
+	}
+#endif
 }
  
 /*
  * Prom init. We read our one and only communication with the firmware.
- * Grab the amount of installed memory
+ * Grab the amount of installed memory.
+ * Better boot loaders (CoLo) pass a command line too :-)
  */
  
 void __init prom_init(void)
 {
-	int argc = fw_arg0;
+	int narg, indx, posn, nchr;
+	unsigned long memsz;
+	char **argv;
  
-	strcpy(arcs_cmdline, my_cmdline);
-
 	mips_machgroup = MACH_GROUP_COBALT;
  
-	add_memory_region(0x0, argc & 0x7fffffff, BOOT_MEM_RAM);
+	memsz = fw_arg0 & 0x7fff0000;
+	narg = fw_arg0 & 0x0000ffff;
+
+	if (narg) {
+		arcs_cmdline[0] = '\0';
+		argv = (char **) fw_arg1;
+		posn = 0;
+		for (indx = 1; indx < narg; ++indx) {
+			nchr = strlen(argv[indx]);
+			if (posn + 1 + nchr + 1 > sizeof(arcs_cmdline))
+				break;
+			if (posn)
+				arcs_cmdline[posn++] = ' ';
+			strcpy(arcs_cmdline + posn, argv[indx]);
+			posn += nchr;
+		}
+	}
+
+	add_memory_region(0x0, memsz, BOOT_MEM_RAM);
 }
  
 unsigned long __init prom_free_prom_memory(void)
@@ -21,6 +21,20 @@
  
 extern int cobalt_board_id;
  
+static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
+{
+	if (dev->devfn == PCI_DEVFN(0, 0) &&
+		(dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) {
+
+		dev->class = (PCI_CLASS_BRIDGE_HOST << 8) | (dev->class & 0xff);
+
+		printk(KERN_INFO "Galileo: fixed bridge class\n");
+	}
+}
+
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
+	 qube_raq_galileo_early_fixup);
+
 static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
 {
 	unsigned short cfgword;
@@ -48,6 +62,9 @@
 {
 	unsigned short galileo_id;
  
+	if (dev->devfn != PCI_DEVFN(0, 0))
+		return;
+
 	/* Fix PCI latency-timer and cache-line-size values in Galileo
 	 * host bridge.
 	 */
@@ -55,6 +72,13 @@
 	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
  
 	/*
+	 * The code described by the comment below has been removed
+	 * as it causes bus mastering by the Ethernet controllers
+	 * to break under any kind of network load. We always set
+	 * the retry timeouts to their maximum.
+	 *
+	 * --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--
+	 *
 	 * On all machines prior to Q2, we had the STOP line disconnected
 	 * from Galileo to VIA on PCI.  The new Galileo does not function
 	 * correctly unless we have it connected.
  
  
  
  
@@ -64,21 +88,43 @@
 	 */
 	pci_read_config_word(dev, PCI_REVISION_ID, &galileo_id);
 	galileo_id &= 0xff;	/* mask off class info */
+
+ 	printk(KERN_INFO "Galileo: revision %u\n", galileo_id);
+
+#if 0
 	if (galileo_id >= 0x10) {
 		/* New Galileo, assumes PCI stop line to VIA is connected. */
 		GALILEO_OUTL(0x4020, GT_PCI0_TOR_OFS);
-	} else if (galileo_id == 0x1 || galileo_id == 0x2) {
+	} else if (galileo_id == 0x1 || galileo_id == 0x2)
+#endif
+	{
 		signed int timeo;
 		/* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
 		timeo = GALILEO_INL(GT_PCI0_TOR_OFS);
 		/* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
-		GALILEO_OUTL(0xffff, GT_PCI0_TOR_OFS);
+		GALILEO_OUTL(
+			(0xff << 16) |		/* retry count */
+			(0xff << 8) |		/* timeout 1   */
+			0xff,			/* timeout 0   */
+			GT_PCI0_TOR_OFS);
+
+		/* enable PCI retry exceeded interrupt */
+		GALILEO_OUTL(GALILEO_INTR_RETRY_CTR | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS);
 	}
 }
  
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GALILEO, PCI_ANY_ID,
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
 	 qube_raq_galileo_fixup);
  
+static char irq_tab_qube1[] __initdata = {
+  [COBALT_PCICONF_CPU]     = 0,
+  [COBALT_PCICONF_ETH0]    = COBALT_QUBE1_ETH0_IRQ,
+  [COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ,
+  [COBALT_PCICONF_VIA]     = 0,
+  [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ,
+  [COBALT_PCICONF_ETH1]    = 0
+};
+
 static char irq_tab_cobalt[] __initdata = {
   [COBALT_PCICONF_CPU]     = 0,
   [COBALT_PCICONF_ETH0]    = COBALT_ETH0_IRQ,
@@ -99,6 +145,9 @@
  
 int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 {
+	if (cobalt_board_id < COBALT_BRD_ID_QUBE2)
+		return irq_tab_qube1[slot];
+
 	if (cobalt_board_id == COBALT_BRD_ID_RAQ2)
 		return irq_tab_raq2[slot];
  
@@ -18,15 +18,15 @@
 #include <asm/cobalt/cobalt.h>
  
 /*
- * Accessing device 31 hangs the GT64120.  Not sure if this will also hang
- * the GT64111, let's be paranoid for now.
+ * Device 31 on the GT64111 is used to generate PCI special
+ * cycles, so we shouldn't expected to find a device there ...
  */
 static inline int pci_range_ck(struct pci_bus *bus, unsigned int devfn)
 {
-	if (bus->number == 0 && devfn == PCI_DEVFN(31, 0))
-		return -1;
+	if (bus->number == 0 && PCI_SLOT(devfn) < 31)
+		return 0;
  
-	return 0;
+	return -1;
 }
  
 static int gt64111_pci_read_config(struct pci_bus *bus, unsigned int devfn,
@@ -575,8 +575,8 @@
  
 static int lcd_waiters = 0;
  
-static long lcd_read(struct inode *inode, struct file *file, char *buf,
-		     unsigned long count)
+static ssize_t lcd_read(struct file *file, char *buf,
+		     size_t count, loff_t *ofs)
 {
 	long buttons_now;
  
@@ -22,7 +22,7 @@
 #define MAX_IDLE_TIME 120
  
 struct lcd_display {
-        unsigned long buttons;
+        unsigned buttons;
         int size1;
         int size2;
         unsigned char line1[LCD_CHARS_PER_LINE];
@@ -19,19 +19,24 @@
  *     9  - PCI
  *    14  - IDE0
  *    15  - IDE1
- *
+ */
+#define COBALT_QUBE_SLOT_IRQ	9
+
+/*
  * CPU IRQs  are 16 ... 23
  */
-#define COBALT_TIMER_IRQ	18
-#define COBALT_SCC_IRQ          19		/* pre-production has 85C30 */
-#define COBALT_RAQ_SCSI_IRQ	19
-#define COBALT_ETH0_IRQ		19
-#define COBALT_ETH1_IRQ		20
-#define COBALT_SERIAL_IRQ	21
-#define COBALT_SCSI_IRQ         21
-#define COBALT_VIA_IRQ		22		/* Chained to VIA ISA bridge */
-#define COBALT_QUBE_SLOT_IRQ	23
+#define COBALT_CPU_IRQ		16
  
+#define COBALT_GALILEO_IRQ	(COBALT_CPU_IRQ + 2)
+#define COBALT_SCC_IRQ          (COBALT_CPU_IRQ + 3)	/* pre-production has 85C30 */
+#define COBALT_RAQ_SCSI_IRQ	(COBALT_CPU_IRQ + 3)
+#define COBALT_ETH0_IRQ		(COBALT_CPU_IRQ + 3)
+#define COBALT_QUBE1_ETH0_IRQ	(COBALT_CPU_IRQ + 4)
+#define COBALT_ETH1_IRQ		(COBALT_CPU_IRQ + 4)
+#define COBALT_SERIAL_IRQ	(COBALT_CPU_IRQ + 5)
+#define COBALT_SCSI_IRQ         (COBALT_CPU_IRQ + 5)
+#define COBALT_VIA_IRQ		(COBALT_CPU_IRQ + 6)	/* Chained to VIA ISA bridge */
+
 /*
  * PCI configuration space manifest constants.  These are wired into
  * the board layout according to the PCI spec to enable the software
  
  
  
@@ -69,16 +74,21 @@
  * Most of this really should go into a separate GT64111 header file.
  */
 #define GT64111_IO_BASE		0x10000000UL
+#define GT64111_IO_END		0x11ffffffUL
+#define GT64111_MEM_BASE	0x12000000UL
+#define GT64111_MEM_END		0x13ffffffUL
 #define GT64111_BASE		0x14000000UL
-#define GALILEO_REG(ofs)	(KSEG0 + GT64111_BASE + (unsigned long)(ofs))
+#define GALILEO_REG(ofs)	CKSEG1ADDR(GT64111_BASE + (unsigned long)(ofs))
  
 #define GALILEO_INL(port)	(*(volatile unsigned int *) GALILEO_REG(port))
 #define GALILEO_OUTL(val, port)						\
 do {									\
-	*(volatile unsigned int *) GALILEO_REG(port) = (port);		\
+	*(volatile unsigned int *) GALILEO_REG(port) = (val);		\
 } while (0)
  
-#define GALILEO_T0EXP		0x0100
+#define GALILEO_INTR_T0EXP	(1 << 8)
+#define GALILEO_INTR_RETRY_CTR	(1 << 20)
+
 #define GALILEO_ENTC0		0x01
 #define GALILEO_SELTC0		0x02
  
@@ -86,6 +96,22 @@
 	GALILEO_OUTL((0x80000000 | (PCI_SLOT (devfn) << 11) |		\
 		(PCI_FUNC (devfn) << 8) | (where)), GT_PCI0_CFGADDR_OFS)
  
+#define COBALT_LED_PORT		(*(volatile unsigned char *) CKSEG1ADDR(0x1c000000))
+# define COBALT_LED_BAR_LEFT	(1 << 0)	/* Qube */
+# define COBALT_LED_BAR_RIGHT	(1 << 1)	/* Qube */
+# define COBALT_LED_WEB		(1 << 2)	/* RaQ */
+# define COBALT_LED_POWER_OFF	(1 << 3)	/* RaQ */
+# define COBALT_LED_RESET	0x0f
+
+#define COBALT_KEY_PORT		((~*(volatile unsigned int *) CKSEG1ADDR(0x1d000000) >> 24) & COBALT_KEY_MASK)
+# define COBALT_KEY_CLEAR	(1 << 1)
+# define COBALT_KEY_LEFT	(1 << 2)
+# define COBALT_KEY_UP		(1 << 3)
+# define COBALT_KEY_DOWN	(1 << 4)
+# define COBALT_KEY_RIGHT	(1 << 5)
+# define COBALT_KEY_ENTER	(1 << 6)
+# define COBALT_KEY_SELECT	(1 << 7)
+# define COBALT_KEY_MASK	0xfe
  
 #endif /* __ASM_COBALT_H */
+/* there's something here ... in the dark */
@@ -52,16 +52,6 @@
 #define JAZZ_SERIAL_PORT_DEFNS
 #endif
  
-#ifdef CONFIG_MIPS_COBALT
-#include <asm/cobalt/cobalt.h>
-#define COBALT_BASE_BAUD  (18432000 / 16)
-#define COBALT_SERIAL_PORT_DEFNS		\
-	/* UART CLK   PORT  IRQ  FLAGS    */ 		\
-	{ 0, COBALT_BASE_BAUD, 0xc800000, COBALT_SERIAL_IRQ, STD_COM_FLAGS },   /* ttyS0 */
-#else
-#define COBALT_SERIAL_PORT_DEFNS
-#endif
-
 /*
  * Both Galileo boards have the same UART mappings.
  */
@@ -342,7 +332,6 @@
 #endif /* CONFIG_SGI_IP32 */
  
 #define SERIAL_PORT_DFNS				\
-	COBALT_SERIAL_PORT_DEFNS			\
 	DDB5477_SERIAL_PORT_DEFNS			\
 	EV96100_SERIAL_PORT_DEFNS			\
 	IP32_SERIAL_PORT_DEFNS                          \
...	...	@@ -323,6 +323,7 @@
323	323	# Cobalt Server
324	324	#
325	325	core-$(CONFIG_MIPS_COBALT) += arch/mips/cobalt/
	326	+cflags-$(CONFIG_MIPS_COBALT) += -Iinclude/asm-mips/cobalt
326	327	load-$(CONFIG_MIPS_COBALT) += 0xffffffff80080000
327	328
328	329	#
...	...	@@ -2,7 +2,7 @@
2	2	# Makefile for the Cobalt micro systems family specific parts of the kernel
3	3	#
4	4
5		-obj-y := irq.o int-handler.o reset.o setup.o promcon.o
	5	+obj-y := irq.o int-handler.o reset.o setup.o
6	6
7	7	EXTRA_AFLAGS := $(CFLAGS)
...	...	@@ -18,8 +18,8 @@
18	18	SAVE_ALL
19	19	CLI
20	20
21		- la ra, ret_from_irq
22		- move a1, sp
	21	+ PTR_LA ra, ret_from_irq
	22	+ move a0, sp
23	23	j cobalt_irq
24	24
25	25	END(cobalt_handle_int)
...	...	@@ -10,6 +10,8 @@
10	10	#include <linux/kernel.h>
11	11	#include <linux/init.h>
12	12	#include <linux/irq.h>
	13	+#include <linux/interrupt.h>
	14	+#include <linux/pci.h>
13	15
14	16	#include <asm/i8259.h>
15	17	#include <asm/irq_cpu.h>
...	...	@@ -25,8 +27,8 @@
25	27	* the CPU interrupt lines, and ones that come in on the via chip. The CPU
26	28	* mappings are:
27	29	*
28		- * 16, - Software interrupt 0 (unused) IE_SW0
29		- * 17 - Software interrupt 1 (unused) IE_SW0
	30	+ * 16 - Software interrupt 0 (unused) IE_SW0
	31	+ * 17 - Software interrupt 1 (unused) IE_SW1
30	32	* 18 - Galileo chip (timer) IE_IRQ0
31	33	* 19 - Tulip 0 + NCR SCSI IE_IRQ1
32	34	* 20 - Tulip 1 IE_IRQ2
33	35
34	36
35	37
36	38
37	39
38	40
39	41
40	42
41	43
42	44
43	45
44	46
45	47
46	48
...	...	@@ -42,62 +44,95 @@
42	44	* 15 - IDE1
43	45	*/
44	46
45		-asmlinkage void cobalt_irq(struct pt_regs *regs)
	47	+static inline void galileo_irq(struct pt_regs *regs)
46	48	{
47		- unsigned int pending = read_c0_status() & read_c0_cause();
	49	+ unsigned int mask, pending, devfn;
48	50
49		- if (pending & CAUSEF_IP2) { /* int 18 */
50		- unsigned long irq_src = GALILEO_INL(GT_INTRCAUSE_OFS);
	51	+ mask = GALILEO_INL(GT_INTRMASK_OFS);
	52	+ pending = GALILEO_INL(GT_INTRCAUSE_OFS) & mask;
51	53
52		- /* Check for timer irq ... */
53		- if (irq_src & GALILEO_T0EXP) {
54		- /* Clear the int line */
55		- GALILEO_OUTL(0, GT_INTRCAUSE_OFS);
56		- do_IRQ(COBALT_TIMER_IRQ, regs);
57		- }
58		- return;
59		- }
	54	+ if (pending & GALILEO_INTR_T0EXP) {
60	55
61		- if (pending & CAUSEF_IP6) { /* int 22 */
62		- int irq = i8259_irq();
	56	+ GALILEO_OUTL(~GALILEO_INTR_T0EXP, GT_INTRCAUSE_OFS);
	57	+ do_IRQ(COBALT_GALILEO_IRQ, regs);
63	58
64		- if (irq >= 0)
65		- do_IRQ(irq, regs);
66		- return;
67		- }
	59	+ } else if (pending & GALILEO_INTR_RETRY_CTR) {
68	60
69		- if (pending & CAUSEF_IP3) { /* int 19 */
70		- do_IRQ(COBALT_ETH0_IRQ, regs);
71		- return;
72		- }
	61	+ devfn = GALILEO_INL(GT_PCI0_CFGADDR_OFS) >> 8;
	62	+ GALILEO_OUTL(~GALILEO_INTR_RETRY_CTR, GT_INTRCAUSE_OFS);
	63	+ printk(KERN_WARNING "Galileo: PCI retry count exceeded (%02x.%u)\n",
	64	+ PCI_SLOT(devfn), PCI_FUNC(devfn));
73	65
74		- if (pending & CAUSEF_IP4) { /* int 20 */
75		- do_IRQ(COBALT_ETH1_IRQ, regs);
76		- return;
77		- }
	66	+ } else {
78	67
79		- if (pending & CAUSEF_IP5) { /* int 21 */
80		- do_IRQ(COBALT_SERIAL_IRQ, regs);
81		- return;
	68	+ GALILEO_OUTL(mask & ~pending, GT_INTRMASK_OFS);
	69	+ printk(KERN_WARNING "Galileo: masking unexpected interrupt %08x\n", pending);
82	70	}
	71	+}
83	72
84		- if (pending & CAUSEF_IP7) { /* int 23 */
85		- do_IRQ(COBALT_QUBE_SLOT_IRQ, regs);
86		- return;
87		- }
	73	+static inline void via_pic_irq(struct pt_regs *regs)
	74	+{
	75	+ int irq;
	76	+
	77	+ irq = i8259_irq();
	78	+ if (irq >= 0)
	79	+ do_IRQ(irq, regs);
88	80	}
89	81
	82	+asmlinkage void cobalt_irq(struct pt_regs *regs)
	83	+{
	84	+ unsigned pending;
	85	+
	86	+ pending = read_c0_status() & read_c0_cause();
	87	+
	88	+ if (pending & CAUSEF_IP2) /* COBALT_GALILEO_IRQ (18) */
	89	+
	90	+ galileo_irq(regs);
	91	+
	92	+ else if (pending & CAUSEF_IP6) /* COBALT_VIA_IRQ (22) */
	93	+
	94	+ via_pic_irq(regs);
	95	+
	96	+ else if (pending & CAUSEF_IP3) /* COBALT_ETH0_IRQ (19) */
	97	+
	98	+ do_IRQ(COBALT_CPU_IRQ + 3, regs);
	99	+
	100	+ else if (pending & CAUSEF_IP4) /* COBALT_ETH1_IRQ (20) */
	101	+
	102	+ do_IRQ(COBALT_CPU_IRQ + 4, regs);
	103	+
	104	+ else if (pending & CAUSEF_IP5) /* COBALT_SERIAL_IRQ (21) */
	105	+
	106	+ do_IRQ(COBALT_CPU_IRQ + 5, regs);
	107	+
	108	+ else if (pending & CAUSEF_IP7) /* IRQ 23 */
	109	+
	110	+ do_IRQ(COBALT_CPU_IRQ + 7, regs);
	111	+}
	112	+
	113	+static struct irqaction irq_via = {
	114	+ no_action, 0, { { 0, } }, "cascade", NULL, NULL
	115	+};
	116	+
90	117	void __init arch_init_irq(void)
91	118	{
	119	+ /*
	120	+ * Mask all Galileo interrupts. The Galileo
	121	+ * handler is set in cobalt_timer_setup()
	122	+ */
	123	+ GALILEO_OUTL(0, GT_INTRMASK_OFS);
	124	+
92	125	set_except_vector(0, cobalt_handle_int);
93	126
94	127	init_i8259_irqs(); /* 0 ... 15 */
95		- mips_cpu_irq_init(16); /* 16 ... 23 */
	128	+ mips_cpu_irq_init(COBALT_CPU_IRQ); /* 16 ... 23 */
96	129
97	130	/*
98	131	* Mask all cpu interrupts
99	132	* (except IE4, we already masked those at VIA level)
100	133	*/
101	134	change_c0_status(ST0_IM, IE_IRQ4);
	135	+
	136	+ setup_irq(COBALT_VIA_IRQ, &irq_via);
102	137	}
1		-/*
2		- * PROM console for Cobalt Raq2
3		- *
4		- * This file is subject to the terms and conditions of the GNU General Public
5		- * License. See the file "COPYING" in the main directory of this archive
6		- * for more details.
7		- *
8		- * Copyright (C) 1995, 1996, 1997 by Ralf Baechle
9		- * Copyright (C) 2001 by Liam Davies (ldavies@agile.tv)
10		- *
11		- */
12		-
13		-#include <linux/init.h>
14		-#include <linux/console.h>
15		-#include <linux/kdev_t.h>
16		-#include <linux/serial_reg.h>
17		-
18		-#include <asm/delay.h>
19		-#include <asm/serial.h>
20		-#include <asm/io.h>
21		-
22		-static unsigned long port = 0xc800000;
23		-
24		-static __inline__ void ns16550_cons_put_char(char ch, unsigned long ioaddr)
25		-{
26		- char lsr;
27		-
28		- do {
29		- lsr = inb(ioaddr + UART_LSR);
30		- } while ((lsr & (UART_LSR_TEMT \| UART_LSR_THRE)) != (UART_LSR_TEMT \| UART_LSR_THRE));
31		- outb(ch, ioaddr + UART_TX);
32		-}
33		-
34		-static __inline__ char ns16550_cons_get_char(unsigned long ioaddr)
35		-{
36		- while ((inb(ioaddr + UART_LSR) & UART_LSR_DR) == 0)
37		- udelay(1);
38		- return inb(ioaddr + UART_RX);
39		-}
40		-
41		-void ns16550_console_write(struct console co, const char s, unsigned count)
42		-{
43		- char lsr, ier;
44		- unsigned i;
45		-
46		- ier = inb(port + UART_IER);
47		- outb(0x00, port + UART_IER);
48		- for (i=0; i < count; i++, s++) {
49		-
50		- if(*s == '\n')
51		- ns16550_cons_put_char('\r', port);
52		- ns16550_cons_put_char(*s, port);
53		- }
54		-
55		- do {
56		- lsr = inb(port + UART_LSR);
57		- } while ((lsr & (UART_LSR_TEMT \| UART_LSR_THRE)) != (UART_LSR_TEMT \| UART_LSR_THRE));
58		-
59		- outb(ier, port + UART_IER);
60		-}
61		-
62		-char getDebugChar(void)
63		-{
64		- return ns16550_cons_get_char(port);
65		-}
66		-
67		-void putDebugChar(char kgdb_char)
68		-{
69		- ns16550_cons_put_char(kgdb_char, port);
70		-}
71		-
72		-static struct console ns16550_console = {
73		- .name = "prom",
74		- .setup = NULL,
75		- .write = ns16550_console_write,
76		- .flags = CON_PRINTBUFFER,
77		- .index = -1,
78		-};
79		-
80		-static int __init ns16550_setup_console(void)
81		-{
82		- register_console(&ns16550_console);
83		-
84		- return 0;
85		-}
86		-
87		-console_initcall(ns16550_setup_console);
...	...	@@ -16,46 +16,43 @@
16	16	#include <asm/reboot.h>
17	17	#include <asm/system.h>
18	18	#include <asm/mipsregs.h>
	19	+#include <asm/cobalt/cobalt.h>
19	20
20		-void cobalt_machine_restart(char *command)
	21	+void cobalt_machine_halt(void)
21	22	{
22		- (volatile char )0xbc000000 = 0x0f;
	23	+ int state, last, diff;
	24	+ unsigned long mark;
23	25
24	26	/*
25		- * Ouch, we're still alive ... This time we take the silver bullet ...
26		- * ... and find that we leave the hardware in a state in which the
27		- * kernel in the flush locks up somewhen during of after the PCI
28		- * detection stuff.
	27	+ * turn off bar on Qube, flash power off LED on RaQ (0.5Hz)
	28	+ *
	29	+ * restart if ENTER and SELECT are pressed
29	30	*/
30		- set_c0_status(ST0_BEV \| ST0_ERL);
31		- change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
32		- flush_cache_all();
33		- write_c0_wired(0);
34		- __asm__ __volatile__(
35		- "jr\t%0"
36		- :
37		- : "r" (0xbfc00000));
38		-}
39	31
40		-extern int led_state;
41		-#define kLED 0xBC000000
42		-#define LEDSet(x) ((volatile unsigned char ) kLED) = (( unsigned char)x)
	32	+ last = COBALT_KEY_PORT;
43	33
44		-void cobalt_machine_halt(void)
45		-{
46		- int mark;
	34	+ for (state = 0;;) {
47	35
48		- /* Blink our cute? little LED (number 3)... */
49		- while (1) {
50		- led_state = led_state \| ( 1 << 3 );
51		- LEDSet(led_state);
52		- mark = jiffies;
53		- while (jiffies<(mark+HZ));
54		- led_state = led_state & ~( 1 << 3 );
55		- LEDSet(led_state);
56		- mark = jiffies;
57		- while (jiffies<(mark+HZ));
	36	+ state ^= COBALT_LED_POWER_OFF;
	37	+ COBALT_LED_PORT = state;
	38	+
	39	+ diff = COBALT_KEY_PORT ^ last;
	40	+ last ^= diff;
	41	+
	42	+ if((diff & (COBALT_KEY_ENTER \| COBALT_KEY_SELECT)) && !(~last & (COBALT_KEY_ENTER \| COBALT_KEY_SELECT)))
	43	+ COBALT_LED_PORT = COBALT_LED_RESET;
	44	+
	45	+ for (mark = jiffies; jiffies - mark < HZ;)
	46	+ ;
58	47	}
	48	+}
	49	+
	50	+void cobalt_machine_restart(char *command)
	51	+{
	52	+ COBALT_LED_PORT = COBALT_LED_RESET;
	53	+
	54	+ /* we should never get here */
	55	+ cobalt_machine_halt();
59	56	}
60	57
61	58	/*
...	...	@@ -13,6 +13,8 @@
13	13	#include <linux/interrupt.h>
14	14	#include <linux/pci.h>
15	15	#include <linux/init.h>
	16	+#include <linux/serial.h>
	17	+#include <linux/serial_core.h>
16	18
17	19	#include <asm/bootinfo.h>
18	20	#include <asm/time.h>
...	...	@@ -21,6 +23,7 @@
21	23	#include <asm/processor.h>
22	24	#include <asm/reboot.h>
23	25	#include <asm/gt64120.h>
	26	+#include <asm/serial.h>
24	27
25	28	#include <asm/cobalt/cobalt.h>
26	29
27	30
28	31
29	32
30	33
31	34
32	35
...	...	@@ -30,45 +33,44 @@
30	33
31	34	int cobalt_board_id;
32	35
33		-static char my_cmdline[CL_SIZE] = {
34		- "console=ttyS0,115200 "
35		-#ifdef CONFIG_IP_PNP
36		- "ip=on "
37		-#endif
38		-#ifdef CONFIG_ROOT_NFS
39		- "root=/dev/nfs "
40		-#else
41		- "root=/dev/hda1 "
42		-#endif
43		- };
44		-
45	36	const char *get_system_type(void)
46	37	{
	38	+ switch (cobalt_board_id) {
	39	+ case COBALT_BRD_ID_QUBE1:
	40	+ return "Cobalt Qube";
	41	+ case COBALT_BRD_ID_RAQ1:
	42	+ return "Cobalt RaQ";
	43	+ case COBALT_BRD_ID_QUBE2:
	44	+ return "Cobalt Qube2";
	45	+ case COBALT_BRD_ID_RAQ2:
	46	+ return "Cobalt RaQ2";
	47	+ }
47	48	return "MIPS Cobalt";
48	49	}
49	50
50	51	static void __init cobalt_timer_setup(struct irqaction *irq)
51	52	{
52		- /* Load timer value for 150 Hz */
53		- GALILEO_OUTL(500000, GT_TC0_OFS);
	53	+ /* Load timer value for 1KHz (TCLK is 50MHz) */
	54	+ GALILEO_OUTL(5010001000 / 1000, GT_TC0_OFS);
54	55
55		- /* Register our timer interrupt */
56		- setup_irq(COBALT_TIMER_IRQ, irq);
	56	+ /* Enable timer */
	57	+ GALILEO_OUTL(GALILEO_ENTC0 \| GALILEO_SELTC0, GT_TC_CONTROL_OFS);
57	58
58		- /* Enable timer ints */
59		- GALILEO_OUTL((GALILEO_ENTC0 \| GALILEO_SELTC0), GT_TC_CONTROL_OFS);
60		- /* Unmask timer int */
61		- GALILEO_OUTL(0x100, GT_INTRMASK_OFS);
	59	+ /* Register interrupt */
	60	+ setup_irq(COBALT_GALILEO_IRQ, irq);
	61	+
	62	+ /* Enable interrupt */
	63	+ GALILEO_OUTL(GALILEO_INTR_T0EXP \| GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS);
62	64	}
63	65
64	66	extern struct pci_ops gt64111_pci_ops;
65	67
66	68	static struct resource cobalt_mem_resource = {
67		- "GT64111 PCI MEM", GT64111_IO_BASE, 0xffffffffUL, IORESOURCE_MEM
	69	+ "PCI memory", GT64111_MEM_BASE, GT64111_MEM_END, IORESOURCE_MEM
68	70	};
69	71
70	72	static struct resource cobalt_io_resource = {
71		- "GT64111 IO MEM", 0x00001000UL, 0x0fffffffUL, IORESOURCE_IO
	73	+ "PCI I/O", 0x1000, 0xffff, IORESOURCE_IO
72	74	};
73	75
74	76	static struct resource cobalt_io_resources[] = {
75	77
...	...	@@ -86,11 +88,12 @@
86	88	.mem_resource = &cobalt_mem_resource,
87	89	.mem_offset = 0,
88	90	.io_resource = &cobalt_io_resource,
89		- .io_offset = 0x00001000UL - GT64111_IO_BASE
	91	+ .io_offset = 0 - GT64111_IO_BASE
90	92	};
91	93
92	94	void __init plat_setup(void)
93	95	{
	96	+ static struct uart_port uart;
94	97	unsigned int devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0);
95	98	int i;
96	99
97	100
...	...	@@ -100,8 +103,11 @@
100	103
101	104	board_timer_setup = cobalt_timer_setup;
102	105
103		- set_io_port_base(KSEG1ADDR(GT64111_IO_BASE));
	106	+ set_io_port_base(CKSEG1ADDR(GT64111_IO_BASE));
104	107
	108	+ /* I/O port resource must include UART and LCD/buttons */
	109	+ ioport_resource.end = 0x0fffffff;
	110	+
105	111	/*
106	112	* This is a prom style console. We just poke at the
107	113	* UART to make it talk.
108	114
109	115
110	116
111	117
112	118
...	...	@@ -120,25 +126,61 @@
120	126	cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8);
121	127	cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id);
122	128
	129	+ printk("Cobalt board ID: %d\n", cobalt_board_id);
	130	+
123	131	#ifdef CONFIG_PCI
124	132	register_pci_controller(&cobalt_pci_controller);
125	133	#endif
	134	+
	135	+#ifdef CONFIG_SERIAL_8250
	136	+ if (cobalt_board_id > COBALT_BRD_ID_RAQ1) {
	137	+
	138	+ uart.line = 0;
	139	+ uart.type = PORT_UNKNOWN;
	140	+ uart.uartclk = 18432000;
	141	+ uart.irq = COBALT_SERIAL_IRQ;
	142	+ uart.flags = STD_COM_FLAGS;
	143	+ uart.iobase = 0xc800000;
	144	+ uart.iotype = UPIO_PORT;
	145	+
	146	+ early_serial_setup(&uart);
	147	+ }
	148	+#endif
126	149	}
127	150
128	151	/*
129	152	* Prom init. We read our one and only communication with the firmware.
130		- * Grab the amount of installed memory
	153	+ * Grab the amount of installed memory.
	154	+ * Better boot loaders (CoLo) pass a command line too :-)
131	155	*/
132	156
133	157	void __init prom_init(void)
134	158	{
135		- int argc = fw_arg0;
	159	+ int narg, indx, posn, nchr;
	160	+ unsigned long memsz;
	161	+ char **argv;
136	162
137		- strcpy(arcs_cmdline, my_cmdline);
138		-
139	163	mips_machgroup = MACH_GROUP_COBALT;
140	164
141		- add_memory_region(0x0, argc & 0x7fffffff, BOOT_MEM_RAM);
	165	+ memsz = fw_arg0 & 0x7fff0000;
	166	+ narg = fw_arg0 & 0x0000ffff;
	167	+
	168	+ if (narg) {
	169	+ arcs_cmdline[0] = '\0';
	170	+ argv = (char **) fw_arg1;
	171	+ posn = 0;
	172	+ for (indx = 1; indx < narg; ++indx) {
	173	+ nchr = strlen(argv[indx]);
	174	+ if (posn + 1 + nchr + 1 > sizeof(arcs_cmdline))
	175	+ break;
	176	+ if (posn)
	177	+ arcs_cmdline[posn++] = ' ';
	178	+ strcpy(arcs_cmdline + posn, argv[indx]);
	179	+ posn += nchr;
	180	+ }
	181	+ }
	182	+
	183	+ add_memory_region(0x0, memsz, BOOT_MEM_RAM);
142	184	}
143	185
144	186	unsigned long __init prom_free_prom_memory(void)
...	...	@@ -21,6 +21,20 @@
21	21
22	22	extern int cobalt_board_id;
23	23
	24	+static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
	25	+{
	26	+ if (dev->devfn == PCI_DEVFN(0, 0) &&
	27	+ (dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) {
	28	+
	29	+ dev->class = (PCI_CLASS_BRIDGE_HOST << 8) \| (dev->class & 0xff);
	30	+
	31	+ printk(KERN_INFO "Galileo: fixed bridge class\n");
	32	+ }
	33	+}
	34	+
	35	+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
	36	+ qube_raq_galileo_early_fixup);
	37	+
24	38	static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
25	39	{
26	40	unsigned short cfgword;
...	...	@@ -48,6 +62,9 @@
48	62	{
49	63	unsigned short galileo_id;
50	64
	65	+ if (dev->devfn != PCI_DEVFN(0, 0))
	66	+ return;
	67	+
51	68	/* Fix PCI latency-timer and cache-line-size values in Galileo
52	69	* host bridge.
53	70	*/
...	...	@@ -55,6 +72,13 @@
55	72	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
56	73
57	74	/*
	75	+ * The code described by the comment below has been removed
	76	+ * as it causes bus mastering by the Ethernet controllers
	77	+ * to break under any kind of network load. We always set
	78	+ * the retry timeouts to their maximum.
	79	+ *
	80	+ * --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--
	81	+ *
58	82	* On all machines prior to Q2, we had the STOP line disconnected
59	83	* from Galileo to VIA on PCI. The new Galileo does not function
60	84	* correctly unless we have it connected.
61	85
62	86
63	87
64	88
...	...	@@ -64,21 +88,43 @@
64	88	*/
65	89	pci_read_config_word(dev, PCI_REVISION_ID, &galileo_id);
66	90	galileo_id &= 0xff; /* mask off class info */
	91	+
	92	+ printk(KERN_INFO "Galileo: revision %u\n", galileo_id);
	93	+
	94	+#if 0
67	95	if (galileo_id >= 0x10) {
68	96	/* New Galileo, assumes PCI stop line to VIA is connected. */
69	97	GALILEO_OUTL(0x4020, GT_PCI0_TOR_OFS);
70		- } else if (galileo_id == 0x1 \|\| galileo_id == 0x2) {
	98	+ } else if (galileo_id == 0x1 \|\| galileo_id == 0x2)
	99	+#endif
	100	+ {
71	101	signed int timeo;
72	102	/* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
73	103	timeo = GALILEO_INL(GT_PCI0_TOR_OFS);
74	104	/* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
75		- GALILEO_OUTL(0xffff, GT_PCI0_TOR_OFS);
	105	+ GALILEO_OUTL(
	106	+ (0xff << 16) \| /* retry count */
	107	+ (0xff << 8) \| /* timeout 1 */
	108	+ 0xff, /* timeout 0 */
	109	+ GT_PCI0_TOR_OFS);
	110	+
	111	+ /* enable PCI retry exceeded interrupt */
	112	+ GALILEO_OUTL(GALILEO_INTR_RETRY_CTR \| GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS);
76	113	}
77	114	}
78	115
79		-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GALILEO, PCI_ANY_ID,
	116	+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
80	117	qube_raq_galileo_fixup);
81	118
	119	+static char irq_tab_qube1[] __initdata = {
	120	+ [COBALT_PCICONF_CPU] = 0,
	121	+ [COBALT_PCICONF_ETH0] = COBALT_QUBE1_ETH0_IRQ,
	122	+ [COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ,
	123	+ [COBALT_PCICONF_VIA] = 0,
	124	+ [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ,
	125	+ [COBALT_PCICONF_ETH1] = 0
	126	+};
	127	+
82	128	static char irq_tab_cobalt[] __initdata = {
83	129	[COBALT_PCICONF_CPU] = 0,
84	130	[COBALT_PCICONF_ETH0] = COBALT_ETH0_IRQ,
...	...	@@ -99,6 +145,9 @@
99	145
100	146	int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
101	147	{
	148	+ if (cobalt_board_id < COBALT_BRD_ID_QUBE2)
	149	+ return irq_tab_qube1[slot];
	150	+
102	151	if (cobalt_board_id == COBALT_BRD_ID_RAQ2)
103	152	return irq_tab_raq2[slot];
104	153
...	...	@@ -18,15 +18,15 @@
18	18	#include <asm/cobalt/cobalt.h>
19	19
20	20	/*
21		- * Accessing device 31 hangs the GT64120. Not sure if this will also hang
22		- * the GT64111, let's be paranoid for now.
	21	+ * Device 31 on the GT64111 is used to generate PCI special
	22	+ * cycles, so we shouldn't expected to find a device there ...
23	23	*/
24	24	static inline int pci_range_ck(struct pci_bus *bus, unsigned int devfn)
25	25	{
26		- if (bus->number == 0 && devfn == PCI_DEVFN(31, 0))
27		- return -1;
	26	+ if (bus->number == 0 && PCI_SLOT(devfn) < 31)
	27	+ return 0;
28	28
29		- return 0;
	29	+ return -1;
30	30	}
31	31
32	32	static int gt64111_pci_read_config(struct pci_bus *bus, unsigned int devfn,
...	...	@@ -575,8 +575,8 @@
575	575
576	576	static int lcd_waiters = 0;
577	577
578		-static long lcd_read(struct inode inode, struct file file, char *buf,
579		- unsigned long count)
	578	+static ssize_t lcd_read(struct file file, char buf,
	579	+ size_t count, loff_t *ofs)
580	580	{
581	581	long buttons_now;
582	582