Commit cbc4dbffc89fbaada94ae7873ad6631a701fd00e
Committed by
Russell King
1 parent
b2627588cb
[ARM] 4512/1: S3C: rename the debug macros for per-cpu updates
Update the debug macros for use with the new per-cpu configuration and usage. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Showing 2 changed files with 53 additions and 6 deletions Side-by-side Diff
include/asm-arm/arch-s3c2410/debug-macro.S
... | ... | @@ -14,9 +14,7 @@ |
14 | 14 | |
15 | 15 | #include <asm/arch/map.h> |
16 | 16 | #include <asm/arch/regs-gpio.h> |
17 | - | |
18 | 17 | #include <asm/plat-s3c/regs-serial.h> |
19 | -#include <asm/plat-s3c/debug-macro.S> | |
20 | 18 | |
21 | 19 | #define S3C2410_UART1_OFF (0x4000) |
22 | 20 | #define SHIFT_2440TXF (14-9) |
... | ... | @@ -31,7 +29,7 @@ |
31 | 29 | #endif |
32 | 30 | .endm |
33 | 31 | |
34 | - .macro fifo_full rd, rx | |
32 | + .macro fifo_full_s3c24xx rd, rx | |
35 | 33 | @ check for arm920 vs arm926. currently assume all arm926 |
36 | 34 | @ devices have an 64 byte FIFO identical to the s3c2440 |
37 | 35 | mrc p15, 0, \rd, c0, c0 |
... | ... | @@ -52,7 +50,14 @@ |
52 | 50 | tst \rd, #S3C2410_UFSTAT_TXFULL |
53 | 51 | .endm |
54 | 52 | |
55 | - .macro fifo_level rd, rx | |
53 | + .macro fifo_full_s3c2410 rd, rx | |
54 | + ldr \rd, [ \rx, # S3C2410_UFSTAT ] | |
55 | + tst \rd, #S3C2410_UFSTAT_TXFULL | |
56 | + .endm | |
57 | + | |
58 | +/* fifo level reading */ | |
59 | + | |
60 | + .macro fifo_level_s3c24xx rd, rx | |
56 | 61 | mrc p15, 0, \rd, c1, c0 |
57 | 62 | tst \rd, #1 |
58 | 63 | addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART) |
... | ... | @@ -66,4 +71,28 @@ |
66 | 71 | andne \rd, \rd, #S3C2410_UFSTAT_TXMASK |
67 | 72 | andeq \rd, \rd, #S3C2440_UFSTAT_TXMASK |
68 | 73 | .endm |
74 | + | |
75 | + .macro fifo_level_s3c2410 rd, rx | |
76 | + ldr \rd, [ \rx, # S3C2410_UFSTAT ] | |
77 | + and \rd, \rd, #S3C2410_UFSTAT_TXMASK | |
78 | + .endm | |
79 | + | |
80 | +/* Select the correct implementation depending on the configuration. The | |
81 | + * S3C2440 will get selected by default, as these are the most widely | |
82 | + * used variants of these | |
83 | +*/ | |
84 | + | |
85 | +#if defined(CONFIG_CPU_LLSERIAL_S3C2410_ONLY) | |
86 | +#define fifo_full fifo_full_s3c2410 | |
87 | +#define fifo_level fifo_level_s3c2410 | |
88 | +#warning 2410only | |
89 | +#elif !defined(CONFIG_CPU_LLSERIAL_S3C2440_ONLY) | |
90 | +#define fifo_full fifo_full_s3c24xx | |
91 | +#define fifo_level fifo_level_s3c24xx | |
92 | +#warning generic | |
93 | +#endif | |
94 | + | |
95 | +/* include the reset of the code which will do the work */ | |
96 | + | |
97 | +#include <asm/plat-s3c/debug-macro.S> |
include/asm-arm/plat-s3c/debug-macro.S
... | ... | @@ -11,8 +11,27 @@ |
11 | 11 | |
12 | 12 | #include <asm/plat-s3c/regs-serial.h> |
13 | 13 | |
14 | -#define S3C2410_UART1_OFF (0x4000) | |
14 | +/* The S3C2440 implementations are used by default as they are the | |
15 | + * most widely re-used */ | |
15 | 16 | |
17 | + .macro fifo_level_s3c2440 rd, rx | |
18 | + ldr \rd, [ \rx, # S3C2410_UFSTAT ] | |
19 | + and \rd, \rd, #S3C2440_UFSTAT_TXMASK | |
20 | + .endm | |
21 | + | |
22 | +#ifndef fifo_level | |
23 | +#define fifo_level fifo_level_s3c2410 | |
24 | +#endif | |
25 | + | |
26 | + .macro fifo_full_s3c2440 rd, rx | |
27 | + ldr \rd, [ \rx, # S3C2410_UFSTAT ] | |
28 | + tst \rd, #S3C2440_UFSTAT_TXFULL | |
29 | + .endm | |
30 | + | |
31 | +#ifndef fifo_full | |
32 | +#define fifo_full fifo_full_s3c2440 | |
33 | +#endif | |
34 | + | |
16 | 35 | .macro senduart,rd,rx |
17 | 36 | strb \rd, [\rx, # S3C2410_UTXH ] |
18 | 37 | .endm |
... | ... | @@ -37,7 +56,6 @@ |
37 | 56 | .endm |
38 | 57 | |
39 | 58 | .macro waituart,rd,rx |
40 | - | |
41 | 59 | ldr \rd, [ \rx, # S3C2410_UFCON ] |
42 | 60 | tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled? |
43 | 61 | beq 1001f @ |