Eric Lee / smarc-fsl-linux-kernel

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Commit d25cf2c7a057d6c01e44d4696fde1d05bfec11bb

Authored by Jack Xu
Committed by Herbert Xu
1 parent 49c1327328

crypto: qat - add next neighbor to chip_info 

Introduce the next neighbor (NN) capability in chip_info as NN registers
are not supported in certain SKUs of QAT.

Signed-off-by: Jack Xu <jack.xu@intel.com>
Co-developed-by: Wojciech Ziemba <wojciech.ziemba@intel.com>
Signed-off-by: Wojciech Ziemba <wojciech.ziemba@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Showing 3 changed files with 18 additions and 6 deletions Side-by-side Diff

drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h
Diff comments   View file @ d25cf2c
... ... @@ -24,6 +24,7 @@
24 24  
25 25 struct icp_qat_fw_loader_chip_info {
26 26 bool sram_visible;
  27 + bool nn;
27 28 bool fw_auth;
28 29 };
29 30  
drivers/crypto/qat/qat_common/qat_hal.c
Diff comments   View file @ d25cf2c
... ... @@ -603,7 +603,9 @@
603 603 qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, csr_val);
604 604 csr_val = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES);
605 605 csr_val &= IGNORE_W1C_MASK;
606   - csr_val |= CE_NN_MODE;
  606 + if (handle->chip_info->nn)
  607 + csr_val |= CE_NN_MODE;
  608 +
607 609 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, csr_val);
608 610 qat_hal_wr_uwords(handle, ae, 0, ARRAY_SIZE(inst),
609 611 (u64 *)inst);
610 612  
... ... @@ -665,10 +667,12 @@
665 667 case PCI_DEVICE_ID_INTEL_QAT_C62X:
666 668 case PCI_DEVICE_ID_INTEL_QAT_C3XXX:
667 669 handle->chip_info->sram_visible = false;
  670 + handle->chip_info->nn = true;
668 671 handle->chip_info->fw_auth = true;
669 672 break;
670 673 case PCI_DEVICE_ID_INTEL_QAT_DH895XCC:
671 674 handle->chip_info->sram_visible = true;
  675 + handle->chip_info->nn = true;
672 676 handle->chip_info->fw_auth = false;
673 677 break;
674 678 default:
... ... @@ -1433,6 +1437,11 @@
1433 1437 {
1434 1438 int stat = 0;
1435 1439 unsigned char ctx;
  1440 + if (!handle->chip_info->nn) {
  1441 + dev_err(&handle->pci_dev->dev, "QAT: No next neigh in 0x%x\n",
  1442 + handle->pci_dev->device);
  1443 + return -EINVAL;
  1444 + }
1436 1445  
1437 1446 if (ctx_mask == 0)
1438 1447 return -EINVAL;
drivers/crypto/qat/qat_common/qat_uclo.c
Diff comments   View file @ d25cf2c
... ... @@ -884,11 +884,13 @@
884 884 pr_err("QAT: qat_hal_set_ae_ctx_mode error\n");
885 885 return ret;
886 886 }
887   - mode = ICP_QAT_NN_MODE(uof_image->ae_mode);
888   - ret = qat_hal_set_ae_nn_mode(handle, ae, mode);
889   - if (ret) {
890   - pr_err("QAT: qat_hal_set_ae_nn_mode error\n");
891   - return ret;
  887 + if (handle->chip_info->nn) {
  888 + mode = ICP_QAT_NN_MODE(uof_image->ae_mode);
  889 + ret = qat_hal_set_ae_nn_mode(handle, ae, mode);
  890 + if (ret) {
  891 + pr_err("QAT: qat_hal_set_ae_nn_mode error\n");
  892 + return ret;
  893 + }
892 894 }
893 895 mode = ICP_QAT_LOC_MEM0_MODE(uof_image->ae_mode);
894 896 ret = qat_hal_set_ae_lm_mode(handle, ae, ICP_LMEM0, mode);